isa_traits.hh revision 2665
12SN/A/* 21458SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Gabe Black 302SN/A */ 312SN/A 321147SN/A#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 331147SN/A#define __ARCH_ALPHA_ISA_TRAITS_HH__ 342SN/A 352037SN/Anamespace LittleEndianGuest {} 362037SN/A 372428SN/A#include "arch/alpha/types.hh" 382431SN/A#include "arch/alpha/constants.hh" 392460SN/A#include "arch/alpha/regfile.hh" 401858SN/A#include "config/full_system.hh" 4156SN/A#include "sim/host.hh" 422SN/A 432107SN/Aclass StaticInstPtr; 442SN/A 452238SN/A#if !FULL_SYSTEM 462238SN/Aclass SyscallReturn { 472238SN/A public: 482238SN/A template <class T> 492238SN/A SyscallReturn(T v, bool s) 502238SN/A { 512238SN/A retval = (uint64_t)v; 522238SN/A success = s; 532238SN/A } 542238SN/A 552238SN/A template <class T> 562238SN/A SyscallReturn(T v) 572238SN/A { 582238SN/A success = (v >= 0); 592238SN/A retval = (uint64_t)v; 602238SN/A } 612238SN/A 622238SN/A ~SyscallReturn() {} 632238SN/A 642238SN/A SyscallReturn& operator=(const SyscallReturn& s) { 652238SN/A retval = s.retval; 662238SN/A success = s.success; 672238SN/A return *this; 682238SN/A } 692238SN/A 702238SN/A bool successful() { return success; } 712238SN/A uint64_t value() { return retval; } 722238SN/A 732238SN/A 742238SN/A private: 752238SN/A uint64_t retval; 762238SN/A bool success; 772238SN/A}; 782238SN/A 792238SN/A#endif 802238SN/A 812512SN/A#if FULL_SYSTEM 822512SN/A#include "arch/alpha/isa_fullsys_traits.hh" 832512SN/A#endif 842512SN/A 852512SN/A 862107SN/Anamespace AlphaISA 872SN/A{ 882SN/A 892449SN/Ausing namespace LittleEndianGuest; 902449SN/A 912227SN/A// redirected register map, really only used for the full system case. 922227SN/Aextern const int reg_redir[NumIntRegs]; 932227SN/A 942227SN/A StaticInstPtr decodeInst(ExtMachInst); 952SN/A 962265SN/A#if !FULL_SYSTEM 972238SN/A static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 982238SN/A { 992238SN/A // check for error condition. Alpha syscall convention is to 1002238SN/A // indicate success/failure in reg a3 (r19) and put the 1012238SN/A // return value itself in the standard return value reg (v0). 1022238SN/A if (return_value.successful()) { 1032238SN/A // no error 1042525SN/A regs->setIntReg(SyscallSuccessReg, 0); 1052525SN/A regs->setIntReg(ReturnValueReg, return_value.value()); 1062238SN/A } else { 1072238SN/A // got an error, return details 1082525SN/A regs->setIntReg(SyscallSuccessReg, (IntReg)-1); 1092525SN/A regs->setIntReg(ReturnValueReg, -return_value.value()); 1102238SN/A } 1112238SN/A } 1122265SN/A#endif 1132264SN/A}; 1142107SN/A 1151147SN/A#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 116