isa_traits.hh revision 2238
12330SN/A/* 22330SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32330SN/A * All rights reserved. 42330SN/A * 52330SN/A * Redistribution and use in source and binary forms, with or without 62330SN/A * modification, are permitted provided that the following conditions are 72330SN/A * met: redistributions of source code must retain the above copyright 82330SN/A * notice, this list of conditions and the following disclaimer; 92330SN/A * redistributions in binary form must reproduce the above copyright 102330SN/A * notice, this list of conditions and the following disclaimer in the 112330SN/A * documentation and/or other materials provided with the distribution; 122330SN/A * neither the name of the copyright holders nor the names of its 132330SN/A * contributors may be used to endorse or promote products derived from 142330SN/A * this software without specific prior written permission. 152330SN/A * 162330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu */ 282689Sktlim@umich.edu 292330SN/A#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 302292SN/A#define __ARCH_ALPHA_ISA_TRAITS_HH__ 312292SN/A 322292SN/Anamespace LittleEndianGuest {} 332292SN/Ausing namespace LittleEndianGuest; 342980Sgblack@eecs.umich.edu 356658Snate@binkert.org//#include "arch/alpha/faults.hh" 368229Snate@binkert.org#include "base/misc.hh" 372362SN/A#include "config/full_system.hh" 382680Sktlim@umich.edu#include "sim/host.hh" 392683Sktlim@umich.edu#include "sim/faults.hh" 402678Sktlim@umich.edu 412292SN/Aclass ExecContext; 422292SN/Aclass FastCPU; 432292SN/Aclass FullCPU; 4413905Sgabeblack@google.comclass Checkpoint; 4513905Sgabeblack@google.com 468902Sandreas.hansson@arm.com#define TARGET_ALPHA 472292SN/A 482862Sktlim@umich.educlass StaticInst; 492862Sktlim@umich.educlass StaticInstPtr; 502330SN/A 512330SN/Anamespace EV5 { 522330SN/Aint DTB_ASN_ASN(uint64_t reg); 532330SN/Aint ITB_ASN_ASN(uint64_t reg); 542330SN/A} 552330SN/A 5610905Sandreas.sandberg@arm.com#if !FULL_SYSTEM 572683Sktlim@umich.educlass SyscallReturn { 582683Sktlim@umich.edu public: 596331Sgblack@eecs.umich.edu template <class T> 602683Sktlim@umich.edu SyscallReturn(T v, bool s) 618735Sandreas.hanson@arm.com { 623486Sktlim@umich.edu retval = (uint64_t)v; 6311168Sandreas.hansson@arm.com success = s; 642862Sktlim@umich.edu } 6511168Sandreas.hansson@arm.com 662862Sktlim@umich.edu template <class T> 6710110Sandreas.hansson@arm.com SyscallReturn(T v) 682683Sktlim@umich.edu { 6910190Sakash.bagdia@arm.com success = (v >= 0); 7010190Sakash.bagdia@arm.com retval = (uint64_t)v; 7111005Sandreas.sandberg@arm.com } 725714Shsul@eecs.umich.edu 7311005Sandreas.sandberg@arm.com ~SyscallReturn() {} 745714Shsul@eecs.umich.edu 756221Snate@binkert.org SyscallReturn& operator=(const SyscallReturn& s) { 762683Sktlim@umich.edu retval = s.retval; 7710110Sandreas.hansson@arm.com success = s.success; 782683Sktlim@umich.edu return *this; 7910110Sandreas.hansson@arm.com } 802683Sktlim@umich.edu 8110110Sandreas.hansson@arm.com bool successful() { return success; } 822683Sktlim@umich.edu uint64_t value() { return retval; } 838706Sandreas.hansson@arm.com 848706Sandreas.hansson@arm.com 858706Sandreas.hansson@arm.com private: 868706Sandreas.hansson@arm.com uint64_t retval; 878921Sandreas.hansson@arm.com bool success; 888706Sandreas.hansson@arm.com}; 898706Sandreas.hansson@arm.com 903675Sktlim@umich.edu#endif 912683Sktlim@umich.edu 922683Sktlim@umich.edu 932683Sktlim@umich.edu 942683Sktlim@umich.edunamespace AlphaISA 952683Sktlim@umich.edu{ 962683Sktlim@umich.edu 972683Sktlim@umich.edu typedef uint32_t MachInst; 982683Sktlim@umich.edu typedef uint64_t ExtMachInst; 9913905Sgabeblack@google.com typedef uint8_t RegIndex; 1002683Sktlim@umich.edu 1019101SBrad.Beckmann@amd.com enum { 1022690Sktlim@umich.edu MemoryEnd = 0xffffffffffffffffULL, 1039101SBrad.Beckmann@amd.com 1048799Sgblack@eecs.umich.edu NumIntArchRegs = 32, 1052683Sktlim@umich.edu NumPALShadowRegs = 8, 1062683Sktlim@umich.edu NumFloatArchRegs = 32, 10711886Sbrandon.potter@amd.com // @todo: Figure out what this number really should be. 10811886Sbrandon.potter@amd.com NumMiscArchRegs = 32, 10911886Sbrandon.potter@amd.com 11011886Sbrandon.potter@amd.com MaxRegsOfAnyType = 32, 11111886Sbrandon.potter@amd.com // Static instruction parameters 11211886Sbrandon.potter@amd.com MaxInstSrcRegs = 3, 11311886Sbrandon.potter@amd.com MaxInstDestRegs = 2, 11411886Sbrandon.potter@amd.com 11511886Sbrandon.potter@amd.com // semantically meaningful register indices 11611886Sbrandon.potter@amd.com ZeroReg = 31, // architecturally meaningful 11711886Sbrandon.potter@amd.com // the rest of these depend on the ABI 11811886Sbrandon.potter@amd.com StackPointerReg = 30, 11911886Sbrandon.potter@amd.com GlobalPointerReg = 29, 12011886Sbrandon.potter@amd.com ProcedureValueReg = 27, 12111886Sbrandon.potter@amd.com ReturnAddressReg = 26, 1229101SBrad.Beckmann@amd.com ReturnValueReg = 0, 1232292SN/A SyscallNumReg = 0, 1242683Sktlim@umich.edu FramePointerReg = 15, 1252683Sktlim@umich.edu ArgumentReg0 = 16, 1262683Sktlim@umich.edu ArgumentReg1 = 17, 12713865Sgabeblack@google.com ArgumentReg2 = 18, 1282683Sktlim@umich.edu ArgumentReg3 = 19, 1292683Sktlim@umich.edu ArgumentReg4 = 20, 1302683Sktlim@umich.edu ArgumentReg5 = 21, 1312683Sktlim@umich.edu SyscallSuccessReg = 19, 1322683Sktlim@umich.edu // Some OS use a second register (o1) to return a second value 1332683Sktlim@umich.edu // for some syscalls 1342683Sktlim@umich.edu SyscallPseudoReturnReg = ArgumentReg4, 1352683Sktlim@umich.edu 1362683Sktlim@umich.edu LogVMPageSize = 13, // 8K bytes 1372683Sktlim@umich.edu VMPageSize = (1 << LogVMPageSize), 1382683Sktlim@umich.edu 1392683Sktlim@umich.edu BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned 1403673Srdreslin@umich.edu 1413486Sktlim@umich.edu WordBytes = 4, 1422683Sktlim@umich.edu HalfwordBytes = 2, 1432683Sktlim@umich.edu ByteBytes = 1, 1442683Sktlim@umich.edu DepNA = 0, 1455999Snate@binkert.org }; 1468834Satgutier@umich.edu 1478834Satgutier@umich.edu enum { 1488834Satgutier@umich.edu NumIntRegs = NumIntArchRegs + NumPALShadowRegs, 1498834Satgutier@umich.edu NumFloatRegs = NumFloatArchRegs, 1502683Sktlim@umich.edu NumMiscRegs = NumMiscArchRegs 1515999Snate@binkert.org }; 1522683Sktlim@umich.edu 1532683Sktlim@umich.edu // These enumerate all the registers for dependence tracking. 1542683Sktlim@umich.edu enum DependenceTags { 1552683Sktlim@umich.edu // 0..31 are the integer regs 0..31 1562683Sktlim@umich.edu // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 1572683Sktlim@umich.edu FP_Base_DepTag = 40, 1582683Sktlim@umich.edu Ctrl_Base_DepTag = 72, 1592683Sktlim@umich.edu Fpcr_DepTag = 72, // floating point control register 1602683Sktlim@umich.edu Uniq_DepTag = 73, 1612683Sktlim@umich.edu Lock_Flag_DepTag = 74, 1622683Sktlim@umich.edu Lock_Addr_DepTag = 75, 1632683Sktlim@umich.edu IPR_Base_DepTag = 76 1643402Sktlim@umich.edu }; 1653402Sktlim@umich.edu 1663402Sktlim@umich.edu typedef uint64_t IntReg; 1675714Shsul@eecs.umich.edu typedef IntReg IntRegFile[NumIntRegs]; 16811005Sandreas.sandberg@arm.com 1695714Shsul@eecs.umich.edu // floating point register file entry type 1702292SN/A typedef union { 1716221Snate@binkert.org uint64_t q; 1722292SN/A double d; 1732690Sktlim@umich.edu } FloatReg; 1742683Sktlim@umich.edu 1752683Sktlim@umich.edu typedef union { 1762292SN/A uint64_t q[NumFloatRegs]; // integer qword view 1772683Sktlim@umich.edu double d[NumFloatRegs]; // double-precision floating point view 1782683Sktlim@umich.edu } FloatRegFile; 1792292SN/A 1802683Sktlim@umich.eduextern const Addr PageShift; 1812292SN/Aextern const Addr PageBytes; 1822292SN/Aextern const Addr PageMask; 1832292SN/Aextern const Addr PageOffset; 1842292SN/A 1852292SN/A// redirected register map, really only used for the full system case. 18613905Sgabeblack@google.comextern const int reg_redir[NumIntRegs]; 1878777Sgblack@eecs.umich.edu 1882683Sktlim@umich.edu#if FULL_SYSTEM 1898229Snate@binkert.org 1908229Snate@binkert.org typedef uint64_t InternalProcReg; 1918706Sandreas.hansson@arm.com 1922683Sktlim@umich.edu#include "arch/alpha/isa_fullsys_traits.hh" 1938706Sandreas.hansson@arm.com 1942683Sktlim@umich.edu#else 1958706Sandreas.hansson@arm.com enum { 1968706Sandreas.hansson@arm.com NumInternalProcRegs = 0 1978852Sandreas.hansson@arm.com }; 1988852Sandreas.hansson@arm.com#endif 1992678Sktlim@umich.edu 2002690Sktlim@umich.edu // control register file contents 2012292SN/A typedef uint64_t MiscReg; 2022292SN/A class MiscRegFile { 2032292SN/A protected: 2042292SN/A uint64_t fpcr; // floating point condition codes 2052292SN/A uint64_t uniq; // process-unique register 2062292SN/A bool lock_flag; // lock flag for LL/SC 2072292SN/A Addr lock_addr; // lock address for LL/SC 2082292SN/A 2092292SN/A public: 2102292SN/A MiscReg readReg(int misc_reg); 2112292SN/A 2122292SN/A MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); 2132292SN/A 214 Fault setReg(int misc_reg, const MiscReg &val); 215 216 Fault setRegWithEffect(int misc_reg, const MiscReg &val, 217 ExecContext *xc); 218 219#if FULL_SYSTEM 220 void clearIprs(); 221 222 protected: 223 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 224 225 private: 226 MiscReg readIpr(int idx, Fault &fault, ExecContext *xc); 227 228 Fault setIpr(int idx, uint64_t val, ExecContext *xc); 229#endif 230 friend class RegFile; 231 }; 232 233 enum { 234 TotalNumRegs = 235 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs 236 }; 237 238 enum { 239 TotalDataRegs = NumIntRegs + NumFloatRegs 240 }; 241 242 typedef union { 243 IntReg intreg; 244 FloatReg fpreg; 245 MiscReg ctrlreg; 246 } AnyReg; 247 248 struct RegFile { 249 IntRegFile intRegFile; // (signed) integer register file 250 FloatRegFile floatRegFile; // floating point register file 251 MiscRegFile miscRegs; // control register file 252 Addr pc; // program counter 253 Addr npc; // next-cycle program counter 254#if FULL_SYSTEM 255 int intrflag; // interrupt flag 256 inline int instAsid() 257 { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); } 258 inline int dataAsid() 259 { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); } 260#endif // FULL_SYSTEM 261 262 void serialize(std::ostream &os); 263 void unserialize(Checkpoint *cp, const std::string §ion); 264 }; 265 266 static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc); 267 268 StaticInstPtr decodeInst(ExtMachInst); 269 270 // return a no-op instruction... used for instruction fetch faults 271 extern const ExtMachInst NoopMachInst; 272 273 enum annotes { 274 ANNOTE_NONE = 0, 275 // An impossible number for instruction annotations 276 ITOUCH_ANNOTE = 0xffffffff, 277 }; 278 279 static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 280 panic("register classification not implemented"); 281 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 282 } 283 284 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 285 panic("register classification not implemented"); 286 return (reg >= 9 && reg <= 15); 287 } 288 289 static inline bool isCallerSaveFloatRegister(unsigned int reg) { 290 panic("register classification not implemented"); 291 return false; 292 } 293 294 static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 295 panic("register classification not implemented"); 296 return false; 297 } 298 299 static inline Addr alignAddress(const Addr &addr, 300 unsigned int nbytes) { 301 return (addr & ~(nbytes - 1)); 302 } 303 304 // Instruction address compression hooks 305 static inline Addr realPCToFetchPC(const Addr &addr) { 306 return addr; 307 } 308 309 static inline Addr fetchPCToRealPC(const Addr &addr) { 310 return addr; 311 } 312 313 // the size of "fetched" instructions (not necessarily the size 314 // of real instructions for PISA) 315 static inline size_t fetchInstSize() { 316 return sizeof(MachInst); 317 } 318 319 static inline MachInst makeRegisterCopy(int dest, int src) { 320 panic("makeRegisterCopy not implemented"); 321 return 0; 322 } 323 324 // Machine operations 325 326 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 327 int regnum); 328 329 void restoreMachineReg(RegFile ®s, const AnyReg ®, 330 int regnum); 331 332#if 0 333 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 334 const RegFile ®s); 335 336 static void unserializeSpecialRegs(const IniFile *db, 337 const std::string &category, 338 ConfigNode *node, 339 RegFile ®s); 340#endif 341 342 /** 343 * Function to insure ISA semantics about 0 registers. 344 * @param xc The execution context. 345 */ 346 template <class XC> 347 void zeroRegisters(XC *xc); 348 349 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 350 { 351 // check for error condition. Alpha syscall convention is to 352 // indicate success/failure in reg a3 (r19) and put the 353 // return value itself in the standard return value reg (v0). 354 if (return_value.successful()) { 355 // no error 356 regs->intRegFile[SyscallSuccessReg] = 0; 357 regs->intRegFile[ReturnValueReg] = return_value.value(); 358 } else { 359 // got an error, return details 360 regs->intRegFile[SyscallSuccessReg] = (IntReg) -1; 361 regs->intRegFile[ReturnValueReg] = -return_value.value(); 362 } 363 } 364 365//typedef AlphaISA TheISA; 366 367//typedef TheISA::MachInst MachInst; 368//typedef TheISA::Addr Addr; 369//typedef TheISA::RegIndex RegIndex; 370//typedef TheISA::IntReg IntReg; 371//typedef TheISA::IntRegFile IntRegFile; 372//typedef TheISA::FloatReg FloatReg; 373//typedef TheISA::FloatRegFile FloatRegFile; 374//typedef TheISA::MiscReg MiscReg; 375//typedef TheISA::MiscRegFile MiscRegFile; 376//typedef TheISA::AnyReg AnyReg; 377//typedef TheISA::RegFile RegFile; 378 379//const int NumIntRegs = TheISA::NumIntRegs; 380//const int NumFloatRegs = TheISA::NumFloatRegs; 381//const int NumMiscRegs = TheISA::NumMiscRegs; 382//const int TotalNumRegs = TheISA::TotalNumRegs; 383//const int VMPageSize = TheISA::VMPageSize; 384//const int LogVMPageSize = TheISA::LogVMPageSize; 385//const int ZeroReg = TheISA::ZeroReg; 386//const int StackPointerReg = TheISA::StackPointerReg; 387//const int GlobalPointerReg = TheISA::GlobalPointerReg; 388//const int ReturnAddressReg = TheISA::ReturnAddressReg; 389//const int ReturnValueReg = TheISA::ReturnValueReg; 390//const int ArgumentReg0 = TheISA::ArgumentReg0; 391//const int ArgumentReg1 = TheISA::ArgumentReg1; 392//const int ArgumentReg2 = TheISA::ArgumentReg2; 393//const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; 394const Addr MaxAddr = (Addr)-1; 395}; 396 397static inline AlphaISA::ExtMachInst 398AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) { 399#if FULL_SYSTEM 400 AlphaISA::ExtMachInst ext_inst = inst; 401 if (pc && 0x1) 402 return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32); 403 else 404 return ext_inst; 405#else 406 return AlphaISA::ExtMachInst(inst); 407#endif 408} 409 410#if FULL_SYSTEM 411//typedef TheISA::InternalProcReg InternalProcReg; 412//const int NumInternalProcRegs = TheISA::NumInternalProcRegs; 413//const int NumInterruptLevels = TheISA::NumInterruptLevels; 414 415#include "arch/alpha/ev5.hh" 416#endif 417 418#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 419