isa_traits.hh revision 1458 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
30#define __ARCH_ALPHA_ISA_TRAITS_HH__
31
32#include "arch/alpha/faults.hh"
33#include "base/misc.hh"
34#include "sim/host.hh"
35
36class FastCPU;
37class FullCPU;
38class Checkpoint;
39
40#define TARGET_ALPHA
41
42template <class ISA> class StaticInst;
43template <class ISA> class StaticInstPtr;
44
45namespace EV5 {
46int DTB_ASN_ASN(uint64_t reg);
47int ITB_ASN_ASN(uint64_t reg);
48}
49
50class AlphaISA
51{
52  public:
53
54    typedef uint32_t MachInst;
55    typedef uint64_t Addr;
56    typedef uint8_t  RegIndex;
57
58    enum {
59        MemoryEnd = 0xffffffffffffffffULL,
60
61        NumIntRegs = 32,
62        NumFloatRegs = 32,
63        NumMiscRegs = 32,
64
65        MaxRegsOfAnyType = 32,
66        // Static instruction parameters
67        MaxInstSrcRegs = 3,
68        MaxInstDestRegs = 2,
69
70        // semantically meaningful register indices
71        ZeroReg = 31,	// architecturally meaningful
72        // the rest of these depend on the ABI
73        StackPointerReg = 30,
74        GlobalPointerReg = 29,
75        ReturnAddressReg = 26,
76        ReturnValueReg = 0,
77        ArgumentReg0 = 16,
78        ArgumentReg1 = 17,
79        ArgumentReg2 = 18,
80        ArgumentReg3 = 19,
81        ArgumentReg4 = 20,
82        ArgumentReg5 = 21,
83
84        LogVMPageSize = 13,	// 8K bytes
85        VMPageSize = (1 << LogVMPageSize),
86
87        BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
88
89        WordBytes = 4,
90        HalfwordBytes = 2,
91        ByteBytes = 1,
92        DepNA = 0,
93    };
94
95    // These enumerate all the registers for dependence tracking.
96    enum DependenceTags {
97        // 0..31 are the integer regs 0..31
98        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
99        FP_Base_DepTag = 32,
100        Ctrl_Base_DepTag = 64,
101        Fpcr_DepTag = 64,		// floating point control register
102        Uniq_DepTag = 65,
103        IPR_Base_DepTag = 66
104    };
105
106    typedef uint64_t IntReg;
107    typedef IntReg IntRegFile[NumIntRegs];
108
109    // floating point register file entry type
110    typedef union {
111        uint64_t q;
112        double d;
113    } FloatReg;
114
115    typedef union {
116        uint64_t q[NumFloatRegs];	// integer qword view
117        double d[NumFloatRegs];		// double-precision floating point view
118    } FloatRegFile;
119
120    // control register file contents
121    typedef uint64_t MiscReg;
122    typedef struct {
123        uint64_t	fpcr;		// floating point condition codes
124        uint64_t	uniq;		// process-unique register
125        bool		lock_flag;	// lock flag for LL/SC
126        Addr		lock_addr;	// lock address for LL/SC
127    } MiscRegFile;
128
129static const Addr PageShift = 13;
130static const Addr PageBytes = ULL(1) << PageShift;
131static const Addr PageMask = ~(PageBytes - 1);
132static const Addr PageOffset = PageBytes - 1;
133
134#ifdef FULL_SYSTEM
135
136    typedef uint64_t InternalProcReg;
137
138#include "arch/alpha/isa_fullsys_traits.hh"
139
140#else
141    enum {
142        NumInternalProcRegs = 0
143    };
144#endif
145
146    enum {
147        TotalNumRegs =
148        NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
149    };
150
151    typedef union {
152        IntReg  intreg;
153        FloatReg   fpreg;
154        MiscReg ctrlreg;
155    } AnyReg;
156
157    struct RegFile {
158        IntRegFile intRegFile;		// (signed) integer register file
159        FloatRegFile floatRegFile;	// floating point register file
160        MiscRegFile miscRegs;		// control register file
161        Addr pc;			// program counter
162        Addr npc;			// next-cycle program counter
163#ifdef FULL_SYSTEM
164        IntReg palregs[NumIntRegs];	// PAL shadow registers
165        InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
166        int intrflag;			// interrupt flag
167        bool pal_shadow;		// using pal_shadow registers
168        inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
169        inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
170#endif // FULL_SYSTEM
171
172        void serialize(std::ostream &os);
173        void unserialize(Checkpoint *cp, const std::string &section);
174    };
175
176    static StaticInstPtr<AlphaISA> decodeInst(MachInst);
177
178    // return a no-op instruction... used for instruction fetch faults
179    static const MachInst NoopMachInst;
180
181    enum annotes {
182        ANNOTE_NONE = 0,
183        // An impossible number for instruction annotations
184        ITOUCH_ANNOTE = 0xffffffff,
185    };
186
187    static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
188        panic("register classification not implemented");
189        return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
190    }
191
192    static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
193        panic("register classification not implemented");
194        return (reg >= 9 && reg <= 15);
195    }
196
197    static inline bool isCallerSaveFloatRegister(unsigned int reg) {
198        panic("register classification not implemented");
199        return false;
200    }
201
202    static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
203        panic("register classification not implemented");
204        return false;
205    }
206
207    static inline Addr alignAddress(const Addr &addr,
208                                         unsigned int nbytes) {
209        return (addr & ~(nbytes - 1));
210    }
211
212    // Instruction address compression hooks
213    static inline Addr realPCToFetchPC(const Addr &addr) {
214        return addr;
215    }
216
217    static inline Addr fetchPCToRealPC(const Addr &addr) {
218        return addr;
219    }
220
221    // the size of "fetched" instructions (not necessarily the size
222    // of real instructions for PISA)
223    static inline size_t fetchInstSize() {
224        return sizeof(MachInst);
225    }
226
227    static inline MachInst makeRegisterCopy(int dest, int src) {
228        panic("makeRegisterCopy not implemented");
229        return 0;
230    }
231
232    // Machine operations
233
234    static void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
235                               int regnum);
236
237    static void restoreMachineReg(RegFile &regs, const AnyReg &reg,
238                                  int regnum);
239
240#if 0
241    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
242                                     const RegFile &regs);
243
244    static void unserializeSpecialRegs(const IniFile *db,
245                                       const std::string &category,
246                                       ConfigNode *node,
247                                       RegFile &regs);
248#endif
249
250    /**
251     * Function to insure ISA semantics about 0 registers.
252     * @param xc The execution context.
253     */
254    template <class XC>
255    static void zeroRegisters(XC *xc);
256};
257
258
259typedef AlphaISA TheISA;
260
261typedef TheISA::MachInst MachInst;
262typedef TheISA::Addr Addr;
263typedef TheISA::RegIndex RegIndex;
264typedef TheISA::IntReg IntReg;
265typedef TheISA::IntRegFile IntRegFile;
266typedef TheISA::FloatReg FloatReg;
267typedef TheISA::FloatRegFile FloatRegFile;
268typedef TheISA::MiscReg MiscReg;
269typedef TheISA::MiscRegFile MiscRegFile;
270typedef TheISA::AnyReg AnyReg;
271typedef TheISA::RegFile RegFile;
272
273const int NumIntRegs   = TheISA::NumIntRegs;
274const int NumFloatRegs = TheISA::NumFloatRegs;
275const int NumMiscRegs  = TheISA::NumMiscRegs;
276const int TotalNumRegs = TheISA::TotalNumRegs;
277const int VMPageSize   = TheISA::VMPageSize;
278const int LogVMPageSize   = TheISA::LogVMPageSize;
279const int ZeroReg = TheISA::ZeroReg;
280const int StackPointerReg = TheISA::StackPointerReg;
281const int GlobalPointerReg = TheISA::GlobalPointerReg;
282const int ReturnAddressReg = TheISA::ReturnAddressReg;
283const int ReturnValueReg = TheISA::ReturnValueReg;
284const int ArgumentReg0 = TheISA::ArgumentReg0;
285const int ArgumentReg1 = TheISA::ArgumentReg1;
286const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
287const int MaxAddr = (Addr)-1;
288
289#ifndef FULL_SYSTEM
290class SyscallReturn {
291        public:
292           template <class T>
293           SyscallReturn(T v, bool s)
294           {
295               retval = (uint64_t)v;
296               success = s;
297           }
298
299           template <class T>
300           SyscallReturn(T v)
301           {
302               success = (v >= 0);
303               retval = (uint64_t)v;
304           }
305
306           ~SyscallReturn() {}
307
308           SyscallReturn& operator=(const SyscallReturn& s) {
309               retval = s.retval;
310               success = s.success;
311               return *this;
312           }
313
314           bool successful() { return success; }
315           uint64_t value() { return retval; }
316
317
318       private:
319           uint64_t retval;
320           bool success;
321};
322
323#endif
324
325
326#ifdef FULL_SYSTEM
327typedef TheISA::InternalProcReg InternalProcReg;
328const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
329const int NumInterruptLevels = TheISA::NumInterruptLevels;
330
331#include "arch/alpha/ev5.hh"
332#endif
333
334#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
335