isa_traits.hh revision 1147
1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 30#define __ARCH_ALPHA_ISA_TRAITS_HH__ 31 32#include "arch/alpha/faults.hh" 33#include "base/misc.hh" 34#include "sim/host.hh" 35 36class FastCPU; 37class FullCPU; 38class Checkpoint; 39 40#define TARGET_ALPHA 41 42template <class ISA> class StaticInst; 43template <class ISA> class StaticInstPtr; 44 45namespace EV5 { 46int DTB_ASN_ASN(uint64_t reg); 47int ITB_ASN_ASN(uint64_t reg); 48} 49 50class AlphaISA 51{ 52 public: 53 54 typedef uint32_t MachInst; 55 typedef uint64_t Addr; 56 typedef uint8_t RegIndex; 57 58 enum { 59 MemoryEnd = 0xffffffffffffffffULL, 60 61 NumIntRegs = 32, 62 NumFloatRegs = 32, 63 NumMiscRegs = 32, 64 65 MaxRegsOfAnyType = 32, 66 // Static instruction parameters 67 MaxInstSrcRegs = 3, 68 MaxInstDestRegs = 2, 69 70 // semantically meaningful register indices 71 ZeroReg = 31, // architecturally meaningful 72 // the rest of these depend on the ABI 73 StackPointerReg = 30, 74 GlobalPointerReg = 29, 75 ReturnAddressReg = 26, 76 ReturnValueReg = 0, 77 ArgumentReg0 = 16, 78 ArgumentReg1 = 17, 79 ArgumentReg2 = 18, 80 ArgumentReg3 = 19, 81 ArgumentReg4 = 20, 82 ArgumentReg5 = 21, 83 84 LogVMPageSize = 13, // 8K bytes 85 VMPageSize = (1 << LogVMPageSize), 86 87 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned 88 89 WordBytes = 4, 90 HalfwordBytes = 2, 91 ByteBytes = 1, 92 DepNA = 0, 93 }; 94 95 // These enumerate all the registers for dependence tracking. 96 enum DependenceTags { 97 // 0..31 are the integer regs 0..31 98 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 99 FP_Base_DepTag = 32, 100 Ctrl_Base_DepTag = 64, 101 Fpcr_DepTag = 64, // floating point control register 102 Uniq_DepTag = 65, 103 IPR_Base_DepTag = 66 104 }; 105 106 typedef uint64_t IntReg; 107 typedef IntReg IntRegFile[NumIntRegs]; 108 109 // floating point register file entry type 110 typedef union { 111 uint64_t q; 112 double d; 113 } FloatReg; 114 115 typedef union { 116 uint64_t q[NumFloatRegs]; // integer qword view 117 double d[NumFloatRegs]; // double-precision floating point view 118 } FloatRegFile; 119 120 // control register file contents 121 typedef uint64_t MiscReg; 122 typedef struct { 123 uint64_t fpcr; // floating point condition codes 124 uint64_t uniq; // process-unique register 125 bool lock_flag; // lock flag for LL/SC 126 Addr lock_addr; // lock address for LL/SC 127 } MiscRegFile; 128 129static const Addr PageShift = 13; 130static const Addr PageBytes = ULL(1) << PageShift; 131static const Addr PageMask = ~(PageBytes - 1); 132static const Addr PageOffset = PageBytes - 1; 133 134#ifdef FULL_SYSTEM 135 136 typedef uint64_t InternalProcReg; 137 138#include "arch/alpha/isa_fullsys_traits.hh" 139 140#else 141 enum { 142 NumInternalProcRegs = 0 143 }; 144#endif 145 146 enum { 147 TotalNumRegs = 148 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs 149 }; 150 151 typedef union { 152 IntReg intreg; 153 FloatReg fpreg; 154 MiscReg ctrlreg; 155 } AnyReg; 156 157 struct RegFile { 158 IntRegFile intRegFile; // (signed) integer register file 159 FloatRegFile floatRegFile; // floating point register file 160 MiscRegFile miscRegs; // control register file 161 Addr pc; // program counter 162 Addr npc; // next-cycle program counter 163#ifdef FULL_SYSTEM 164 IntReg palregs[NumIntRegs]; // PAL shadow registers 165 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 166 int intrflag; // interrupt flag 167 bool pal_shadow; // using pal_shadow registers 168 inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } 169 inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } 170#endif // FULL_SYSTEM 171 172 void serialize(std::ostream &os); 173 void unserialize(Checkpoint *cp, const std::string §ion); 174 }; 175 176 static StaticInstPtr<AlphaISA> decodeInst(MachInst); 177 178 enum annotes { 179 ANNOTE_NONE = 0, 180 // An impossible number for instruction annotations 181 ITOUCH_ANNOTE = 0xffffffff, 182 }; 183 184 static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 185 panic("register classification not implemented"); 186 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 187 } 188 189 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 190 panic("register classification not implemented"); 191 return (reg >= 9 && reg <= 15); 192 } 193 194 static inline bool isCallerSaveFloatRegister(unsigned int reg) { 195 panic("register classification not implemented"); 196 return false; 197 } 198 199 static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 200 panic("register classification not implemented"); 201 return false; 202 } 203 204 static inline Addr alignAddress(const Addr &addr, 205 unsigned int nbytes) { 206 return (addr & ~(nbytes - 1)); 207 } 208 209 // Instruction address compression hooks 210 static inline Addr realPCToFetchPC(const Addr &addr) { 211 return addr; 212 } 213 214 static inline Addr fetchPCToRealPC(const Addr &addr) { 215 return addr; 216 } 217 218 // the size of "fetched" instructions (not necessarily the size 219 // of real instructions for PISA) 220 static inline size_t fetchInstSize() { 221 return sizeof(MachInst); 222 } 223 224 static inline MachInst makeRegisterCopy(int dest, int src) { 225 panic("makeRegisterCopy not implemented"); 226 return 0; 227 } 228 229 // Machine operations 230 231 static void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 232 int regnum); 233 234 static void restoreMachineReg(RegFile ®s, const AnyReg ®, 235 int regnum); 236 237#if 0 238 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 239 const RegFile ®s); 240 241 static void unserializeSpecialRegs(const IniFile *db, 242 const std::string &category, 243 ConfigNode *node, 244 RegFile ®s); 245#endif 246 247 /** 248 * Function to insure ISA semantics about 0 registers. 249 * @param xc The execution context. 250 */ 251 template <class XC> 252 static void zeroRegisters(XC *xc); 253}; 254 255 256typedef AlphaISA TheISA; 257 258typedef TheISA::MachInst MachInst; 259typedef TheISA::Addr Addr; 260typedef TheISA::RegIndex RegIndex; 261typedef TheISA::IntReg IntReg; 262typedef TheISA::IntRegFile IntRegFile; 263typedef TheISA::FloatReg FloatReg; 264typedef TheISA::FloatRegFile FloatRegFile; 265typedef TheISA::MiscReg MiscReg; 266typedef TheISA::MiscRegFile MiscRegFile; 267typedef TheISA::AnyReg AnyReg; 268typedef TheISA::RegFile RegFile; 269 270const int NumIntRegs = TheISA::NumIntRegs; 271const int NumFloatRegs = TheISA::NumFloatRegs; 272const int NumMiscRegs = TheISA::NumMiscRegs; 273const int TotalNumRegs = TheISA::TotalNumRegs; 274const int VMPageSize = TheISA::VMPageSize; 275const int LogVMPageSize = TheISA::LogVMPageSize; 276const int ZeroReg = TheISA::ZeroReg; 277const int StackPointerReg = TheISA::StackPointerReg; 278const int GlobalPointerReg = TheISA::GlobalPointerReg; 279const int ReturnAddressReg = TheISA::ReturnAddressReg; 280const int ReturnValueReg = TheISA::ReturnValueReg; 281const int ArgumentReg0 = TheISA::ArgumentReg0; 282const int ArgumentReg1 = TheISA::ArgumentReg1; 283const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; 284const int MaxAddr = (Addr)-1; 285 286#ifdef FULL_SYSTEM 287typedef TheISA::InternalProcReg InternalProcReg; 288const int NumInternalProcRegs = TheISA::NumInternalProcRegs; 289const int NumInterruptLevels = TheISA::NumInterruptLevels; 290 291#include "arch/alpha/ev5.hh" 292#endif 293 294#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 295