decoder.isa revision 8738:66bf413b0d5b
1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OPCODE default Unknown::unknown() { 37 38 format LoadAddress { 39 0x08: lda({{ Ra = Rb + disp; }}); 40 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 41 } 42 43 format LoadOrNop { 44 0x0a: ldbu({{ Ra_uq = Mem_ub; }}); 45 0x0c: ldwu({{ Ra_uq = Mem_uw; }}); 46 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 47 0x23: ldt({{ Fa = Mem_df; }}); 48 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC); 49 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC); 50 } 51 52 format LoadOrPrefetch { 53 0x28: ldl({{ Ra_sl = Mem_sl; }}); 54 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT); 55 // IsFloating flag on lds gets the prefetch to disassemble 56 // using f31 instead of r31... funcitonally it's unnecessary 57 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }}, 58 pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 59 } 60 61 format Store { 62 0x0e: stb({{ Mem_ub = Ra<7:0>; }}); 63 0x0d: stw({{ Mem_uw = Ra<15:0>; }}); 64 0x2c: stl({{ Mem_ul = Ra<31:0>; }}); 65 0x2d: stq({{ Mem_uq = Ra_uq; }}); 66 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }}); 67 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }}); 68 0x27: stt({{ Mem_df = Fa; }}); 69 } 70 71 format StoreCond { 72 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }}, 73 {{ 74 uint64_t tmp = write_result; 75 // see stq_c 76 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 77 if (tmp == 1) { 78 xc->setStCondFailures(0); 79 } 80 }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 81 0x2f: stq_c({{ Mem_uq = Ra; }}, 82 {{ 83 uint64_t tmp = write_result; 84 // If the write operation returns 0 or 1, then 85 // this was a conventional store conditional, 86 // and the value indicates the success/failure 87 // of the operation. If another value is 88 // returned, then this was a Turbolaser 89 // mailbox access, and we don't update the 90 // result register at all. 91 Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 92 if (tmp == 1) { 93 // clear failure counter... this is 94 // non-architectural and for debugging 95 // only. 96 xc->setStCondFailures(0); 97 } 98 }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 99 } 100 101 format IntegerOperate { 102 103 0x10: decode INTFUNC { // integer arithmetic operations 104 105 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }}); 106 0x40: addlv({{ 107 int32_t tmp = Ra_sl + Rb_or_imm_sl; 108 // signed overflow occurs when operands have same sign 109 // and sign of result does not match. 110 if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>) 111 fault = new IntegerOverflowFault; 112 Rc_sl = tmp; 113 }}); 114 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }}); 115 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }}); 116 117 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 118 0x60: addqv({{ 119 uint64_t tmp = Ra + Rb_or_imm; 120 // signed overflow occurs when operands have same sign 121 // and sign of result does not match. 122 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 123 fault = new IntegerOverflowFault; 124 Rc = tmp; 125 }}); 126 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 127 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 128 129 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }}); 130 0x49: sublv({{ 131 int32_t tmp = Ra_sl - Rb_or_imm_sl; 132 // signed overflow detection is same as for add, 133 // except we need to look at the *complemented* 134 // sign bit of the subtrahend (Rb), i.e., if the initial 135 // signs are the *same* then no overflow can occur 136 if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>) 137 fault = new IntegerOverflowFault; 138 Rc_sl = tmp; 139 }}); 140 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }}); 141 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }}); 142 143 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 144 0x69: subqv({{ 145 uint64_t tmp = Ra - Rb_or_imm; 146 // signed overflow detection is same as for add, 147 // except we need to look at the *complemented* 148 // sign bit of the subtrahend (Rb), i.e., if the initial 149 // signs are the *same* then no overflow can occur 150 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 151 fault = new IntegerOverflowFault; 152 Rc = tmp; 153 }}); 154 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 155 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 156 157 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 158 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }}); 159 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }}); 160 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }}); 161 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }}); 162 163 0x0f: cmpbge({{ 164 int hi = 7; 165 int lo = 0; 166 uint64_t tmp = 0; 167 for (int i = 0; i < 8; ++i) { 168 tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i; 169 hi += 8; 170 lo += 8; 171 } 172 Rc = tmp; 173 }}); 174 } 175 176 0x11: decode INTFUNC { // integer logical operations 177 178 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 179 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 180 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 181 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 182 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 183 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 184 185 // conditional moves 186 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 187 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 188 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 189 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 190 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }}); 191 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }}); 192 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }}); 193 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }}); 194 195 // For AMASK, RA must be R31. 196 0x61: decode RA { 197 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 198 } 199 200 // For IMPLVER, RA must be R31 and the B operand 201 // must be the immediate value 1. 202 0x6c: decode RA { 203 31: decode IMM { 204 1: decode INTIMM { 205 // return EV5 for FullSystem and EV6 otherwise 206 1: implver({{ Rc = FullSystem ? 1 : 2 }}); 207 } 208 } 209 } 210 211 // The mysterious 11.25... 212 0x25: WarnUnimpl::eleven25(); 213 } 214 215 0x12: decode INTFUNC { 216 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 217 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }}); 218 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }}); 219 220 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 221 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 222 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 223 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 224 225 0x52: mskwh({{ 226 int bv = Rb_or_imm<2:0>; 227 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 228 }}); 229 0x62: msklh({{ 230 int bv = Rb_or_imm<2:0>; 231 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 232 }}); 233 0x72: mskqh({{ 234 int bv = Rb_or_imm<2:0>; 235 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 236 }}); 237 238 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 239 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 240 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 241 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }}); 242 243 0x5a: extwh({{ 244 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 245 0x6a: extlh({{ 246 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 247 0x7a: extqh({{ 248 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 249 250 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 251 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 252 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 253 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 254 255 0x57: inswh({{ 256 int bv = Rb_or_imm<2:0>; 257 Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0; 258 }}); 259 0x67: inslh({{ 260 int bv = Rb_or_imm<2:0>; 261 Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0; 262 }}); 263 0x77: insqh({{ 264 int bv = Rb_or_imm<2:0>; 265 Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0; 266 }}); 267 268 0x30: zap({{ 269 uint64_t zapmask = 0; 270 for (int i = 0; i < 8; ++i) { 271 if (Rb_or_imm<i:>) 272 zapmask |= (mask(8) << (i * 8)); 273 } 274 Rc = Ra & ~zapmask; 275 }}); 276 0x31: zapnot({{ 277 uint64_t zapmask = 0; 278 for (int i = 0; i < 8; ++i) { 279 if (!Rb_or_imm<i:>) 280 zapmask |= (mask(8) << (i * 8)); 281 } 282 Rc = Ra & ~zapmask; 283 }}); 284 } 285 286 0x13: decode INTFUNC { // integer multiplies 287 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp); 288 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 289 0x30: umulh({{ 290 uint64_t hi, lo; 291 mul128(Ra, Rb_or_imm, hi, lo); 292 Rc = hi; 293 }}, IntMultOp); 294 0x40: mullv({{ 295 // 32-bit multiply with trap on overflow 296 int64_t Rax = Ra_sl; // sign extended version of Ra_sl 297 int64_t Rbx = Rb_or_imm_sl; 298 int64_t tmp = Rax * Rbx; 299 // To avoid overflow, all the upper 32 bits must match 300 // the sign bit of the lower 32. We code this as 301 // checking the upper 33 bits for all 0s or all 1s. 302 uint64_t sign_bits = tmp<63:31>; 303 if (sign_bits != 0 && sign_bits != mask(33)) 304 fault = new IntegerOverflowFault; 305 Rc_sl = tmp<31:0>; 306 }}, IntMultOp); 307 0x60: mulqv({{ 308 // 64-bit multiply with trap on overflow 309 uint64_t hi, lo; 310 mul128(Ra, Rb_or_imm, hi, lo); 311 // all the upper 64 bits must match the sign bit of 312 // the lower 64 313 if (!((hi == 0 && lo<63:> == 0) || 314 (hi == mask(64) && lo<63:> == 1))) 315 fault = new IntegerOverflowFault; 316 Rc = lo; 317 }}, IntMultOp); 318 } 319 320 0x1c: decode INTFUNC { 321 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); } 322 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); } 323 324 0x30: ctpop({{ 325 uint64_t count = 0; 326 for (int i = 0; Rb<63:i>; ++i) { 327 if (Rb<i:i> == 0x1) 328 ++count; 329 } 330 Rc = count; 331 }}, IntAluOp); 332 333 0x31: perr({{ 334 uint64_t temp = 0; 335 int hi = 7; 336 int lo = 0; 337 for (int i = 0; i < 8; ++i) { 338 uint8_t ra_ub = Ra_uq<hi:lo>; 339 uint8_t rb_ub = Rb_uq<hi:lo>; 340 temp += (ra_ub >= rb_ub) ? 341 (ra_ub - rb_ub) : (rb_ub - ra_ub); 342 hi += 8; 343 lo += 8; 344 } 345 Rc = temp; 346 }}); 347 348 0x32: ctlz({{ 349 uint64_t count = 0; 350 uint64_t temp = Rb; 351 if (temp<63:32>) temp >>= 32; else count += 32; 352 if (temp<31:16>) temp >>= 16; else count += 16; 353 if (temp<15:8>) temp >>= 8; else count += 8; 354 if (temp<7:4>) temp >>= 4; else count += 4; 355 if (temp<3:2>) temp >>= 2; else count += 2; 356 if (temp<1:1>) temp >>= 1; else count += 1; 357 if ((temp<0:0>) != 0x1) count += 1; 358 Rc = count; 359 }}, IntAluOp); 360 361 0x33: cttz({{ 362 uint64_t count = 0; 363 uint64_t temp = Rb; 364 if (!(temp<31:0>)) { temp >>= 32; count += 32; } 365 if (!(temp<15:0>)) { temp >>= 16; count += 16; } 366 if (!(temp<7:0>)) { temp >>= 8; count += 8; } 367 if (!(temp<3:0>)) { temp >>= 4; count += 4; } 368 if (!(temp<1:0>)) { temp >>= 2; count += 2; } 369 if (!(temp<0:0> & ULL(0x1))) { 370 temp >>= 1; count += 1; 371 } 372 if (!(temp<0:0> & ULL(0x1))) count += 1; 373 Rc = count; 374 }}, IntAluOp); 375 376 377 0x34: unpkbw({{ 378 Rc = (Rb_uq<7:0> 379 | (Rb_uq<15:8> << 16) 380 | (Rb_uq<23:16> << 32) 381 | (Rb_uq<31:24> << 48)); 382 }}, IntAluOp); 383 384 0x35: unpkbl({{ 385 Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32)); 386 }}, IntAluOp); 387 388 0x36: pkwb({{ 389 Rc = (Rb_uq<7:0> 390 | (Rb_uq<23:16> << 8) 391 | (Rb_uq<39:32> << 16) 392 | (Rb_uq<55:48> << 24)); 393 }}, IntAluOp); 394 395 0x37: pklb({{ 396 Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8)); 397 }}, IntAluOp); 398 399 0x38: minsb8({{ 400 uint64_t temp = 0; 401 int hi = 63; 402 int lo = 56; 403 for (int i = 7; i >= 0; --i) { 404 int8_t ra_sb = Ra_uq<hi:lo>; 405 int8_t rb_sb = Rb_uq<hi:lo>; 406 temp = ((temp << 8) 407 | ((ra_sb < rb_sb) ? Ra_uq<hi:lo> 408 : Rb_uq<hi:lo>)); 409 hi -= 8; 410 lo -= 8; 411 } 412 Rc = temp; 413 }}); 414 415 0x39: minsw4({{ 416 uint64_t temp = 0; 417 int hi = 63; 418 int lo = 48; 419 for (int i = 3; i >= 0; --i) { 420 int16_t ra_sw = Ra_uq<hi:lo>; 421 int16_t rb_sw = Rb_uq<hi:lo>; 422 temp = ((temp << 16) 423 | ((ra_sw < rb_sw) ? Ra_uq<hi:lo> 424 : Rb_uq<hi:lo>)); 425 hi -= 16; 426 lo -= 16; 427 } 428 Rc = temp; 429 }}); 430 431 0x3a: minub8({{ 432 uint64_t temp = 0; 433 int hi = 63; 434 int lo = 56; 435 for (int i = 7; i >= 0; --i) { 436 uint8_t ra_ub = Ra_uq<hi:lo>; 437 uint8_t rb_ub = Rb_uq<hi:lo>; 438 temp = ((temp << 8) 439 | ((ra_ub < rb_ub) ? Ra_uq<hi:lo> 440 : Rb_uq<hi:lo>)); 441 hi -= 8; 442 lo -= 8; 443 } 444 Rc = temp; 445 }}); 446 447 0x3b: minuw4({{ 448 uint64_t temp = 0; 449 int hi = 63; 450 int lo = 48; 451 for (int i = 3; i >= 0; --i) { 452 uint16_t ra_sw = Ra_uq<hi:lo>; 453 uint16_t rb_sw = Rb_uq<hi:lo>; 454 temp = ((temp << 16) 455 | ((ra_sw < rb_sw) ? Ra_uq<hi:lo> 456 : Rb_uq<hi:lo>)); 457 hi -= 16; 458 lo -= 16; 459 } 460 Rc = temp; 461 }}); 462 463 0x3c: maxub8({{ 464 uint64_t temp = 0; 465 int hi = 63; 466 int lo = 56; 467 for (int i = 7; i >= 0; --i) { 468 uint8_t ra_ub = Ra_uq<hi:lo>; 469 uint8_t rb_ub = Rb_uq<hi:lo>; 470 temp = ((temp << 8) 471 | ((ra_ub > rb_ub) ? Ra_uq<hi:lo> 472 : Rb_uq<hi:lo>)); 473 hi -= 8; 474 lo -= 8; 475 } 476 Rc = temp; 477 }}); 478 479 0x3d: maxuw4({{ 480 uint64_t temp = 0; 481 int hi = 63; 482 int lo = 48; 483 for (int i = 3; i >= 0; --i) { 484 uint16_t ra_uw = Ra_uq<hi:lo>; 485 uint16_t rb_uw = Rb_uq<hi:lo>; 486 temp = ((temp << 16) 487 | ((ra_uw > rb_uw) ? Ra_uq<hi:lo> 488 : Rb_uq<hi:lo>)); 489 hi -= 16; 490 lo -= 16; 491 } 492 Rc = temp; 493 }}); 494 495 0x3e: maxsb8({{ 496 uint64_t temp = 0; 497 int hi = 63; 498 int lo = 56; 499 for (int i = 7; i >= 0; --i) { 500 int8_t ra_sb = Ra_uq<hi:lo>; 501 int8_t rb_sb = Rb_uq<hi:lo>; 502 temp = ((temp << 8) 503 | ((ra_sb > rb_sb) ? Ra_uq<hi:lo> 504 : Rb_uq<hi:lo>)); 505 hi -= 8; 506 lo -= 8; 507 } 508 Rc = temp; 509 }}); 510 511 0x3f: maxsw4({{ 512 uint64_t temp = 0; 513 int hi = 63; 514 int lo = 48; 515 for (int i = 3; i >= 0; --i) { 516 int16_t ra_sw = Ra_uq<hi:lo>; 517 int16_t rb_sw = Rb_uq<hi:lo>; 518 temp = ((temp << 16) 519 | ((ra_sw > rb_sw) ? Ra_uq<hi:lo> 520 : Rb_uq<hi:lo>)); 521 hi -= 16; 522 lo -= 16; 523 } 524 Rc = temp; 525 }}); 526 527 format BasicOperateWithNopCheck { 528 0x70: decode RB { 529 31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp); 530 } 531 0x78: decode RB { 532 31: ftois({{ Rc_sl = t_to_s(Fa_uq); }}, 533 FloatCvtOp); 534 } 535 } 536 } 537 } 538 539 // Conditional branches. 540 format CondBranch { 541 0x39: beq({{ cond = (Ra == 0); }}); 542 0x3d: bne({{ cond = (Ra != 0); }}); 543 0x3e: bge({{ cond = (Ra_sq >= 0); }}); 544 0x3f: bgt({{ cond = (Ra_sq > 0); }}); 545 0x3b: ble({{ cond = (Ra_sq <= 0); }}); 546 0x3a: blt({{ cond = (Ra_sq < 0); }}); 547 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 548 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 549 550 0x31: fbeq({{ cond = (Fa == 0); }}); 551 0x35: fbne({{ cond = (Fa != 0); }}); 552 0x36: fbge({{ cond = (Fa >= 0); }}); 553 0x37: fbgt({{ cond = (Fa > 0); }}); 554 0x33: fble({{ cond = (Fa <= 0); }}); 555 0x32: fblt({{ cond = (Fa < 0); }}); 556 } 557 558 // unconditional branches 559 format UncondBranch { 560 0x30: br(); 561 0x34: bsr(IsCall); 562 } 563 564 // indirect branches 565 0x1a: decode JMPFUNC { 566 format Jump { 567 0: jmp(); 568 1: jsr(IsCall); 569 2: ret(IsReturn); 570 3: jsr_coroutine(IsCall, IsReturn); 571 } 572 } 573 574 // Square root and integer-to-FP moves 575 0x14: decode FP_SHORTFUNC { 576 // Integer to FP register moves must have RB == 31 577 0x4: decode RB { 578 31: decode FP_FULLFUNC { 579 format BasicOperateWithNopCheck { 580 0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp); 581 0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp); 582 0x014: FailUnimpl::itoff(); // VAX-format conversion 583 } 584 } 585 } 586 587 // Square root instructions must have FA == 31 588 0xb: decode FA { 589 31: decode FP_TYPEFUNC { 590 format FloatingPointOperate { 591#if SS_COMPATIBLE_FP 592 0x0b: sqrts({{ 593 if (Fb < 0.0) 594 fault = new ArithmeticFault; 595 Fc = sqrt(Fb); 596 }}, FloatSqrtOp); 597#else 598 0x0b: sqrts({{ 599 if (Fb_sf < 0.0) 600 fault = new ArithmeticFault; 601 Fc_sf = sqrt(Fb_sf); 602 }}, FloatSqrtOp); 603#endif 604 0x2b: sqrtt({{ 605 if (Fb < 0.0) 606 fault = new ArithmeticFault; 607 Fc = sqrt(Fb); 608 }}, FloatSqrtOp); 609 } 610 } 611 } 612 613 // VAX-format sqrtf and sqrtg are not implemented 614 0xa: FailUnimpl::sqrtfg(); 615 } 616 617 // IEEE floating point 618 0x16: decode FP_SHORTFUNC_TOP2 { 619 // The top two bits of the short function code break this 620 // space into four groups: binary ops, compares, reserved, and 621 // conversions. See Table 4-12 of AHB. There are different 622 // special cases in these different groups, so we decode on 623 // these top two bits first just to select a decode strategy. 624 // Most of these instructions may have various trapping and 625 // rounding mode flags set; these are decoded in the 626 // FloatingPointDecode template used by the 627 // FloatingPointOperate format. 628 629 // add/sub/mul/div: just decode on the short function code 630 // and source type. All valid trapping and rounding modes apply. 631 0: decode FP_TRAPMODE { 632 // check for valid trapping modes here 633 0,1,5,7: decode FP_TYPEFUNC { 634 format FloatingPointOperate { 635#if SS_COMPATIBLE_FP 636 0x00: adds({{ Fc = Fa + Fb; }}); 637 0x01: subs({{ Fc = Fa - Fb; }}); 638 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 639 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 640#else 641 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }}); 642 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }}); 643 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp); 644 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp); 645#endif 646 647 0x20: addt({{ Fc = Fa + Fb; }}); 648 0x21: subt({{ Fc = Fa - Fb; }}); 649 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 650 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 651 } 652 } 653 } 654 655 // Floating-point compare instructions must have the default 656 // rounding mode, and may use the default trapping mode or 657 // /SU. Both trapping modes are treated the same by M5; the 658 // only difference on the real hardware (as far a I can tell) 659 // is that without /SU you'd get an imprecise trap if you 660 // tried to compare a NaN with something else (instead of an 661 // "unordered" result). 662 1: decode FP_FULLFUNC { 663 format BasicOperateWithNopCheck { 664 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 665 FloatCmpOp); 666 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 667 FloatCmpOp); 668 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 669 FloatCmpOp); 670 0x0a4, 0x5a4: cmptun({{ // unordered 671 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 672 }}, FloatCmpOp); 673 } 674 } 675 676 // The FP-to-integer and integer-to-FP conversion insts 677 // require that FA be 31. 678 3: decode FA { 679 31: decode FP_TYPEFUNC { 680 format FloatingPointOperate { 681 0x2f: decode FP_ROUNDMODE { 682 format FPFixedRounding { 683 // "chopped" i.e. round toward zero 684 0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }}, 685 Chopped); 686 // round to minus infinity 687 1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }}, 688 MinusInfinity); 689 } 690 default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }}); 691 } 692 693 // The cvtts opcode is overloaded to be cvtst if the trap 694 // mode is 2 or 6 (which are not valid otherwise) 695 0x2c: decode FP_FULLFUNC { 696 format BasicOperateWithNopCheck { 697 // trap on denorm version "cvtst/s" is 698 // simulated same as cvtst 699 0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }}); 700 } 701 default: cvtts({{ Fc_sf = Fb; }}); 702 } 703 704 // The trapping mode for integer-to-FP conversions 705 // must be /SUI or nothing; /U and /SU are not 706 // allowed. The full set of rounding modes are 707 // supported though. 708 0x3c: decode FP_TRAPMODE { 709 0,7: cvtqs({{ Fc_sf = Fb_sq; }}); 710 } 711 0x3e: decode FP_TRAPMODE { 712 0,7: cvtqt({{ Fc = Fb_sq; }}); 713 } 714 } 715 } 716 } 717 } 718 719 // misc FP operate 720 0x17: decode FP_FULLFUNC { 721 format BasicOperateWithNopCheck { 722 0x010: cvtlq({{ 723 Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>; 724 }}); 725 0x030: cvtql({{ 726 Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29); 727 }}); 728 729 // We treat the precise & imprecise trapping versions of 730 // cvtql identically. 731 0x130, 0x530: cvtqlv({{ 732 // To avoid overflow, all the upper 32 bits must match 733 // the sign bit of the lower 32. We code this as 734 // checking the upper 33 bits for all 0s or all 1s. 735 uint64_t sign_bits = Fb_uq<63:31>; 736 if (sign_bits != 0 && sign_bits != mask(33)) 737 fault = new IntegerOverflowFault; 738 Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29); 739 }}); 740 741 0x020: cpys({{ // copy sign 742 Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>; 743 }}); 744 0x021: cpysn({{ // copy sign negated 745 Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>; 746 }}); 747 0x022: cpyse({{ // copy sign and exponent 748 Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>; 749 }}); 750 751 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 752 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 753 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 754 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 755 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 756 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 757 758 0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess); 759 0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess); 760 } 761 } 762 763 // miscellaneous mem-format ops 764 0x18: decode MEMFUNC { 765 format WarnUnimpl { 766 0x8000: fetch(); 767 0xa000: fetch_m(); 768 0xe800: ecb(); 769 } 770 771 format MiscPrefetch { 772 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 773 {{ ; }}, 774 mem_flags = PREFETCH); 775 } 776 777 format BasicOperate { 778 0xc000: rpcc({{ 779 /* Rb is a fake dependency so here is a fun way to get 780 * the parser to understand that. 781 */ 782 uint64_t unused_var M5_VAR_USED = Rb; 783 Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick(); 784 }}, IsUnverifiable); 785 786 // All of the barrier instructions below do nothing in 787 // their execute() methods (hence the empty code blocks). 788 // All of their functionality is hard-coded in the 789 // pipeline based on the flags IsSerializing, 790 // IsMemBarrier, and IsWriteBarrier. In the current 791 // detailed CPU model, the execute() function only gets 792 // called at fetch, so there's no way to generate pipeline 793 // behavior at any other stage. Once we go to an 794 // exec-in-exec CPU model we should be able to get rid of 795 // these flags and implement this behavior via the 796 // execute() methods. 797 798 // trapb is just a barrier on integer traps, where excb is 799 // a barrier on integer and FP traps. "EXCB is thus a 800 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 801 // them the same though. 802 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 803 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 804 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 805 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 806 } 807 808 0xe000: decode FullSystem { 809 0: FailUnimpl::rc_se(); 810 default: BasicOperate::rc({{ 811 Ra = IntrFlag; 812 IntrFlag = 0; 813 }}, IsNonSpeculative, IsUnverifiable); 814 } 815 0xf000: decode FullSystem { 816 0: FailUnimpl::rs_se(); 817 default: BasicOperate::rs({{ 818 Ra = IntrFlag; 819 IntrFlag = 1; 820 }}, IsNonSpeculative, IsUnverifiable); 821 } 822 } 823 824#if FULL_SYSTEM 825 0x00: CallPal::call_pal({{ 826 if (!palValid || 827 (palPriv 828 && xc->readMiscReg(IPR_ICM) != mode_kernel)) { 829 // invalid pal function code, or attempt to do privileged 830 // PAL call in non-kernel mode 831 fault = new UnimplementedOpcodeFault; 832 } else { 833 // check to see if simulator wants to do something special 834 // on this PAL call (including maybe suppress it) 835 bool dopal = xc->simPalCheck(palFunc); 836 837 if (dopal) { 838 xc->setMiscReg(IPR_EXC_ADDR, NPC); 839 NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset; 840 } 841 } 842 }}, IsNonSpeculative); 843#else 844 0x00: decode PALFUNC { 845 format EmulatedCallPal { 846 0x00: halt ({{ 847 exitSimLoop("halt instruction encountered"); 848 }}, IsNonSpeculative); 849 0x83: callsys({{ 850 xc->syscall(R0); 851 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 852 // Read uniq reg into ABI return value register (r0) 853 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); 854 // Write uniq reg with value from ABI arg register (r16) 855 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess); 856 } 857 } 858#endif 859 860#if FULL_SYSTEM 861 0x1b: decode PALMODE { 862 0: OpcdecFault::hw_st_quad(); 863 1: decode HW_LDST_QUAD { 864 format HwLoad { 865 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }}, 866 L, IsSerializing, IsSerializeBefore); 867 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }}, 868 Q, IsSerializing, IsSerializeBefore); 869 } 870 } 871 } 872 873 0x1f: decode PALMODE { 874 0: OpcdecFault::hw_st_cond(); 875 format HwStore { 876 1: decode HW_LDST_COND { 877 0: decode HW_LDST_QUAD { 878 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 879 {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore); 880 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 881 {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore); 882 } 883 884 1: FailUnimpl::hw_st_cond(); 885 } 886 } 887 } 888 889 0x19: decode PALMODE { 890 0: OpcdecFault::hw_mfpr(); 891 format HwMoveIPR { 892 1: hw_mfpr({{ 893 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 894 IprToMiscRegIndex[ipr_index] : -1; 895 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || 896 miscRegIndex >= NumInternalProcRegs) 897 fault = new UnimplementedOpcodeFault; 898 else 899 Ra = xc->readMiscReg(miscRegIndex); 900 }}, IsIprAccess); 901 } 902 } 903 904 0x1d: decode PALMODE { 905 0: OpcdecFault::hw_mtpr(); 906 format HwMoveIPR { 907 1: hw_mtpr({{ 908 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 909 IprToMiscRegIndex[ipr_index] : -1; 910 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) || 911 miscRegIndex >= NumInternalProcRegs) 912 fault = new UnimplementedOpcodeFault; 913 else 914 xc->setMiscReg(miscRegIndex, Ra); 915 if (traceData) { traceData->setData(Ra); } 916 }}, IsIprAccess); 917 } 918 } 919 920 0x1e: decode PALMODE { 921 0: OpcdecFault::hw_rei(); 922 format BasicOperate { 923 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); 924 } 925 } 926 927#endif 928 929 format BasicOperate { 930 // M5 special opcodes use the reserved 0x01 opcode space 931 0x01: decode M5FUNC { 932 0x00: arm({{ 933 PseudoInst::arm(xc->tcBase()); 934 }}, IsNonSpeculative); 935 0x01: quiesce({{ 936 PseudoInst::quiesce(xc->tcBase()); 937 }}, IsNonSpeculative, IsQuiesce); 938 0x02: quiesceNs({{ 939 PseudoInst::quiesceNs(xc->tcBase(), R16); 940 }}, IsNonSpeculative, IsQuiesce); 941 0x03: quiesceCycles({{ 942 PseudoInst::quiesceCycles(xc->tcBase(), R16); 943 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 944 0x04: quiesceTime({{ 945 R0 = PseudoInst::quiesceTime(xc->tcBase()); 946 }}, IsNonSpeculative, IsUnverifiable); 947 0x07: rpns({{ 948 R0 = PseudoInst::rpns(xc->tcBase()); 949 }}, IsNonSpeculative, IsUnverifiable); 950 0x09: wakeCPU({{ 951 PseudoInst::wakeCPU(xc->tcBase(), R16); 952 }}, IsNonSpeculative, IsUnverifiable); 953 0x10: deprecated_ivlb({{ 954 warn_once("Obsolete M5 ivlb instruction encountered.\n"); 955 }}); 956 0x11: deprecated_ivle({{ 957 warn_once("Obsolete M5 ivlb instruction encountered.\n"); 958 }}); 959 0x20: deprecated_exit ({{ 960 warn_once("deprecated M5 exit instruction encountered.\n"); 961 PseudoInst::m5exit(xc->tcBase(), 0); 962 }}, No_OpClass, IsNonSpeculative); 963 0x21: m5exit({{ 964 PseudoInst::m5exit(xc->tcBase(), R16); 965 }}, No_OpClass, IsNonSpeculative); 966 0x31: loadsymbol({{ 967 PseudoInst::loadsymbol(xc->tcBase()); 968 }}, No_OpClass, IsNonSpeculative); 969 0x30: initparam({{ 970 Ra = PseudoInst::initParam(xc->tcBase()); 971 }}); 972 0x40: resetstats({{ 973 PseudoInst::resetstats(xc->tcBase(), R16, R17); 974 }}, IsNonSpeculative); 975 0x41: dumpstats({{ 976 PseudoInst::dumpstats(xc->tcBase(), R16, R17); 977 }}, IsNonSpeculative); 978 0x42: dumpresetstats({{ 979 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17); 980 }}, IsNonSpeculative); 981 0x43: m5checkpoint({{ 982 PseudoInst::m5checkpoint(xc->tcBase(), R16, R17); 983 }}, IsNonSpeculative); 984 0x50: m5readfile({{ 985 R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18); 986 }}, IsNonSpeculative); 987 0x51: m5break({{ 988 PseudoInst::debugbreak(xc->tcBase()); 989 }}, IsNonSpeculative); 990 0x52: m5switchcpu({{ 991 PseudoInst::switchcpu(xc->tcBase()); 992 }}, IsNonSpeculative); 993 0x53: m5addsymbol({{ 994 PseudoInst::addsymbol(xc->tcBase(), R16, R17); 995 }}, IsNonSpeculative); 996 0x54: m5panic({{ 997 panic("M5 panic instruction called at pc = %#x.", PC); 998 }}, IsNonSpeculative); 999#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase()) 1000 0x55: decode RA { 1001 0x00: m5a_old({{ 1002 panic("Deprecated M5 annotate instruction executed " 1003 "at pc = %#x\n", PC); 1004 }}, IsNonSpeculative); 1005 0x01: m5a_bsm({{ 1006 CPANN(swSmBegin); 1007 }}, IsNonSpeculative); 1008 0x02: m5a_esm({{ 1009 CPANN(swSmEnd); 1010 }}, IsNonSpeculative); 1011 0x03: m5a_begin({{ 1012 CPANN(swExplictBegin); 1013 }}, IsNonSpeculative); 1014 0x04: m5a_end({{ 1015 CPANN(swEnd); 1016 }}, IsNonSpeculative); 1017 0x06: m5a_q({{ 1018 CPANN(swQ); 1019 }}, IsNonSpeculative); 1020 0x07: m5a_dq({{ 1021 CPANN(swDq); 1022 }}, IsNonSpeculative); 1023 0x08: m5a_wf({{ 1024 CPANN(swWf); 1025 }}, IsNonSpeculative); 1026 0x09: m5a_we({{ 1027 CPANN(swWe); 1028 }}, IsNonSpeculative); 1029 0x0C: m5a_sq({{ 1030 CPANN(swSq); 1031 }}, IsNonSpeculative); 1032 0x0D: m5a_aq({{ 1033 CPANN(swAq); 1034 }}, IsNonSpeculative); 1035 0x0E: m5a_pq({{ 1036 CPANN(swPq); 1037 }}, IsNonSpeculative); 1038 0x0F: m5a_l({{ 1039 CPANN(swLink); 1040 }}, IsNonSpeculative); 1041 0x10: m5a_identify({{ 1042 CPANN(swIdentify); 1043 }}, IsNonSpeculative); 1044 0x11: m5a_getid({{ 1045 R0 = CPANN(swGetId); 1046 }}, IsNonSpeculative); 1047 0x13: m5a_scl({{ 1048 CPANN(swSyscallLink); 1049 }}, IsNonSpeculative); 1050 0x14: m5a_rq({{ 1051 CPANN(swRq); 1052 }}, IsNonSpeculative); 1053 } // M5 Annotate Operations 1054#undef CPANN 1055 0x56: m5reserved2({{ 1056 warn("M5 reserved opcode ignored"); 1057 }}, IsNonSpeculative); 1058 0x57: m5reserved3({{ 1059 warn("M5 reserved opcode ignored"); 1060 }}, IsNonSpeculative); 1061 0x58: m5reserved4({{ 1062 warn("M5 reserved opcode ignored"); 1063 }}, IsNonSpeculative); 1064 0x59: m5reserved5({{ 1065 warn("M5 reserved opcode ignored"); 1066 }}, IsNonSpeculative); 1067 } 1068 } 1069} 1070