decoder.isa revision 7720
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OPCODE default Unknown::unknown() {
37
38    format LoadAddress {
39        0x08: lda({{ Ra = Rb + disp; }});
40        0x09: ldah({{ Ra = Rb + (disp << 16); }});
41    }
42
43    format LoadOrNop {
44        0x0a: ldbu({{ Ra.uq = Mem.ub; }});
45        0x0c: ldwu({{ Ra.uq = Mem.uw; }});
46        0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
47        0x23: ldt({{ Fa = Mem.df; }});
48        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
49        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
50#ifdef USE_COPY
51        0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
52                                      {{ fault = xc->copySrcTranslate(EA); }},
53                                      inst_flags = [IsMemRef, IsLoad, IsCopy]);
54#endif
55    }
56
57    format LoadOrPrefetch {
58        0x28: ldl({{ Ra.sl = Mem.sl; }});
59        0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
60        // IsFloating flag on lds gets the prefetch to disassemble
61        // using f31 instead of r31... funcitonally it's unnecessary
62        0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
63                  pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
64    }
65
66    format Store {
67        0x0e: stb({{ Mem.ub = Ra<7:0>; }});
68        0x0d: stw({{ Mem.uw = Ra<15:0>; }});
69        0x2c: stl({{ Mem.ul = Ra<31:0>; }});
70        0x2d: stq({{ Mem.uq = Ra.uq; }});
71        0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
72        0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
73        0x27: stt({{ Mem.df = Fa; }});
74#ifdef USE_COPY
75        0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
76                                       {{ fault = xc->copy(EA); }},
77                                       inst_flags = [IsMemRef, IsStore, IsCopy]);
78#endif
79    }
80
81    format StoreCond {
82        0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
83                    {{
84                        uint64_t tmp = write_result;
85                        // see stq_c
86                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
87                        if (tmp == 1) {
88                            xc->setStCondFailures(0);
89                        }
90                    }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
91        0x2f: stq_c({{ Mem.uq = Ra; }},
92                    {{
93                        uint64_t tmp = write_result;
94                        // If the write operation returns 0 or 1, then
95                        // this was a conventional store conditional,
96                        // and the value indicates the success/failure
97                        // of the operation.  If another value is
98                        // returned, then this was a Turbolaser
99                        // mailbox access, and we don't update the
100                        // result register at all.
101                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
102                        if (tmp == 1) {
103                            // clear failure counter... this is
104                            // non-architectural and for debugging
105                            // only.
106                            xc->setStCondFailures(0);
107                        }
108                    }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
109    }
110
111    format IntegerOperate {
112
113        0x10: decode INTFUNC {	// integer arithmetic operations
114
115            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
116            0x40: addlv({{
117                int32_t tmp  = Ra.sl + Rb_or_imm.sl;
118                // signed overflow occurs when operands have same sign
119                // and sign of result does not match.
120                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
121                    fault = new IntegerOverflowFault;
122                Rc.sl = tmp;
123            }});
124            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
125            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
126
127            0x20: addq({{ Rc = Ra + Rb_or_imm; }});
128            0x60: addqv({{
129                uint64_t tmp = Ra + Rb_or_imm;
130                // signed overflow occurs when operands have same sign
131                // and sign of result does not match.
132                if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
133                    fault = new IntegerOverflowFault;
134                Rc = tmp;
135            }});
136            0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
137            0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
138
139            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
140            0x49: sublv({{
141                int32_t tmp  = Ra.sl - Rb_or_imm.sl;
142                // signed overflow detection is same as for add,
143                // except we need to look at the *complemented*
144                // sign bit of the subtrahend (Rb), i.e., if the initial
145                // signs are the *same* then no overflow can occur
146                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
147                    fault = new IntegerOverflowFault;
148                Rc.sl = tmp;
149            }});
150            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
151            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
152
153            0x29: subq({{ Rc = Ra - Rb_or_imm; }});
154            0x69: subqv({{
155                uint64_t tmp  = Ra - Rb_or_imm;
156                // signed overflow detection is same as for add,
157                // except we need to look at the *complemented*
158                // sign bit of the subtrahend (Rb), i.e., if the initial
159                // signs are the *same* then no overflow can occur
160                if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
161                    fault = new IntegerOverflowFault;
162                Rc = tmp;
163            }});
164            0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
165            0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
166
167            0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
168            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
169            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
170            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
171            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
172
173            0x0f: cmpbge({{
174                int hi = 7;
175                int lo = 0;
176                uint64_t tmp = 0;
177                for (int i = 0; i < 8; ++i) {
178                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
179                    hi += 8;
180                    lo += 8;
181                }
182                Rc = tmp;
183            }});
184        }
185
186        0x11: decode INTFUNC {	// integer logical operations
187
188            0x00: and({{ Rc = Ra & Rb_or_imm; }});
189            0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
190            0x20: bis({{ Rc = Ra | Rb_or_imm; }});
191            0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
192            0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
193            0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
194
195            // conditional moves
196            0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
197            0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
198            0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
199            0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
200            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
201            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
202            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
203            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
204
205            // For AMASK, RA must be R31.
206            0x61: decode RA {
207                31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
208            }
209
210            // For IMPLVER, RA must be R31 and the B operand
211            // must be the immediate value 1.
212            0x6c: decode RA {
213                31: decode IMM {
214                    1: decode INTIMM {
215                        // return EV5 for FULL_SYSTEM and EV6 otherwise
216                        1: implver({{
217#if FULL_SYSTEM
218                             Rc = 1;
219#else
220                             Rc = 2;
221#endif
222                        }});
223                    }
224                }
225            }
226
227#if FULL_SYSTEM
228            // The mysterious 11.25...
229            0x25: WarnUnimpl::eleven25();
230#endif
231        }
232
233        0x12: decode INTFUNC {
234            0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
235            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
236            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
237
238            0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
239            0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
240            0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
241            0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
242
243            0x52: mskwh({{
244                int bv = Rb_or_imm<2:0>;
245                Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
246            }});
247            0x62: msklh({{
248                int bv = Rb_or_imm<2:0>;
249                Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
250            }});
251            0x72: mskqh({{
252                int bv = Rb_or_imm<2:0>;
253                Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
254            }});
255
256            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
257            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
258            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
259            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
260
261            0x5a: extwh({{
262                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
263            0x6a: extlh({{
264                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
265            0x7a: extqh({{
266                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
267
268            0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
269            0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
270            0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
271            0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
272
273            0x57: inswh({{
274                int bv = Rb_or_imm<2:0>;
275                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
276            }});
277            0x67: inslh({{
278                int bv = Rb_or_imm<2:0>;
279                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
280            }});
281            0x77: insqh({{
282                int bv = Rb_or_imm<2:0>;
283                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
284            }});
285
286            0x30: zap({{
287                uint64_t zapmask = 0;
288                for (int i = 0; i < 8; ++i) {
289                    if (Rb_or_imm<i:>)
290                        zapmask |= (mask(8) << (i * 8));
291                }
292                Rc = Ra & ~zapmask;
293            }});
294            0x31: zapnot({{
295                uint64_t zapmask = 0;
296                for (int i = 0; i < 8; ++i) {
297                    if (!Rb_or_imm<i:>)
298                        zapmask |= (mask(8) << (i * 8));
299                }
300                Rc = Ra & ~zapmask;
301            }});
302        }
303
304        0x13: decode INTFUNC {	// integer multiplies
305            0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
306            0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
307            0x30: umulh({{
308                uint64_t hi, lo;
309                mul128(Ra, Rb_or_imm, hi, lo);
310                Rc = hi;
311            }}, IntMultOp);
312            0x40: mullv({{
313                // 32-bit multiply with trap on overflow
314                int64_t Rax = Ra.sl;	// sign extended version of Ra.sl
315                int64_t Rbx = Rb_or_imm.sl;
316                int64_t tmp = Rax * Rbx;
317                // To avoid overflow, all the upper 32 bits must match
318                // the sign bit of the lower 32.  We code this as
319                // checking the upper 33 bits for all 0s or all 1s.
320                uint64_t sign_bits = tmp<63:31>;
321                if (sign_bits != 0 && sign_bits != mask(33))
322                    fault = new IntegerOverflowFault;
323                Rc.sl = tmp<31:0>;
324            }}, IntMultOp);
325            0x60: mulqv({{
326                // 64-bit multiply with trap on overflow
327                uint64_t hi, lo;
328                mul128(Ra, Rb_or_imm, hi, lo);
329                // all the upper 64 bits must match the sign bit of
330                // the lower 64
331                if (!((hi == 0 && lo<63:> == 0) ||
332                      (hi == mask(64) && lo<63:> == 1)))
333                    fault = new IntegerOverflowFault;
334                Rc = lo;
335            }}, IntMultOp);
336        }
337
338        0x1c: decode INTFUNC {
339            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
340            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
341
342            0x30: ctpop({{
343                             uint64_t count = 0;
344                             for (int i = 0; Rb<63:i>; ++i) {
345                                 if (Rb<i:i> == 0x1)
346                                     ++count;
347                             }
348                             Rc = count;
349                           }}, IntAluOp);
350
351            0x31: perr({{
352                             uint64_t temp = 0;
353                             int hi = 7;
354                             int lo = 0;
355                             for (int i = 0; i < 8; ++i) {
356                                 uint8_t ra_ub = Ra.uq<hi:lo>;
357                                 uint8_t rb_ub = Rb.uq<hi:lo>;
358                                 temp += (ra_ub >= rb_ub) ? 
359                                         (ra_ub - rb_ub) : (rb_ub - ra_ub);
360                                 hi += 8;
361                                 lo += 8;
362                             }
363                             Rc = temp;
364                           }});
365
366            0x32: ctlz({{
367                             uint64_t count = 0;
368                             uint64_t temp = Rb;
369                             if (temp<63:32>) temp >>= 32; else count += 32;
370                             if (temp<31:16>) temp >>= 16; else count += 16;
371                             if (temp<15:8>) temp >>= 8; else count += 8;
372                             if (temp<7:4>) temp >>= 4; else count += 4;
373                             if (temp<3:2>) temp >>= 2; else count += 2;
374                             if (temp<1:1>) temp >>= 1; else count += 1;
375                             if ((temp<0:0>) != 0x1) count += 1;
376                             Rc = count;
377                           }}, IntAluOp);
378
379            0x33: cttz({{
380                             uint64_t count = 0;
381                             uint64_t temp = Rb;
382                             if (!(temp<31:0>)) { temp >>= 32; count += 32; }
383                             if (!(temp<15:0>)) { temp >>= 16; count += 16; }
384                             if (!(temp<7:0>)) { temp >>= 8; count += 8; }
385                             if (!(temp<3:0>)) { temp >>= 4; count += 4; }
386                             if (!(temp<1:0>)) { temp >>= 2; count += 2; }
387                             if (!(temp<0:0> & ULL(0x1))) { 
388                                 temp >>= 1; count += 1; 
389                             }
390                             if (!(temp<0:0> & ULL(0x1))) count += 1;
391                             Rc = count;
392                           }}, IntAluOp);
393
394
395            0x34: unpkbw({{ 
396                             Rc = (Rb.uq<7:0> 
397                                   | (Rb.uq<15:8> << 16) 
398                                   | (Rb.uq<23:16> << 32) 
399                                   | (Rb.uq<31:24> << 48)); 
400                           }}, IntAluOp);
401
402            0x35: unpkbl({{
403                             Rc = (Rb.uq<7:0> | (Rb.uq<15:8> << 32)); 
404                           }}, IntAluOp);
405
406            0x36: pkwb({{
407                             Rc = (Rb.uq<7:0> 
408                                   | (Rb.uq<23:16> << 8) 
409                                   | (Rb.uq<39:32> << 16) 
410                                   | (Rb.uq<55:48> << 24)); 
411                           }}, IntAluOp);
412
413            0x37: pklb({{
414                             Rc = (Rb.uq<7:0> | (Rb.uq<39:32> << 8)); 
415                           }}, IntAluOp);
416
417            0x38: minsb8({{
418                             uint64_t temp = 0;
419                             int hi = 63;
420                             int lo = 56;
421                             for (int i = 7; i >= 0; --i) {
422                                 int8_t ra_sb = Ra.uq<hi:lo>;
423                                 int8_t rb_sb = Rb.uq<hi:lo>;
424                                 temp = ((temp << 8) 
425                                         | ((ra_sb < rb_sb) ? Ra.uq<hi:lo>
426                                                          : Rb.uq<hi:lo>));
427                                 hi -= 8;
428                                 lo -= 8;
429                             }
430                             Rc = temp;
431                          }});
432
433            0x39: minsw4({{
434                             uint64_t temp = 0;
435                             int hi = 63;
436                             int lo = 48;
437                             for (int i = 3; i >= 0; --i) {
438                                 int16_t ra_sw = Ra.uq<hi:lo>;
439                                 int16_t rb_sw = Rb.uq<hi:lo>;
440                                 temp = ((temp << 16) 
441                                         | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
442                                                          : Rb.uq<hi:lo>));
443                                 hi -= 16;
444                                 lo -= 16;
445                             }
446                             Rc = temp;
447                          }});
448
449            0x3a: minub8({{
450                             uint64_t temp = 0;
451                             int hi = 63;
452                             int lo = 56;
453                             for (int i = 7; i >= 0; --i) {
454                                 uint8_t ra_ub = Ra.uq<hi:lo>;
455                                 uint8_t rb_ub = Rb.uq<hi:lo>;
456                                 temp = ((temp << 8) 
457                                         | ((ra_ub < rb_ub) ? Ra.uq<hi:lo>
458                                                          : Rb.uq<hi:lo>));
459                                 hi -= 8;
460                                 lo -= 8;
461                             }
462                             Rc = temp;
463                          }});
464
465            0x3b: minuw4({{
466                             uint64_t temp = 0;
467                             int hi = 63;
468                             int lo = 48;
469                             for (int i = 3; i >= 0; --i) {
470                                 uint16_t ra_sw = Ra.uq<hi:lo>;
471                                 uint16_t rb_sw = Rb.uq<hi:lo>;
472                                 temp = ((temp << 16) 
473                                         | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
474                                                          : Rb.uq<hi:lo>));
475                                 hi -= 16;
476                                 lo -= 16;
477                             }
478                             Rc = temp;
479                          }});
480
481            0x3c: maxub8({{
482                             uint64_t temp = 0;
483                             int hi = 63;
484                             int lo = 56;
485                             for (int i = 7; i >= 0; --i) {
486                                 uint8_t ra_ub = Ra.uq<hi:lo>;
487                                 uint8_t rb_ub = Rb.uq<hi:lo>;
488                                 temp = ((temp << 8) 
489                                         | ((ra_ub > rb_ub) ? Ra.uq<hi:lo>
490                                                          : Rb.uq<hi:lo>));
491                                 hi -= 8;
492                                 lo -= 8;
493                             }
494                             Rc = temp;
495                          }});
496
497            0x3d: maxuw4({{
498                             uint64_t temp = 0;
499                             int hi = 63;
500                             int lo = 48;
501                             for (int i = 3; i >= 0; --i) {
502                                 uint16_t ra_uw = Ra.uq<hi:lo>;
503                                 uint16_t rb_uw = Rb.uq<hi:lo>;
504                                 temp = ((temp << 16) 
505                                         | ((ra_uw > rb_uw) ? Ra.uq<hi:lo>
506                                                          : Rb.uq<hi:lo>));
507                                 hi -= 16;
508                                 lo -= 16;
509                             }
510                             Rc = temp;
511                          }});
512
513            0x3e: maxsb8({{
514                             uint64_t temp = 0;
515                             int hi = 63;
516                             int lo = 56;
517                             for (int i = 7; i >= 0; --i) {
518                                 int8_t ra_sb = Ra.uq<hi:lo>;
519                                 int8_t rb_sb = Rb.uq<hi:lo>;
520                                 temp = ((temp << 8) 
521                                         | ((ra_sb > rb_sb) ? Ra.uq<hi:lo>
522                                                          : Rb.uq<hi:lo>));
523                                 hi -= 8;
524                                 lo -= 8;
525                             }
526                             Rc = temp;
527                          }});
528
529            0x3f: maxsw4({{
530                             uint64_t temp = 0;
531                             int hi = 63;
532                             int lo = 48;
533                             for (int i = 3; i >= 0; --i) {
534                                 int16_t ra_sw = Ra.uq<hi:lo>;
535                                 int16_t rb_sw = Rb.uq<hi:lo>;
536                                 temp = ((temp << 16) 
537                                         | ((ra_sw > rb_sw) ? Ra.uq<hi:lo>
538                                                          : Rb.uq<hi:lo>));
539                                 hi -= 16;
540                                 lo -= 16;
541                             }
542                             Rc = temp;
543                          }});
544
545            format BasicOperateWithNopCheck {
546                0x70: decode RB {
547                    31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
548                }
549                0x78: decode RB {
550                    31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
551                              FloatCvtOp);
552                }
553            }
554        }
555    }
556
557    // Conditional branches.
558    format CondBranch {
559        0x39: beq({{ cond = (Ra == 0); }});
560        0x3d: bne({{ cond = (Ra != 0); }});
561        0x3e: bge({{ cond = (Ra.sq >= 0); }});
562        0x3f: bgt({{ cond = (Ra.sq >  0); }});
563        0x3b: ble({{ cond = (Ra.sq <= 0); }});
564        0x3a: blt({{ cond = (Ra.sq < 0); }});
565        0x38: blbc({{ cond = ((Ra & 1) == 0); }});
566        0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
567
568        0x31: fbeq({{ cond = (Fa == 0); }});
569        0x35: fbne({{ cond = (Fa != 0); }});
570        0x36: fbge({{ cond = (Fa >= 0); }});
571        0x37: fbgt({{ cond = (Fa >  0); }});
572        0x33: fble({{ cond = (Fa <= 0); }});
573        0x32: fblt({{ cond = (Fa < 0); }});
574    }
575
576    // unconditional branches
577    format UncondBranch {
578        0x30: br();
579        0x34: bsr(IsCall);
580    }
581
582    // indirect branches
583    0x1a: decode JMPFUNC {
584        format Jump {
585            0: jmp();
586            1: jsr(IsCall);
587            2: ret(IsReturn);
588            3: jsr_coroutine(IsCall, IsReturn);
589        }
590    }
591
592    // Square root and integer-to-FP moves
593    0x14: decode FP_SHORTFUNC {
594        // Integer to FP register moves must have RB == 31
595        0x4: decode RB {
596            31: decode FP_FULLFUNC {
597                format BasicOperateWithNopCheck {
598                    0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
599                    0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
600                    0x014: FailUnimpl::itoff();	// VAX-format conversion
601                }
602            }
603        }
604
605        // Square root instructions must have FA == 31
606        0xb: decode FA {
607            31: decode FP_TYPEFUNC {
608                format FloatingPointOperate {
609#if SS_COMPATIBLE_FP
610                    0x0b: sqrts({{
611                        if (Fb < 0.0)
612                            fault = new ArithmeticFault;
613                        Fc = sqrt(Fb);
614                    }}, FloatSqrtOp);
615#else
616                    0x0b: sqrts({{
617                        if (Fb.sf < 0.0)
618                            fault = new ArithmeticFault;
619                        Fc.sf = sqrt(Fb.sf);
620                    }}, FloatSqrtOp);
621#endif
622                    0x2b: sqrtt({{
623                        if (Fb < 0.0)
624                            fault = new ArithmeticFault;
625                        Fc = sqrt(Fb);
626                    }}, FloatSqrtOp);
627                }
628            }
629        }
630
631        // VAX-format sqrtf and sqrtg are not implemented
632        0xa: FailUnimpl::sqrtfg();
633    }
634
635    // IEEE floating point
636    0x16: decode FP_SHORTFUNC_TOP2 {
637        // The top two bits of the short function code break this
638        // space into four groups: binary ops, compares, reserved, and
639        // conversions.  See Table 4-12 of AHB.  There are different
640        // special cases in these different groups, so we decode on
641        // these top two bits first just to select a decode strategy.
642        // Most of these instructions may have various trapping and
643        // rounding mode flags set; these are decoded in the
644        // FloatingPointDecode template used by the
645        // FloatingPointOperate format.
646
647        // add/sub/mul/div: just decode on the short function code
648        // and source type.  All valid trapping and rounding modes apply.
649        0: decode FP_TRAPMODE {
650            // check for valid trapping modes here
651            0,1,5,7: decode FP_TYPEFUNC {
652                   format FloatingPointOperate {
653#if SS_COMPATIBLE_FP
654                       0x00: adds({{ Fc = Fa + Fb; }});
655                       0x01: subs({{ Fc = Fa - Fb; }});
656                       0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
657                       0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
658#else
659                       0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
660                       0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
661                       0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
662                       0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
663#endif
664
665                       0x20: addt({{ Fc = Fa + Fb; }});
666                       0x21: subt({{ Fc = Fa - Fb; }});
667                       0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
668                       0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
669                   }
670             }
671        }
672
673        // Floating-point compare instructions must have the default
674        // rounding mode, and may use the default trapping mode or
675        // /SU.  Both trapping modes are treated the same by M5; the
676        // only difference on the real hardware (as far a I can tell)
677        // is that without /SU you'd get an imprecise trap if you
678        // tried to compare a NaN with something else (instead of an
679        // "unordered" result).
680        1: decode FP_FULLFUNC {
681            format BasicOperateWithNopCheck {
682                0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
683                                     FloatCmpOp);
684                0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
685                                     FloatCmpOp);
686                0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
687                                     FloatCmpOp);
688                0x0a4, 0x5a4: cmptun({{ // unordered
689                    Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
690                }}, FloatCmpOp);
691            }
692        }
693
694        // The FP-to-integer and integer-to-FP conversion insts
695        // require that FA be 31.
696        3: decode FA {
697            31: decode FP_TYPEFUNC {
698                format FloatingPointOperate {
699                    0x2f: decode FP_ROUNDMODE {
700                        format FPFixedRounding {
701                            // "chopped" i.e. round toward zero
702                            0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
703                                     Chopped);
704                            // round to minus infinity
705                            1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
706                                     MinusInfinity);
707                        }
708                      default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
709                    }
710
711                    // The cvtts opcode is overloaded to be cvtst if the trap
712                    // mode is 2 or 6 (which are not valid otherwise)
713                    0x2c: decode FP_FULLFUNC {
714                        format BasicOperateWithNopCheck {
715                            // trap on denorm version "cvtst/s" is
716                            // simulated same as cvtst
717                            0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
718                        }
719                      default: cvtts({{ Fc.sf = Fb; }});
720                    }
721
722                    // The trapping mode for integer-to-FP conversions
723                    // must be /SUI or nothing; /U and /SU are not
724                    // allowed.  The full set of rounding modes are
725                    // supported though.
726                    0x3c: decode FP_TRAPMODE {
727                        0,7: cvtqs({{ Fc.sf = Fb.sq; }});
728                    }
729                    0x3e: decode FP_TRAPMODE {
730                        0,7: cvtqt({{ Fc    = Fb.sq; }});
731                    }
732                }
733            }
734        }
735    }
736
737    // misc FP operate
738    0x17: decode FP_FULLFUNC {
739        format BasicOperateWithNopCheck {
740            0x010: cvtlq({{
741                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
742            }});
743            0x030: cvtql({{
744                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
745            }});
746
747            // We treat the precise & imprecise trapping versions of
748            // cvtql identically.
749            0x130, 0x530: cvtqlv({{
750                // To avoid overflow, all the upper 32 bits must match
751                // the sign bit of the lower 32.  We code this as
752                // checking the upper 33 bits for all 0s or all 1s.
753                uint64_t sign_bits = Fb.uq<63:31>;
754                if (sign_bits != 0 && sign_bits != mask(33))
755                    fault = new IntegerOverflowFault;
756                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
757            }});
758
759            0x020: cpys({{  // copy sign
760                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
761            }});
762            0x021: cpysn({{ // copy sign negated
763                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
764            }});
765            0x022: cpyse({{ // copy sign and exponent
766                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
767            }});
768
769            0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
770            0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
771            0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
772            0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
773            0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
774            0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
775
776            0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
777            0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
778        }
779    }
780
781    // miscellaneous mem-format ops
782    0x18: decode MEMFUNC {
783        format WarnUnimpl {
784            0x8000: fetch();
785            0xa000: fetch_m();
786            0xe800: ecb();
787        }
788
789        format MiscPrefetch {
790            0xf800: wh64({{ EA = Rb & ~ULL(63); }},
791                         {{ xc->writeHint(EA, 64, memAccessFlags); }},
792                         mem_flags = PREFETCH,
793                         inst_flags = [IsMemRef, IsDataPrefetch,
794                                       IsStore, MemWriteOp]);
795        }
796
797        format BasicOperate {
798            0xc000: rpcc({{
799#if FULL_SYSTEM
800        /* Rb is a fake dependency so here is a fun way to get
801         * the parser to understand that.
802         */
803                Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
804
805#else
806                Ra = curTick;
807#endif
808            }}, IsUnverifiable);
809
810            // All of the barrier instructions below do nothing in
811            // their execute() methods (hence the empty code blocks).
812            // All of their functionality is hard-coded in the
813            // pipeline based on the flags IsSerializing,
814            // IsMemBarrier, and IsWriteBarrier.  In the current
815            // detailed CPU model, the execute() function only gets
816            // called at fetch, so there's no way to generate pipeline
817            // behavior at any other stage.  Once we go to an
818            // exec-in-exec CPU model we should be able to get rid of
819            // these flags and implement this behavior via the
820            // execute() methods.
821
822            // trapb is just a barrier on integer traps, where excb is
823            // a barrier on integer and FP traps.  "EXCB is thus a
824            // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
825            // them the same though.
826            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
827            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
828            0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
829            0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
830        }
831
832#if FULL_SYSTEM
833        format BasicOperate {
834            0xe000: rc({{
835                Ra = IntrFlag;
836                IntrFlag = 0;
837            }}, IsNonSpeculative, IsUnverifiable);
838            0xf000: rs({{
839                Ra = IntrFlag;
840                IntrFlag = 1;
841            }}, IsNonSpeculative, IsUnverifiable);
842        }
843#else
844        format FailUnimpl {
845            0xe000: rc();
846            0xf000: rs();
847        }
848#endif
849    }
850
851#if FULL_SYSTEM
852    0x00: CallPal::call_pal({{
853        if (!palValid ||
854            (palPriv
855             && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
856            // invalid pal function code, or attempt to do privileged
857            // PAL call in non-kernel mode
858            fault = new UnimplementedOpcodeFault;
859        } else {
860            // check to see if simulator wants to do something special
861            // on this PAL call (including maybe suppress it)
862            bool dopal = xc->simPalCheck(palFunc);
863
864            if (dopal) {
865                PCState pc = PCS;
866                xc->setMiscReg(IPR_EXC_ADDR, pc.npc());
867                pc.npc(xc->readMiscReg(IPR_PAL_BASE) + palOffset);
868                PCS = pc;
869            }
870        }
871    }}, IsNonSpeculative);
872#else
873    0x00: decode PALFUNC {
874        format EmulatedCallPal {
875            0x00: halt ({{
876                exitSimLoop("halt instruction encountered");
877            }}, IsNonSpeculative);
878            0x83: callsys({{
879                xc->syscall(R0);
880            }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
881            // Read uniq reg into ABI return value register (r0)
882            0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
883            // Write uniq reg with value from ABI arg register (r16)
884            0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
885        }
886    }
887#endif
888
889#if FULL_SYSTEM
890    0x1b: decode PALMODE {
891        0: OpcdecFault::hw_st_quad();
892        1: decode HW_LDST_QUAD {
893            format HwLoad {
894                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
895                         L, IsSerializing, IsSerializeBefore);
896                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
897                         Q, IsSerializing, IsSerializeBefore);
898            }
899        }
900    }
901
902    0x1f: decode PALMODE {
903        0: OpcdecFault::hw_st_cond();
904        format HwStore {
905            1: decode HW_LDST_COND {
906                0: decode HW_LDST_QUAD {
907                    0: hw_st({{ EA = (Rb + disp) & ~3; }},
908                {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
909                    1: hw_st({{ EA = (Rb + disp) & ~7; }},
910                {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
911                }
912
913                1: FailUnimpl::hw_st_cond();
914            }
915        }
916    }
917
918    0x19: decode PALMODE {
919        0: OpcdecFault::hw_mfpr();
920        format HwMoveIPR {
921            1: hw_mfpr({{
922                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
923                        IprToMiscRegIndex[ipr_index] : -1;
924                if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
925                    miscRegIndex >= NumInternalProcRegs)
926                        fault = new UnimplementedOpcodeFault;
927                else
928                    Ra = xc->readMiscReg(miscRegIndex);
929            }}, IsIprAccess);
930        }
931    }
932
933    0x1d: decode PALMODE {
934        0: OpcdecFault::hw_mtpr();
935        format HwMoveIPR {
936            1: hw_mtpr({{
937                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
938                        IprToMiscRegIndex[ipr_index] : -1;
939                if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
940                    miscRegIndex >= NumInternalProcRegs)
941                        fault = new UnimplementedOpcodeFault;
942                else
943                    xc->setMiscReg(miscRegIndex, Ra);
944                if (traceData) { traceData->setData(Ra); }
945            }}, IsIprAccess);
946        }
947    }
948
949  0x1e: decode PALMODE {
950      0: OpcdecFault::hw_rei();
951        format BasicOperate {
952          1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
953        }
954    }
955
956#endif
957
958    format BasicOperate {
959        // M5 special opcodes use the reserved 0x01 opcode space
960        0x01: decode M5FUNC {
961#if FULL_SYSTEM
962            0x00: arm({{
963                PseudoInst::arm(xc->tcBase());
964            }}, IsNonSpeculative);
965            0x01: quiesce({{
966                PseudoInst::quiesce(xc->tcBase());
967            }}, IsNonSpeculative, IsQuiesce);
968            0x02: quiesceNs({{
969                PseudoInst::quiesceNs(xc->tcBase(), R16);
970            }}, IsNonSpeculative, IsQuiesce);
971            0x03: quiesceCycles({{
972                PseudoInst::quiesceCycles(xc->tcBase(), R16);
973            }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
974            0x04: quiesceTime({{
975                R0 = PseudoInst::quiesceTime(xc->tcBase());
976            }}, IsNonSpeculative, IsUnverifiable);
977#endif
978            0x07: rpns({{
979                R0 = PseudoInst::rpns(xc->tcBase());
980            }}, IsNonSpeculative, IsUnverifiable);
981            0x09: wakeCPU({{
982                PseudoInst::wakeCPU(xc->tcBase(), R16);
983            }}, IsNonSpeculative, IsUnverifiable);
984            0x10: deprecated_ivlb({{
985                warn_once("Obsolete M5 ivlb instruction encountered.\n");
986            }});
987            0x11: deprecated_ivle({{
988                warn_once("Obsolete M5 ivlb instruction encountered.\n");
989            }});
990            0x20: deprecated_exit ({{
991                warn_once("deprecated M5 exit instruction encountered.\n");
992                PseudoInst::m5exit(xc->tcBase(), 0);
993            }}, No_OpClass, IsNonSpeculative);
994            0x21: m5exit({{
995                PseudoInst::m5exit(xc->tcBase(), R16);
996            }}, No_OpClass, IsNonSpeculative);
997#if FULL_SYSTEM
998            0x31: loadsymbol({{
999                PseudoInst::loadsymbol(xc->tcBase());
1000            }}, No_OpClass, IsNonSpeculative);
1001            0x30: initparam({{
1002                Ra = xc->tcBase()->getCpuPtr()->system->init_param;
1003            }});
1004#endif
1005            0x40: resetstats({{
1006                PseudoInst::resetstats(xc->tcBase(), R16, R17);
1007            }}, IsNonSpeculative);
1008            0x41: dumpstats({{
1009                PseudoInst::dumpstats(xc->tcBase(), R16, R17);
1010            }}, IsNonSpeculative);
1011            0x42: dumpresetstats({{
1012                PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
1013            }}, IsNonSpeculative);
1014            0x43: m5checkpoint({{
1015                PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
1016            }}, IsNonSpeculative);
1017#if FULL_SYSTEM
1018            0x50: m5readfile({{
1019                R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
1020            }}, IsNonSpeculative);
1021#endif
1022            0x51: m5break({{
1023                PseudoInst::debugbreak(xc->tcBase());
1024            }}, IsNonSpeculative);
1025            0x52: m5switchcpu({{
1026                PseudoInst::switchcpu(xc->tcBase());
1027            }}, IsNonSpeculative);
1028#if FULL_SYSTEM
1029            0x53: m5addsymbol({{
1030                PseudoInst::addsymbol(xc->tcBase(), R16, R17);
1031            }}, IsNonSpeculative);
1032#endif
1033            0x54: m5panic({{
1034                panic("M5 panic instruction called at pc=%#x.",
1035                    xc->pcState().pc());
1036            }}, IsNonSpeculative);
1037#define  CPANN(lbl) CPA::cpa()->lbl(xc->tcBase())
1038            0x55: decode RA {
1039                0x00: m5a_old({{
1040                    panic("Deprecated M5 annotate instruction executed at pc=%#x\n",
1041                        xc->pcState().pc());
1042                }}, IsNonSpeculative);
1043                0x01: m5a_bsm({{
1044                    CPANN(swSmBegin);
1045                }}, IsNonSpeculative);
1046                0x02: m5a_esm({{
1047                    CPANN(swSmEnd);
1048                }}, IsNonSpeculative);
1049                0x03: m5a_begin({{
1050                    CPANN(swExplictBegin);
1051                }}, IsNonSpeculative);
1052                0x04: m5a_end({{
1053                    CPANN(swEnd);
1054                }}, IsNonSpeculative);
1055                0x06: m5a_q({{
1056                    CPANN(swQ);
1057                }}, IsNonSpeculative);
1058                0x07: m5a_dq({{
1059                    CPANN(swDq);
1060                }}, IsNonSpeculative);
1061                0x08: m5a_wf({{
1062                    CPANN(swWf);
1063                }}, IsNonSpeculative);
1064                0x09: m5a_we({{
1065                    CPANN(swWe);
1066                }}, IsNonSpeculative);
1067                0x0C: m5a_sq({{
1068                    CPANN(swSq);
1069                }}, IsNonSpeculative);
1070                0x0D: m5a_aq({{
1071                    CPANN(swAq);
1072                }}, IsNonSpeculative);
1073                0x0E: m5a_pq({{
1074                    CPANN(swPq);
1075                }}, IsNonSpeculative);
1076                0x0F: m5a_l({{
1077                    CPANN(swLink);
1078                }}, IsNonSpeculative);
1079                0x10: m5a_identify({{
1080                    CPANN(swIdentify);
1081                }}, IsNonSpeculative);
1082                0x11: m5a_getid({{
1083                    R0 = CPANN(swGetId);
1084                }}, IsNonSpeculative);
1085                0x13: m5a_scl({{
1086                    CPANN(swSyscallLink);
1087                }}, IsNonSpeculative);
1088                0x14: m5a_rq({{
1089                    CPANN(swRq);
1090                }}, IsNonSpeculative);
1091            } // M5 Annotate Operations
1092#undef CPANN
1093            0x56: m5reserved2({{
1094                warn("M5 reserved opcode ignored");
1095            }}, IsNonSpeculative);
1096            0x57: m5reserved3({{
1097                warn("M5 reserved opcode ignored");
1098            }}, IsNonSpeculative);
1099            0x58: m5reserved4({{
1100                warn("M5 reserved opcode ignored");
1101            }}, IsNonSpeculative);
1102            0x59: m5reserved5({{
1103                warn("M5 reserved opcode ignored");
1104            }}, IsNonSpeculative);
1105        }
1106    }
1107}
1108