decoder.isa revision 2721:dc6524ccab53
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OPCODE default Unknown::unknown() {
37
38    format LoadAddress {
39        0x08: lda({{ Ra = Rb + disp; }});
40        0x09: ldah({{ Ra = Rb + (disp << 16); }});
41    }
42
43    format LoadOrNop {
44        0x0a: ldbu({{ Ra.uq = Mem.ub; }});
45        0x0c: ldwu({{ Ra.uq = Mem.uw; }});
46        0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
47        0x23: ldt({{ Fa = Mem.df; }});
48        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
49        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
50        0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
51                                      {{ fault = xc->copySrcTranslate(EA); }},
52                                      inst_flags = [IsMemRef, IsLoad, IsCopy]);
53    }
54
55    format LoadOrPrefetch {
56        0x28: ldl({{ Ra.sl = Mem.sl; }});
57        0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
58        // IsFloating flag on lds gets the prefetch to disassemble
59        // using f31 instead of r31... funcitonally it's unnecessary
60        0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
61                  pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
62    }
63
64    format Store {
65        0x0e: stb({{ Mem.ub = Ra<7:0>; }});
66        0x0d: stw({{ Mem.uw = Ra<15:0>; }});
67        0x2c: stl({{ Mem.ul = Ra<31:0>; }});
68        0x2d: stq({{ Mem.uq = Ra.uq; }});
69        0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
70        0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
71        0x27: stt({{ Mem.df = Fa; }});
72        0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
73                                       {{ fault = xc->copy(EA); }},
74                                       inst_flags = [IsMemRef, IsStore, IsCopy]);
75    }
76
77    format StoreCond {
78        0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
79                    {{
80                        uint64_t tmp = write_result;
81                        // see stq_c
82                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
83                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
84        0x2f: stq_c({{ Mem.uq = Ra; }},
85                    {{
86                        uint64_t tmp = write_result;
87                        // If the write operation returns 0 or 1, then
88                        // this was a conventional store conditional,
89                        // and the value indicates the success/failure
90                        // of the operation.  If another value is
91                        // returned, then this was a Turbolaser
92                        // mailbox access, and we don't update the
93                        // result register at all.
94                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
95                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
96    }
97
98    format IntegerOperate {
99
100        0x10: decode INTFUNC {	// integer arithmetic operations
101
102            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
103            0x40: addlv({{
104                uint32_t tmp  = Ra.sl + Rb_or_imm.sl;
105                // signed overflow occurs when operands have same sign
106                // and sign of result does not match.
107                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
108                    fault = new IntegerOverflowFault;
109                Rc.sl = tmp;
110            }});
111            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
112            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
113
114            0x20: addq({{ Rc = Ra + Rb_or_imm; }});
115            0x60: addqv({{
116                uint64_t tmp = Ra + Rb_or_imm;
117                // signed overflow occurs when operands have same sign
118                // and sign of result does not match.
119                if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
120                    fault = new IntegerOverflowFault;
121                Rc = tmp;
122            }});
123            0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
124            0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
125
126            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
127            0x49: sublv({{
128                uint32_t tmp  = Ra.sl - Rb_or_imm.sl;
129                // signed overflow detection is same as for add,
130                // except we need to look at the *complemented*
131                // sign bit of the subtrahend (Rb), i.e., if the initial
132                // signs are the *same* then no overflow can occur
133                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
134                    fault = new IntegerOverflowFault;
135                Rc.sl = tmp;
136            }});
137            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
138            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
139
140            0x29: subq({{ Rc = Ra - Rb_or_imm; }});
141            0x69: subqv({{
142                uint64_t tmp  = Ra - Rb_or_imm;
143                // signed overflow detection is same as for add,
144                // except we need to look at the *complemented*
145                // sign bit of the subtrahend (Rb), i.e., if the initial
146                // signs are the *same* then no overflow can occur
147                if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
148                    fault = new IntegerOverflowFault;
149                Rc = tmp;
150            }});
151            0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
152            0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
153
154            0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
155            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
156            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
157            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
158            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
159
160            0x0f: cmpbge({{
161                int hi = 7;
162                int lo = 0;
163                uint64_t tmp = 0;
164                for (int i = 0; i < 8; ++i) {
165                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
166                    hi += 8;
167                    lo += 8;
168                }
169                Rc = tmp;
170            }});
171        }
172
173        0x11: decode INTFUNC {	// integer logical operations
174
175            0x00: and({{ Rc = Ra & Rb_or_imm; }});
176            0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
177            0x20: bis({{ Rc = Ra | Rb_or_imm; }});
178            0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
179            0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
180            0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
181
182            // conditional moves
183            0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
184            0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
185            0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
186            0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
187            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
188            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
189            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
190            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
191
192            // For AMASK, RA must be R31.
193            0x61: decode RA {
194                31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
195            }
196
197            // For IMPLVER, RA must be R31 and the B operand
198            // must be the immediate value 1.
199            0x6c: decode RA {
200                31: decode IMM {
201                    1: decode INTIMM {
202                        // return EV5 for FULL_SYSTEM and EV6 otherwise
203                        1: implver({{
204#if FULL_SYSTEM
205                             Rc = 1;
206#else
207                             Rc = 2;
208#endif
209                        }});
210                    }
211                }
212            }
213
214#if FULL_SYSTEM
215            // The mysterious 11.25...
216            0x25: WarnUnimpl::eleven25();
217#endif
218        }
219
220        0x12: decode INTFUNC {
221            0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
222            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
223            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
224
225            0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
226            0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
227            0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
228            0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
229
230            0x52: mskwh({{
231                int bv = Rb_or_imm<2:0>;
232                Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
233            }});
234            0x62: msklh({{
235                int bv = Rb_or_imm<2:0>;
236                Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
237            }});
238            0x72: mskqh({{
239                int bv = Rb_or_imm<2:0>;
240                Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
241            }});
242
243            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
244            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
245            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
246            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
247
248            0x5a: extwh({{
249                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
250            0x6a: extlh({{
251                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
252            0x7a: extqh({{
253                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
254
255            0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
256            0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
257            0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
258            0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
259
260            0x57: inswh({{
261                int bv = Rb_or_imm<2:0>;
262                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
263            }});
264            0x67: inslh({{
265                int bv = Rb_or_imm<2:0>;
266                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
267            }});
268            0x77: insqh({{
269                int bv = Rb_or_imm<2:0>;
270                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
271            }});
272
273            0x30: zap({{
274                uint64_t zapmask = 0;
275                for (int i = 0; i < 8; ++i) {
276                    if (Rb_or_imm<i:>)
277                        zapmask |= (mask(8) << (i * 8));
278                }
279                Rc = Ra & ~zapmask;
280            }});
281            0x31: zapnot({{
282                uint64_t zapmask = 0;
283                for (int i = 0; i < 8; ++i) {
284                    if (!Rb_or_imm<i:>)
285                        zapmask |= (mask(8) << (i * 8));
286                }
287                Rc = Ra & ~zapmask;
288            }});
289        }
290
291        0x13: decode INTFUNC {	// integer multiplies
292            0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
293            0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
294            0x30: umulh({{
295                uint64_t hi, lo;
296                mul128(Ra, Rb_or_imm, hi, lo);
297                Rc = hi;
298            }}, IntMultOp);
299            0x40: mullv({{
300                // 32-bit multiply with trap on overflow
301                int64_t Rax = Ra.sl;	// sign extended version of Ra.sl
302                int64_t Rbx = Rb_or_imm.sl;
303                int64_t tmp = Rax * Rbx;
304                // To avoid overflow, all the upper 32 bits must match
305                // the sign bit of the lower 32.  We code this as
306                // checking the upper 33 bits for all 0s or all 1s.
307                uint64_t sign_bits = tmp<63:31>;
308                if (sign_bits != 0 && sign_bits != mask(33))
309                    fault = new IntegerOverflowFault;
310                Rc.sl = tmp<31:0>;
311            }}, IntMultOp);
312            0x60: mulqv({{
313                // 64-bit multiply with trap on overflow
314                uint64_t hi, lo;
315                mul128(Ra, Rb_or_imm, hi, lo);
316                // all the upper 64 bits must match the sign bit of
317                // the lower 64
318                if (!((hi == 0 && lo<63:> == 0) ||
319                      (hi == mask(64) && lo<63:> == 1)))
320                    fault = new IntegerOverflowFault;
321                Rc = lo;
322            }}, IntMultOp);
323        }
324
325        0x1c: decode INTFUNC {
326            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
327            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
328            0x32: ctlz({{
329                             uint64_t count = 0;
330                             uint64_t temp = Rb;
331                             if (temp<63:32>) temp >>= 32; else count += 32;
332                             if (temp<31:16>) temp >>= 16; else count += 16;
333                             if (temp<15:8>) temp >>= 8; else count += 8;
334                             if (temp<7:4>) temp >>= 4; else count += 4;
335                             if (temp<3:2>) temp >>= 2; else count += 2;
336                             if (temp<1:1>) temp >>= 1; else count += 1;
337                             if ((temp<0:0>) != 0x1) count += 1;
338                             Rc = count;
339                           }}, IntAluOp);
340
341            0x33: cttz({{
342                             uint64_t count = 0;
343                             uint64_t temp = Rb;
344                             if (!(temp<31:0>)) { temp >>= 32; count += 32; }
345                             if (!(temp<15:0>)) { temp >>= 16; count += 16; }
346                             if (!(temp<7:0>)) { temp >>= 8; count += 8; }
347                             if (!(temp<3:0>)) { temp >>= 4; count += 4; }
348                             if (!(temp<1:0>)) { temp >>= 2; count += 2; }
349                             if (!(temp<0:0> & ULL(0x1))) count += 1;
350                             Rc = count;
351                           }}, IntAluOp);
352
353            format FailUnimpl {
354                0x30: ctpop();
355                0x31: perr();
356                0x34: unpkbw();
357                0x35: unpkbl();
358                0x36: pkwb();
359                0x37: pklb();
360                0x38: minsb8();
361                0x39: minsw4();
362                0x3a: minub8();
363                0x3b: minuw4();
364                0x3c: maxub8();
365                0x3d: maxuw4();
366                0x3e: maxsb8();
367                0x3f: maxsw4();
368            }
369
370            format BasicOperateWithNopCheck {
371                0x70: decode RB {
372                    31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
373                }
374                0x78: decode RB {
375                    31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
376                              FloatCvtOp);
377                }
378            }
379        }
380    }
381
382    // Conditional branches.
383    format CondBranch {
384        0x39: beq({{ cond = (Ra == 0); }});
385        0x3d: bne({{ cond = (Ra != 0); }});
386        0x3e: bge({{ cond = (Ra.sq >= 0); }});
387        0x3f: bgt({{ cond = (Ra.sq >  0); }});
388        0x3b: ble({{ cond = (Ra.sq <= 0); }});
389        0x3a: blt({{ cond = (Ra.sq < 0); }});
390        0x38: blbc({{ cond = ((Ra & 1) == 0); }});
391        0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
392
393        0x31: fbeq({{ cond = (Fa == 0); }});
394        0x35: fbne({{ cond = (Fa != 0); }});
395        0x36: fbge({{ cond = (Fa >= 0); }});
396        0x37: fbgt({{ cond = (Fa >  0); }});
397        0x33: fble({{ cond = (Fa <= 0); }});
398        0x32: fblt({{ cond = (Fa < 0); }});
399    }
400
401    // unconditional branches
402    format UncondBranch {
403        0x30: br();
404        0x34: bsr(IsCall);
405    }
406
407    // indirect branches
408    0x1a: decode JMPFUNC {
409        format Jump {
410            0: jmp();
411            1: jsr(IsCall);
412            2: ret(IsReturn);
413            3: jsr_coroutine(IsCall, IsReturn);
414        }
415    }
416
417    // Square root and integer-to-FP moves
418    0x14: decode FP_SHORTFUNC {
419        // Integer to FP register moves must have RB == 31
420        0x4: decode RB {
421            31: decode FP_FULLFUNC {
422                format BasicOperateWithNopCheck {
423                    0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
424                    0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
425                    0x014: FailUnimpl::itoff();	// VAX-format conversion
426                }
427            }
428        }
429
430        // Square root instructions must have FA == 31
431        0xb: decode FA {
432            31: decode FP_TYPEFUNC {
433                format FloatingPointOperate {
434#if SS_COMPATIBLE_FP
435                    0x0b: sqrts({{
436                        if (Fb < 0.0)
437                            fault = new ArithmeticFault;
438                        Fc = sqrt(Fb);
439                    }}, FloatSqrtOp);
440#else
441                    0x0b: sqrts({{
442                        if (Fb.sf < 0.0)
443                            fault = new ArithmeticFault;
444                        Fc.sf = sqrt(Fb.sf);
445                    }}, FloatSqrtOp);
446#endif
447                    0x2b: sqrtt({{
448                        if (Fb < 0.0)
449                            fault = new ArithmeticFault;
450                        Fc = sqrt(Fb);
451                    }}, FloatSqrtOp);
452                }
453            }
454        }
455
456        // VAX-format sqrtf and sqrtg are not implemented
457        0xa: FailUnimpl::sqrtfg();
458    }
459
460    // IEEE floating point
461    0x16: decode FP_SHORTFUNC_TOP2 {
462        // The top two bits of the short function code break this
463        // space into four groups: binary ops, compares, reserved, and
464        // conversions.  See Table 4-12 of AHB.  There are different
465        // special cases in these different groups, so we decode on
466        // these top two bits first just to select a decode strategy.
467        // Most of these instructions may have various trapping and
468        // rounding mode flags set; these are decoded in the
469        // FloatingPointDecode template used by the
470        // FloatingPointOperate format.
471
472        // add/sub/mul/div: just decode on the short function code
473        // and source type.  All valid trapping and rounding modes apply.
474        0: decode FP_TRAPMODE {
475            // check for valid trapping modes here
476            0,1,5,7: decode FP_TYPEFUNC {
477                   format FloatingPointOperate {
478#if SS_COMPATIBLE_FP
479                       0x00: adds({{ Fc = Fa + Fb; }});
480                       0x01: subs({{ Fc = Fa - Fb; }});
481                       0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
482                       0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
483#else
484                       0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
485                       0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
486                       0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
487                       0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
488#endif
489
490                       0x20: addt({{ Fc = Fa + Fb; }});
491                       0x21: subt({{ Fc = Fa - Fb; }});
492                       0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
493                       0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
494                   }
495             }
496        }
497
498        // Floating-point compare instructions must have the default
499        // rounding mode, and may use the default trapping mode or
500        // /SU.  Both trapping modes are treated the same by M5; the
501        // only difference on the real hardware (as far a I can tell)
502        // is that without /SU you'd get an imprecise trap if you
503        // tried to compare a NaN with something else (instead of an
504        // "unordered" result).
505        1: decode FP_FULLFUNC {
506            format BasicOperateWithNopCheck {
507                0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
508                                     FloatCmpOp);
509                0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
510                                     FloatCmpOp);
511                0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
512                                     FloatCmpOp);
513                0x0a4, 0x5a4: cmptun({{ // unordered
514                    Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
515                }}, FloatCmpOp);
516            }
517        }
518
519        // The FP-to-integer and integer-to-FP conversion insts
520        // require that FA be 31.
521        3: decode FA {
522            31: decode FP_TYPEFUNC {
523                format FloatingPointOperate {
524                    0x2f: decode FP_ROUNDMODE {
525                        format FPFixedRounding {
526                            // "chopped" i.e. round toward zero
527                            0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
528                                     Chopped);
529                            // round to minus infinity
530                            1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
531                                     MinusInfinity);
532                        }
533                      default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
534                    }
535
536                    // The cvtts opcode is overloaded to be cvtst if the trap
537                    // mode is 2 or 6 (which are not valid otherwise)
538                    0x2c: decode FP_FULLFUNC {
539                        format BasicOperateWithNopCheck {
540                            // trap on denorm version "cvtst/s" is
541                            // simulated same as cvtst
542                            0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
543                        }
544                      default: cvtts({{ Fc.sf = Fb; }});
545                    }
546
547                    // The trapping mode for integer-to-FP conversions
548                    // must be /SUI or nothing; /U and /SU are not
549                    // allowed.  The full set of rounding modes are
550                    // supported though.
551                    0x3c: decode FP_TRAPMODE {
552                        0,7: cvtqs({{ Fc.sf = Fb.sq; }});
553                    }
554                    0x3e: decode FP_TRAPMODE {
555                        0,7: cvtqt({{ Fc    = Fb.sq; }});
556                    }
557                }
558            }
559        }
560    }
561
562    // misc FP operate
563    0x17: decode FP_FULLFUNC {
564        format BasicOperateWithNopCheck {
565            0x010: cvtlq({{
566                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
567            }});
568            0x030: cvtql({{
569                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
570            }});
571
572            // We treat the precise & imprecise trapping versions of
573            // cvtql identically.
574            0x130, 0x530: cvtqlv({{
575                // To avoid overflow, all the upper 32 bits must match
576                // the sign bit of the lower 32.  We code this as
577                // checking the upper 33 bits for all 0s or all 1s.
578                uint64_t sign_bits = Fb.uq<63:31>;
579                if (sign_bits != 0 && sign_bits != mask(33))
580                    fault = new IntegerOverflowFault;
581                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
582            }});
583
584            0x020: cpys({{  // copy sign
585                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
586            }});
587            0x021: cpysn({{ // copy sign negated
588                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
589            }});
590            0x022: cpyse({{ // copy sign and exponent
591                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
592            }});
593
594            0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
595            0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
596            0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
597            0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
598            0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
599            0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
600
601            0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
602            0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
603        }
604    }
605
606    // miscellaneous mem-format ops
607    0x18: decode MEMFUNC {
608        format WarnUnimpl {
609            0x8000: fetch();
610            0xa000: fetch_m();
611            0xe800: ecb();
612        }
613
614        format MiscPrefetch {
615            0xf800: wh64({{ EA = Rb & ~ULL(63); }},
616                         {{ xc->writeHint(EA, 64, memAccessFlags); }},
617                         mem_flags = NO_FAULT,
618                         inst_flags = [IsMemRef, IsDataPrefetch,
619                                       IsStore, MemWriteOp]);
620        }
621
622        format BasicOperate {
623            0xc000: rpcc({{
624#if FULL_SYSTEM
625        /* Rb is a fake dependency so here is a fun way to get
626         * the parser to understand that.
627         */
628                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
629
630#else
631                Ra = curTick;
632#endif
633            }}, IsUnverifiable);
634
635            // All of the barrier instructions below do nothing in
636            // their execute() methods (hence the empty code blocks).
637            // All of their functionality is hard-coded in the
638            // pipeline based on the flags IsSerializing,
639            // IsMemBarrier, and IsWriteBarrier.  In the current
640            // detailed CPU model, the execute() function only gets
641            // called at fetch, so there's no way to generate pipeline
642            // behavior at any other stage.  Once we go to an
643            // exec-in-exec CPU model we should be able to get rid of
644            // these flags and implement this behavior via the
645            // execute() methods.
646
647            // trapb is just a barrier on integer traps, where excb is
648            // a barrier on integer and FP traps.  "EXCB is thus a
649            // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
650            // them the same though.
651            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
652            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
653            0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
654            0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
655        }
656
657#if FULL_SYSTEM
658        format BasicOperate {
659            0xe000: rc({{
660                Ra = xc->readIntrFlag();
661                xc->setIntrFlag(0);
662            }}, IsNonSpeculative, IsUnverifiable);
663            0xf000: rs({{
664                Ra = xc->readIntrFlag();
665                xc->setIntrFlag(1);
666            }}, IsNonSpeculative, IsUnverifiable);
667        }
668#else
669        format FailUnimpl {
670            0xe000: rc();
671            0xf000: rs();
672        }
673#endif
674    }
675
676#if FULL_SYSTEM
677    0x00: CallPal::call_pal({{
678        if (!palValid ||
679            (palPriv
680             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
681            // invalid pal function code, or attempt to do privileged
682            // PAL call in non-kernel mode
683            fault = new UnimplementedOpcodeFault;
684        }
685        else {
686            // check to see if simulator wants to do something special
687            // on this PAL call (including maybe suppress it)
688            bool dopal = xc->simPalCheck(palFunc);
689
690            if (dopal) {
691                xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
692                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
693            }
694        }
695    }}, IsNonSpeculative);
696#else
697    0x00: decode PALFUNC {
698        format EmulatedCallPal {
699            0x00: halt ({{
700                exitSimLoop(curTick, "halt instruction encountered");
701            }}, IsNonSpeculative);
702            0x83: callsys({{
703                xc->syscall(R0);
704            }}, IsNonSpeculative);
705            // Read uniq reg into ABI return value register (r0)
706            0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
707            // Write uniq reg with value from ABI arg register (r16)
708            0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
709        }
710    }
711#endif
712
713#if FULL_SYSTEM
714    0x1b: decode PALMODE {
715        0: OpcdecFault::hw_st_quad();
716        1: decode HW_LDST_QUAD {
717            format HwLoad {
718                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
719                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
720            }
721        }
722    }
723
724    0x1f: decode PALMODE {
725        0: OpcdecFault::hw_st_cond();
726        format HwStore {
727            1: decode HW_LDST_COND {
728                0: decode HW_LDST_QUAD {
729                    0: hw_st({{ EA = (Rb + disp) & ~3; }},
730                {{ Mem.ul = Ra<31:0>; }}, L);
731                    1: hw_st({{ EA = (Rb + disp) & ~7; }},
732                {{ Mem.uq = Ra.uq; }}, Q);
733                }
734
735                1: FailUnimpl::hw_st_cond();
736            }
737        }
738    }
739
740    0x19: decode PALMODE {
741        0: OpcdecFault::hw_mfpr();
742        format HwMoveIPR {
743            1: hw_mfpr({{
744                Ra = xc->readMiscRegWithEffect(ipr_index, fault);
745            }}, IsIprAccess);
746        }
747    }
748
749    0x1d: decode PALMODE {
750        0: OpcdecFault::hw_mtpr();
751        format HwMoveIPR {
752            1: hw_mtpr({{
753                xc->setMiscRegWithEffect(ipr_index, Ra);
754                if (traceData) { traceData->setData(Ra); }
755            }}, IsIprAccess);
756        }
757    }
758
759    format BasicOperate {
760        0x1e: decode PALMODE {
761            0: OpcdecFault::hw_rei();
762            1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
763        }
764
765        // M5 special opcodes use the reserved 0x01 opcode space
766        0x01: decode M5FUNC {
767            0x00: arm({{
768                AlphaPseudo::arm(xc->tcBase());
769            }}, IsNonSpeculative);
770            0x01: quiesce({{
771                AlphaPseudo::quiesce(xc->tcBase());
772            }}, IsNonSpeculative, IsQuiesce);
773            0x02: quiesceNs({{
774                AlphaPseudo::quiesceNs(xc->tcBase(), R16);
775            }}, IsNonSpeculative, IsQuiesce);
776            0x03: quiesceCycles({{
777                AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
778            }}, IsNonSpeculative, IsQuiesce);
779            0x04: quiesceTime({{
780                R0 = AlphaPseudo::quiesceTime(xc->tcBase());
781            }}, IsNonSpeculative);
782            0x10: ivlb({{
783                AlphaPseudo::ivlb(xc->tcBase());
784            }}, No_OpClass, IsNonSpeculative);
785            0x11: ivle({{
786                AlphaPseudo::ivle(xc->tcBase());
787            }}, No_OpClass, IsNonSpeculative);
788            0x20: m5exit_old({{
789                AlphaPseudo::m5exit_old(xc->tcBase());
790            }}, No_OpClass, IsNonSpeculative);
791            0x21: m5exit({{
792                AlphaPseudo::m5exit(xc->tcBase(), R16);
793            }}, No_OpClass, IsNonSpeculative);
794            0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
795            0x40: resetstats({{
796                AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
797            }}, IsNonSpeculative);
798            0x41: dumpstats({{
799                AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
800            }}, IsNonSpeculative);
801            0x42: dumpresetstats({{
802                AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
803            }}, IsNonSpeculative);
804            0x43: m5checkpoint({{
805                AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
806            }}, IsNonSpeculative);
807            0x50: m5readfile({{
808                R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
809            }}, IsNonSpeculative);
810            0x51: m5break({{
811                AlphaPseudo::debugbreak(xc->tcBase());
812            }}, IsNonSpeculative);
813            0x52: m5switchcpu({{
814                AlphaPseudo::switchcpu(xc->tcBase());
815            }}, IsNonSpeculative);
816            0x53: m5addsymbol({{
817                AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
818            }}, IsNonSpeculative);
819            0x54: m5panic({{
820                panic("M5 panic instruction called at pc=%#x.", xc->readPC());
821            }}, IsNonSpeculative);
822
823        }
824    }
825#endif
826}
827