decoder.isa revision 2667:fe64b8353b1c
12SN/A// -*- mode:c++ -*- 29428SAndreas.Sandberg@ARM.com 39920Syasuko.eckert@amd.com// Copyright (c) 2003-2006 The Regents of The University of Michigan 48733Sgeoffrey.blake@arm.com// All rights reserved. 58733Sgeoffrey.blake@arm.com// 68733Sgeoffrey.blake@arm.com// Redistribution and use in source and binary forms, with or without 78733Sgeoffrey.blake@arm.com// modification, are permitted provided that the following conditions are 88733Sgeoffrey.blake@arm.com// met: redistributions of source code must retain the above copyright 98733Sgeoffrey.blake@arm.com// notice, this list of conditions and the following disclaimer; 108733Sgeoffrey.blake@arm.com// redistributions in binary form must reproduce the above copyright 118733Sgeoffrey.blake@arm.com// notice, this list of conditions and the following disclaimer in the 128733Sgeoffrey.blake@arm.com// documentation and/or other materials provided with the distribution; 138733Sgeoffrey.blake@arm.com// neither the name of the copyright holders nor the names of its 148733Sgeoffrey.blake@arm.com// contributors may be used to endorse or promote products derived from 152190SN/A// this software without specific prior written permission. 162SN/A// 172SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282SN/A// 292SN/A// Authors: Steve Reinhardt 302SN/A 312SN/A//////////////////////////////////////////////////////////////////// 322SN/A// 332SN/A// The actual decoder specification 342SN/A// 352SN/A 362SN/Adecode OPCODE default Unknown::unknown() { 372SN/A 382SN/A format LoadAddress { 392SN/A 0x08: lda({{ Ra = Rb + disp; }}); 402665SN/A 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 412665SN/A } 422SN/A 432SN/A format LoadOrNop { 442680Sktlim@umich.edu 0x0a: ldbu({{ Ra.uq = Mem.ub; }}); 452680Sktlim@umich.edu 0x0c: ldwu({{ Ra.uq = Mem.uw; }}); 462SN/A 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 478229Snate@binkert.org 0x23: ldt({{ Fa = Mem.df; }}); 487680Sgblack@eecs.umich.edu 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED); 497680Sgblack@eecs.umich.edu 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED); 506329Sgblack@eecs.umich.edu 0x20: MiscPrefetch::copy_load({{ EA = Ra; }}, 513453Sgblack@eecs.umich.edu {{ fault = xc->copySrcTranslate(EA); }}, 526216Snate@binkert.org inst_flags = [IsMemRef, IsLoad, IsCopy]); 536658Snate@binkert.org } 542SN/A 552190SN/A format LoadOrPrefetch { 562190SN/A 0x28: ldl({{ Ra.sl = Mem.sl; }}); 573453Sgblack@eecs.umich.edu 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT); 583453Sgblack@eecs.umich.edu // IsFloating flag on lds gets the prefetch to disassemble 599020Sgblack@eecs.umich.edu // using f31 instead of r31... funcitonally it's unnecessary 606022Sgblack@eecs.umich.edu 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }}, 613453Sgblack@eecs.umich.edu pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 622190SN/A } 638887Sgeoffrey.blake@arm.com 647680Sgblack@eecs.umich.edu format Store { 652313SN/A 0x0e: stb({{ Mem.ub = Ra<7:0>; }}); 668706Sandreas.hansson@arm.com 0x0d: stw({{ Mem.uw = Ra<15:0>; }}); 678706Sandreas.hansson@arm.com 0x2c: stl({{ Mem.ul = Ra<31:0>; }}); 688706Sandreas.hansson@arm.com 0x2d: stq({{ Mem.uq = Ra.uq; }}); 692190SN/A 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 702190SN/A 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 713548Sgblack@eecs.umich.edu 0x27: stt({{ Mem.df = Fa; }}); 723548Sgblack@eecs.umich.edu 0x24: MiscPrefetch::copy_store({{ EA = Rb; }}, 733548Sgblack@eecs.umich.edu {{ fault = xc->copy(EA); }}, 748902Sandreas.hansson@arm.com inst_flags = [IsMemRef, IsStore, IsCopy]); 758902Sandreas.hansson@arm.com } 762SN/A 772680Sktlim@umich.edu format StoreCond { 782680Sktlim@umich.edu 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }}, 792680Sktlim@umich.edu {{ 802680Sktlim@umich.edu uint64_t tmp = write_result; 812680Sktlim@umich.edu // see stq_c 822680Sktlim@umich.edu Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 832680Sktlim@umich.edu }}, mem_flags = LOCKED); 842680Sktlim@umich.edu 0x2f: stq_c({{ Mem.uq = Ra; }}, 852680Sktlim@umich.edu {{ 862680Sktlim@umich.edu uint64_t tmp = write_result; 872680Sktlim@umich.edu // If the write operation returns 0 or 1, then 882682Sktlim@umich.edu // this was a conventional store conditional, 892680Sktlim@umich.edu // and the value indicates the success/failure 902680Sktlim@umich.edu // of the operation. If another value is 912680Sktlim@umich.edu // returned, then this was a Turbolaser 922680Sktlim@umich.edu // mailbox access, and we don't update the 932680Sktlim@umich.edu // result register at all. 942SN/A Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 952107SN/A }}, mem_flags = LOCKED); 962107SN/A } 972190SN/A 982455SN/A format IntegerOperate { 992455SN/A 1009920Syasuko.eckert@amd.com 0x10: decode INTFUNC { // integer arithmetic operations 1012159SN/A 1022SN/A 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 1036029Ssteve.reinhardt@amd.com 0x40: addlv({{ 104246SN/A uint32_t tmp = Ra.sl + Rb_or_imm.sl; 105246SN/A // signed overflow occurs when operands have same sign 106246SN/A // and sign of result does not match. 107246SN/A if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 108246SN/A fault = new IntegerOverflowFault; 109246SN/A Rc.sl = tmp; 110246SN/A }}); 1112190SN/A 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); 112246SN/A 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }}); 113246SN/A 114246SN/A 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 115246SN/A 0x60: addqv({{ 116246SN/A uint64_t tmp = Ra + Rb_or_imm; 117246SN/A // signed overflow occurs when operands have same sign 118246SN/A // and sign of result does not match. 1192SN/A if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1202680Sktlim@umich.edu fault = new IntegerOverflowFault; 1212423SN/A Rc = tmp; 1222190SN/A }}); 123180SN/A 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 12410110Sandreas.hansson@arm.com 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 1252190SN/A 12610190Sakash.bagdia@arm.com 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }}); 12710190Sakash.bagdia@arm.com 0x49: sublv({{ 12810110Sandreas.hansson@arm.com uint32_t tmp = Ra.sl - Rb_or_imm.sl; 1295715Shsul@eecs.umich.edu // signed overflow detection is same as for add, 1305715Shsul@eecs.umich.edu // except we need to look at the *complemented* 1315714Shsul@eecs.umich.edu // sign bit of the subtrahend (Rb), i.e., if the initial 13210110Sandreas.hansson@arm.com // signs are the *same* then no overflow can occur 1335714Shsul@eecs.umich.edu if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1345714Shsul@eecs.umich.edu fault = new IntegerOverflowFault; 1355714Shsul@eecs.umich.edu Rc.sl = tmp; 1366022Sgblack@eecs.umich.edu }}); 1372190SN/A 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); 1386022Sgblack@eecs.umich.edu 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }}); 1392521SN/A 1408887Sgeoffrey.blake@arm.com 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 1418733Sgeoffrey.blake@arm.com 0x69: subqv({{ 1429020Sgblack@eecs.umich.edu uint64_t tmp = Ra - Rb_or_imm; 1438541Sgblack@eecs.umich.edu // signed overflow detection is same as for add, 1444997Sgblack@eecs.umich.edu // except we need to look at the *complemented* 1454997Sgblack@eecs.umich.edu // sign bit of the subtrahend (Rb), i.e., if the initial 1463548Sgblack@eecs.umich.edu // signs are the *same* then no overflow can occur 1472654SN/A if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1488852Sandreas.hansson@arm.com fault = new IntegerOverflowFault; 1492521SN/A Rc = tmp; 1508852Sandreas.hansson@arm.com }}); 1513673Srdreslin@umich.edu 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 1528706Sandreas.hansson@arm.com 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 1538706Sandreas.hansson@arm.com 1548706Sandreas.hansson@arm.com 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 1558706Sandreas.hansson@arm.com 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }}); 1568706Sandreas.hansson@arm.com 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }}); 1578706Sandreas.hansson@arm.com 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }}); 1588706Sandreas.hansson@arm.com 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }}); 1598799Sgblack@eecs.umich.edu 1608852Sandreas.hansson@arm.com 0x0f: cmpbge({{ 1612518SN/A int hi = 7; 1622190SN/A int lo = 0; 1632190SN/A uint64_t tmp = 0; 1642190SN/A for (int i = 0; i < 8; ++i) { 1652159SN/A tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i; 1662235SN/A hi += 8; 1672103SN/A lo += 8; 168393SN/A } 169393SN/A Rc = tmp; 1709180Sandreas.hansson@arm.com }}); 171393SN/A } 172393SN/A 1739180Sandreas.hansson@arm.com 0x11: decode INTFUNC { // integer logical operations 174393SN/A 175393SN/A 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 1769180Sandreas.hansson@arm.com 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 1772159SN/A 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 1782190SN/A 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 1792159SN/A 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 1802680Sktlim@umich.edu 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 1812159SN/A 1822190SN/A // conditional moves 1832159SN/A 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 1842313SN/A 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 1852235SN/A 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 1862235SN/A 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 1872235SN/A 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }}); 1882235SN/A 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }}); 1892235SN/A 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }}); 1902254SN/A 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }}); 1912254SN/A 1922254SN/A // For AMASK, RA must be R31. 1932235SN/A 0x61: decode RA { 1942680Sktlim@umich.edu 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 1952159SN/A } 1962190SN/A 1972159SN/A // For IMPLVER, RA must be R31 and the B operand 1982159SN/A // must be the immediate value 1. 1992159SN/A 0x6c: decode RA { 2002159SN/A 31: decode IMM { 2012190SN/A 1: decode INTIMM { 2022159SN/A // return EV5 for FULL_SYSTEM and EV6 otherwise 2032455SN/A 1: implver({{ 2042159SN/A#if FULL_SYSTEM 2052455SN/A Rc = 1; 2062159SN/A#else 2079920Syasuko.eckert@amd.com Rc = 2; 2089920Syasuko.eckert@amd.com#endif 2092190SN/A }}); 2102159SN/A } 2112455SN/A } 2122159SN/A } 2132455SN/A 2142455SN/A#if FULL_SYSTEM 2159920Syasuko.eckert@amd.com // The mysterious 11.25... 2169920Syasuko.eckert@amd.com 0x25: WarnUnimpl::eleven25(); 2177720Sgblack@eecs.umich.edu#endif 2182159SN/A } 2197720Sgblack@eecs.umich.edu 2202159SN/A 0x12: decode INTFUNC { 2218733Sgeoffrey.blake@arm.com 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 2228733Sgeoffrey.blake@arm.com 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }}); 2237720Sgblack@eecs.umich.edu 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }}); 2242159SN/A 2257720Sgblack@eecs.umich.edu 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 2262159SN/A 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 2277720Sgblack@eecs.umich.edu 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 2285260Sksewell@umich.edu 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 2294172Ssaidi@eecs.umich.edu 2304172Ssaidi@eecs.umich.edu 0x52: mskwh({{ 2312190SN/A int bv = Rb_or_imm<2:0>; 2322159SN/A Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 2334172Ssaidi@eecs.umich.edu }}); 2342190SN/A 0x62: msklh({{ 2353468Sgblack@eecs.umich.edu int bv = Rb_or_imm<2:0>; 2362190SN/A Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 2376313Sgblack@eecs.umich.edu }}); 2386313Sgblack@eecs.umich.edu 0x72: mskqh({{ 2399920Syasuko.eckert@amd.com int bv = Rb_or_imm<2:0>; 24010033SAli.Saidi@ARM.com Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 2416313Sgblack@eecs.umich.edu }}); 2426221Snate@binkert.org 2436221Snate@binkert.org 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 2446221Snate@binkert.org 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 2456221Snate@binkert.org 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 2466221Snate@binkert.org 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }}); 2474661Sksewell@umich.edu 2486221Snate@binkert.org 0x5a: extwh({{ 2496221Snate@binkert.org Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 2506221Snate@binkert.org 0x6a: extlh({{ 2516221Snate@binkert.org Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 2524661Sksewell@umich.edu 0x7a: extqh({{ 2532235SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 2542235SN/A 2552190SN/A 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 2562190SN/A 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 2572190SN/A 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 2582159SN/A 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 2592235SN/A 2602190SN/A 0x57: inswh({{ 2612190SN/A int bv = Rb_or_imm<2:0>; 2622235SN/A Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0; 2632190SN/A }}); 2642834Sksewell@umich.edu 0x67: inslh({{ 2654111Sgblack@eecs.umich.edu int bv = Rb_or_imm<2:0>; 2664111Sgblack@eecs.umich.edu Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0; 2672834Sksewell@umich.edu }}); 2682834Sksewell@umich.edu 0x77: insqh({{ 2692834Sksewell@umich.edu int bv = Rb_or_imm<2:0>; 2702834Sksewell@umich.edu Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0; 2712525SN/A }}); 2725217Ssaidi@eecs.umich.edu 2735217Ssaidi@eecs.umich.edu 0x30: zap({{ 2749426SAndreas.Sandberg@ARM.com uint64_t zapmask = 0; 2759426SAndreas.Sandberg@ARM.com for (int i = 0; i < 8; ++i) { 2769426SAndreas.Sandberg@ARM.com if (Rb_or_imm<i:>) 2779426SAndreas.Sandberg@ARM.com zapmask |= (mask(8) << (i * 8)); 2789426SAndreas.Sandberg@ARM.com } 2799426SAndreas.Sandberg@ARM.com Rc = Ra & ~zapmask; 2809426SAndreas.Sandberg@ARM.com }}); 2819426SAndreas.Sandberg@ARM.com 0x31: zapnot({{ 2829426SAndreas.Sandberg@ARM.com uint64_t zapmask = 0; 2839426SAndreas.Sandberg@ARM.com for (int i = 0; i < 8; ++i) { 2849426SAndreas.Sandberg@ARM.com if (!Rb_or_imm<i:>) 2859426SAndreas.Sandberg@ARM.com zapmask |= (mask(8) << (i * 8)); 2869426SAndreas.Sandberg@ARM.com } 2879426SAndreas.Sandberg@ARM.com Rc = Ra & ~zapmask; 2889426SAndreas.Sandberg@ARM.com }}); 2899426SAndreas.Sandberg@ARM.com } 2909426SAndreas.Sandberg@ARM.com 2919426SAndreas.Sandberg@ARM.com 0x13: decode INTFUNC { // integer multiplies 2929426SAndreas.Sandberg@ARM.com 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 2939426SAndreas.Sandberg@ARM.com 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 2949426SAndreas.Sandberg@ARM.com 0x30: umulh({{ 2959426SAndreas.Sandberg@ARM.com uint64_t hi, lo; 2969920Syasuko.eckert@amd.com mul128(Ra, Rb_or_imm, hi, lo); 2979920Syasuko.eckert@amd.com Rc = hi; 2989426SAndreas.Sandberg@ARM.com }}, IntMultOp); 2999426SAndreas.Sandberg@ARM.com 0x40: mullv({{ 3002159SN/A // 32-bit multiply with trap on overflow 3012159SN/A int64_t Rax = Ra.sl; // sign extended version of Ra.sl 3022682Sktlim@umich.edu int64_t Rbx = Rb_or_imm.sl; 3032682Sktlim@umich.edu int64_t tmp = Rax * Rbx; 3042682Sktlim@umich.edu // To avoid overflow, all the upper 32 bits must match 3052682Sktlim@umich.edu // the sign bit of the lower 32. We code this as 3062682Sktlim@umich.edu // checking the upper 33 bits for all 0s or all 1s. 3072682Sktlim@umich.edu uint64_t sign_bits = tmp<63:31>; 3082682Sktlim@umich.edu if (sign_bits != 0 && sign_bits != mask(33)) 3092682Sktlim@umich.edu fault = new IntegerOverflowFault; 3102682Sktlim@umich.edu Rc.sl = tmp<31:0>; 3112682Sktlim@umich.edu }}, IntMultOp); 3122680Sktlim@umich.edu 0x60: mulqv({{ 3132680Sktlim@umich.edu // 64-bit multiply with trap on overflow 3142190SN/A uint64_t hi, lo; 3152190SN/A mul128(Ra, Rb_or_imm, hi, lo); 3162680Sktlim@umich.edu // all the upper 64 bits must match the sign bit of 3172680Sktlim@umich.edu // the lower 64 3182159SN/A if (!((hi == 0 && lo<63:> == 0) || 3192190SN/A (hi == mask(64) && lo<63:> == 1))) 3202680Sktlim@umich.edu fault = new IntegerOverflowFault; 3212SN/A Rc = lo; 3222SN/A }}, IntMultOp); 3232SN/A } 3242680Sktlim@umich.edu 3252SN/A 0x1c: decode INTFUNC { 32610110Sandreas.hansson@arm.com 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 3272SN/A 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } 32810190Sakash.bagdia@arm.com 0x32: ctlz({{ 32910190Sakash.bagdia@arm.com uint64_t count = 0; 33010110Sandreas.hansson@arm.com uint64_t temp = Rb; 3315715Shsul@eecs.umich.edu if (temp<63:32>) temp >>= 32; else count += 32; 33210110Sandreas.hansson@arm.com if (temp<31:16>) temp >>= 16; else count += 16; 3335714Shsul@eecs.umich.edu if (temp<15:8>) temp >>= 8; else count += 8; 33410110Sandreas.hansson@arm.com if (temp<7:4>) temp >>= 4; else count += 4; 3355714Shsul@eecs.umich.edu if (temp<3:2>) temp >>= 2; else count += 2; 3365714Shsul@eecs.umich.edu if (temp<1:1>) temp >>= 1; else count += 1; 3375714Shsul@eecs.umich.edu if ((temp<0:0>) != 0x1) count += 1; 3386022Sgblack@eecs.umich.edu Rc = count; 3391917SN/A }}, IntAluOp); 3406022Sgblack@eecs.umich.edu 3412521SN/A 0x33: cttz({{ 3428887Sgeoffrey.blake@arm.com uint64_t count = 0; 3438733Sgeoffrey.blake@arm.com uint64_t temp = Rb; 3449020Sgblack@eecs.umich.edu if (!(temp<31:0>)) { temp >>= 32; count += 32; } 3458541Sgblack@eecs.umich.edu if (!(temp<15:0>)) { temp >>= 16; count += 16; } 3464997Sgblack@eecs.umich.edu if (!(temp<7:0>)) { temp >>= 8; count += 8; } 3474997Sgblack@eecs.umich.edu if (!(temp<3:0>)) { temp >>= 4; count += 4; } 3483548Sgblack@eecs.umich.edu if (!(temp<1:0>)) { temp >>= 2; count += 2; } 3493548Sgblack@eecs.umich.edu if (!(temp<0:0> & ULL(0x1))) count += 1; 3502654SN/A Rc = count; 3518852Sandreas.hansson@arm.com }}, IntAluOp); 3522521SN/A 3538852Sandreas.hansson@arm.com format FailUnimpl { 3543673Srdreslin@umich.edu 0x30: ctpop(); 3558706Sandreas.hansson@arm.com 0x31: perr(); 3568799Sgblack@eecs.umich.edu 0x34: unpkbw(); 3578852Sandreas.hansson@arm.com 0x35: unpkbl(); 3582518SN/A 0x36: pkwb(); 3592680Sktlim@umich.edu 0x37: pklb(); 3602SN/A 0x38: minsb8(); 3612680Sktlim@umich.edu 0x39: minsw4(); 362595SN/A 0x3a: minub8(); 3632680Sktlim@umich.edu 0x3b: minuw4(); 3642SN/A 0x3c: maxub8(); 3652190SN/A 0x3d: maxuw4(); 3662190SN/A 0x3e: maxsb8(); 3679180Sandreas.hansson@arm.com 0x3f: maxsw4(); 3689180Sandreas.hansson@arm.com } 3692SN/A 3702190SN/A format BasicOperateWithNopCheck { 3719180Sandreas.hansson@arm.com 0x70: decode RB { 3722SN/A 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp); 3732190SN/A } 3749180Sandreas.hansson@arm.com 0x78: decode RB { 375217SN/A 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }}, 3762680Sktlim@umich.edu FloatCvtOp); 3772190SN/A } 3782680Sktlim@umich.edu } 3792680Sktlim@umich.edu } 3802190SN/A } 3812680Sktlim@umich.edu 3822190SN/A // Conditional branches. 3832680Sktlim@umich.edu format CondBranch { 3842235SN/A 0x39: beq({{ cond = (Ra == 0); }}); 3852680Sktlim@umich.edu 0x3d: bne({{ cond = (Ra != 0); }}); 3862680Sktlim@umich.edu 0x3e: bge({{ cond = (Ra.sq >= 0); }}); 3872254SN/A 0x3f: bgt({{ cond = (Ra.sq > 0); }}); 3882680Sktlim@umich.edu 0x3b: ble({{ cond = (Ra.sq <= 0); }}); 3892680Sktlim@umich.edu 0x3a: blt({{ cond = (Ra.sq < 0); }}); 3902SN/A 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 3912190SN/A 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 3922680Sktlim@umich.edu 3932SN/A 0x31: fbeq({{ cond = (Fa == 0); }}); 3942680Sktlim@umich.edu 0x35: fbne({{ cond = (Fa != 0); }}); 395716SN/A 0x36: fbge({{ cond = (Fa >= 0); }}); 3962SN/A 0x37: fbgt({{ cond = (Fa > 0); }}); 3972SN/A 0x33: fble({{ cond = (Fa <= 0); }}); 3982SN/A 0x32: fblt({{ cond = (Fa < 0); }}); 3992SN/A } 4002680Sktlim@umich.edu 4012SN/A // unconditional branches 4022455SN/A format UncondBranch { 4032680Sktlim@umich.edu 0x30: br(); 4042SN/A 0x34: bsr(IsCall); 4052455SN/A } 4062680Sktlim@umich.edu 4072SN/A // indirect branches 4089920Syasuko.eckert@amd.com 0x1a: decode JMPFUNC { 4099920Syasuko.eckert@amd.com format Jump { 4109920Syasuko.eckert@amd.com 0: jmp(); 4112SN/A 1: jsr(IsCall); 4122680Sktlim@umich.edu 2: ret(IsReturn); 4132SN/A 3: jsr_coroutine(IsCall, IsReturn); 4142455SN/A } 4152680Sktlim@umich.edu } 4162SN/A 4172455SN/A // Square root and integer-to-FP moves 4182680Sktlim@umich.edu 0x14: decode FP_SHORTFUNC { 4192SN/A // Integer to FP register moves must have RB == 31 4209920Syasuko.eckert@amd.com 0x4: decode RB { 4219920Syasuko.eckert@amd.com 31: decode FP_FULLFUNC { 4229920Syasuko.eckert@amd.com format BasicOperateWithNopCheck { 4237720Sgblack@eecs.umich.edu 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 4242SN/A 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 4257720Sgblack@eecs.umich.edu 0x014: FailUnimpl::itoff(); // VAX-format conversion 4262206SN/A } 4278733Sgeoffrey.blake@arm.com } 4288733Sgeoffrey.blake@arm.com } 4297720Sgblack@eecs.umich.edu 4307720Sgblack@eecs.umich.edu // Square root instructions must have FA == 31 4317720Sgblack@eecs.umich.edu 0xb: decode FA { 4325260Sksewell@umich.edu 31: decode FP_TYPEFUNC { 4337597Sminkyu.jeong@arm.com format FloatingPointOperate { 4347597Sminkyu.jeong@arm.com#if SS_COMPATIBLE_FP 4357597Sminkyu.jeong@arm.com 0x0b: sqrts({{ 4367597Sminkyu.jeong@arm.com if (Fb < 0.0) 4377597Sminkyu.jeong@arm.com fault = new ArithmeticFault; 4384172Ssaidi@eecs.umich.edu Fc = sqrt(Fb); 4394172Ssaidi@eecs.umich.edu }}, FloatSqrtOp); 4404172Ssaidi@eecs.umich.edu#else 4412159SN/A 0x0b: sqrts({{ 4422680Sktlim@umich.edu if (Fb.sf < 0.0) 4432SN/A fault = new ArithmeticFault; 4444172Ssaidi@eecs.umich.edu Fc.sf = sqrt(Fb.sf); 4454172Ssaidi@eecs.umich.edu }}, FloatSqrtOp); 4462SN/A#endif 4473468Sgblack@eecs.umich.edu 0x2b: sqrtt({{ 4482680Sktlim@umich.edu if (Fb < 0.0) 4492SN/A fault = new ArithmeticFault; 4506313Sgblack@eecs.umich.edu Fc = sqrt(Fb); 4516313Sgblack@eecs.umich.edu }}, FloatSqrtOp); 4526313Sgblack@eecs.umich.edu } 4536313Sgblack@eecs.umich.edu } 4546313Sgblack@eecs.umich.edu } 4556313Sgblack@eecs.umich.edu 4569920Syasuko.eckert@amd.com // VAX-format sqrtf and sqrtg are not implemented 4579920Syasuko.eckert@amd.com 0xa: FailUnimpl::sqrtfg(); 4589920Syasuko.eckert@amd.com } 45910033SAli.Saidi@ARM.com 46010033SAli.Saidi@ARM.com // IEEE floating point 46110033SAli.Saidi@ARM.com 0x16: decode FP_SHORTFUNC_TOP2 { 4622190SN/A // The top two bits of the short function code break this 4632680Sktlim@umich.edu // space into four groups: binary ops, compares, reserved, and 4642190SN/A // conversions. See Table 4-12 of AHB. There are different 4652190SN/A // special cases in these different groups, so we decode on 4662680Sktlim@umich.edu // these top two bits first just to select a decode strategy. 4672SN/A // Most of these instructions may have various trapping and 4682190SN/A // rounding mode flags set; these are decoded in the 4692680Sktlim@umich.edu // FloatingPointDecode template used by the 4702190SN/A // FloatingPointOperate format. 4714111Sgblack@eecs.umich.edu 4724111Sgblack@eecs.umich.edu // add/sub/mul/div: just decode on the short function code 4734111Sgblack@eecs.umich.edu // and source type. All valid trapping and rounding modes apply. 4742680Sktlim@umich.edu 0: decode FP_TRAPMODE { 4759426SAndreas.Sandberg@ARM.com // check for valid trapping modes here 4769426SAndreas.Sandberg@ARM.com 0,1,5,7: decode FP_TYPEFUNC { 4779426SAndreas.Sandberg@ARM.com format FloatingPointOperate { 4789426SAndreas.Sandberg@ARM.com#if SS_COMPATIBLE_FP 4799426SAndreas.Sandberg@ARM.com 0x00: adds({{ Fc = Fa + Fb; }}); 4809426SAndreas.Sandberg@ARM.com 0x01: subs({{ Fc = Fa - Fb; }}); 4819426SAndreas.Sandberg@ARM.com 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 4829426SAndreas.Sandberg@ARM.com 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 4839426SAndreas.Sandberg@ARM.com#else 4849426SAndreas.Sandberg@ARM.com 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }}); 4859426SAndreas.Sandberg@ARM.com 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }}); 4869426SAndreas.Sandberg@ARM.com 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); 4879426SAndreas.Sandberg@ARM.com 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp); 4889426SAndreas.Sandberg@ARM.com#endif 4899426SAndreas.Sandberg@ARM.com 4909426SAndreas.Sandberg@ARM.com 0x20: addt({{ Fc = Fa + Fb; }}); 4919426SAndreas.Sandberg@ARM.com 0x21: subt({{ Fc = Fa - Fb; }}); 4929426SAndreas.Sandberg@ARM.com 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 4939920Syasuko.eckert@amd.com 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 4949920Syasuko.eckert@amd.com } 4959920Syasuko.eckert@amd.com } 4969920Syasuko.eckert@amd.com } 4979920Syasuko.eckert@amd.com 4989920Syasuko.eckert@amd.com // Floating-point compare instructions must have the default 4992SN/A // rounding mode, and may use the default trapping mode or 5002SN/A // /SU. Both trapping modes are treated the same by M5; the 5019428SAndreas.Sandberg@ARM.com // only difference on the real hardware (as far a I can tell) 5029428SAndreas.Sandberg@ARM.com // is that without /SU you'd get an imprecise trap if you 5039428SAndreas.Sandberg@ARM.com // tried to compare a NaN with something else (instead of an 5049428SAndreas.Sandberg@ARM.com // "unordered" result). 5059428SAndreas.Sandberg@ARM.com 1: decode FP_FULLFUNC { 5069428SAndreas.Sandberg@ARM.com format BasicOperateWithNopCheck { 5079428SAndreas.Sandberg@ARM.com 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 5089428SAndreas.Sandberg@ARM.com FloatCmpOp); 5099428SAndreas.Sandberg@ARM.com 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 5109428SAndreas.Sandberg@ARM.com FloatCmpOp); 5119428SAndreas.Sandberg@ARM.com 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 5129428SAndreas.Sandberg@ARM.com FloatCmpOp); 5139428SAndreas.Sandberg@ARM.com 0x0a4, 0x5a4: cmptun({{ // unordered 5149428SAndreas.Sandberg@ARM.com Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 5159428SAndreas.Sandberg@ARM.com }}, FloatCmpOp); 5169441SAndreas.Sandberg@ARM.com } 5179441SAndreas.Sandberg@ARM.com } 5189441SAndreas.Sandberg@ARM.com 5199441SAndreas.Sandberg@ARM.com // The FP-to-integer and integer-to-FP conversion insts 5209441SAndreas.Sandberg@ARM.com // require that FA be 31. 5219441SAndreas.Sandberg@ARM.com 3: decode FA { 5229441SAndreas.Sandberg@ARM.com 31: decode FP_TYPEFUNC { 5239441SAndreas.Sandberg@ARM.com format FloatingPointOperate { 5249441SAndreas.Sandberg@ARM.com 0x2f: decode FP_ROUNDMODE { 5259441SAndreas.Sandberg@ARM.com format FPFixedRounding { 5269441SAndreas.Sandberg@ARM.com // "chopped" i.e. round toward zero 5279441SAndreas.Sandberg@ARM.com 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }}, 5289441SAndreas.Sandberg@ARM.com Chopped); 5292190SN/A // round to minus infinity 530 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }}, 531 MinusInfinity); 532 } 533 default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }}); 534 } 535 536 // The cvtts opcode is overloaded to be cvtst if the trap 537 // mode is 2 or 6 (which are not valid otherwise) 538 0x2c: decode FP_FULLFUNC { 539 format BasicOperateWithNopCheck { 540 // trap on denorm version "cvtst/s" is 541 // simulated same as cvtst 542 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }}); 543 } 544 default: cvtts({{ Fc.sf = Fb; }}); 545 } 546 547 // The trapping mode for integer-to-FP conversions 548 // must be /SUI or nothing; /U and /SU are not 549 // allowed. The full set of rounding modes are 550 // supported though. 551 0x3c: decode FP_TRAPMODE { 552 0,7: cvtqs({{ Fc.sf = Fb.sq; }}); 553 } 554 0x3e: decode FP_TRAPMODE { 555 0,7: cvtqt({{ Fc = Fb.sq; }}); 556 } 557 } 558 } 559 } 560 } 561 562 // misc FP operate 563 0x17: decode FP_FULLFUNC { 564 format BasicOperateWithNopCheck { 565 0x010: cvtlq({{ 566 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>; 567 }}); 568 0x030: cvtql({{ 569 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 570 }}); 571 572 // We treat the precise & imprecise trapping versions of 573 // cvtql identically. 574 0x130, 0x530: cvtqlv({{ 575 // To avoid overflow, all the upper 32 bits must match 576 // the sign bit of the lower 32. We code this as 577 // checking the upper 33 bits for all 0s or all 1s. 578 uint64_t sign_bits = Fb.uq<63:31>; 579 if (sign_bits != 0 && sign_bits != mask(33)) 580 fault = new IntegerOverflowFault; 581 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 582 }}); 583 584 0x020: cpys({{ // copy sign 585 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>; 586 }}); 587 0x021: cpysn({{ // copy sign negated 588 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>; 589 }}); 590 0x022: cpyse({{ // copy sign and exponent 591 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>; 592 }}); 593 594 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 595 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 596 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 597 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 598 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 599 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 600 601 0x024: mt_fpcr({{ FPCR = Fa.uq; }}); 602 0x025: mf_fpcr({{ Fa.uq = FPCR; }}); 603 } 604 } 605 606 // miscellaneous mem-format ops 607 0x18: decode MEMFUNC { 608 format WarnUnimpl { 609 0x8000: fetch(); 610 0xa000: fetch_m(); 611 0xe800: ecb(); 612 } 613 614 format MiscPrefetch { 615 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 616 {{ xc->writeHint(EA, 64, memAccessFlags); }}, 617 mem_flags = NO_FAULT, 618 inst_flags = [IsMemRef, IsDataPrefetch, 619 IsStore, MemWriteOp]); 620 } 621 622 format BasicOperate { 623 0xc000: rpcc({{ 624#if FULL_SYSTEM 625 /* Rb is a fake dependency so here is a fun way to get 626 * the parser to understand that. 627 */ 628 Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0); 629 630#else 631 Ra = curTick; 632#endif 633 }}); 634 635 // All of the barrier instructions below do nothing in 636 // their execute() methods (hence the empty code blocks). 637 // All of their functionality is hard-coded in the 638 // pipeline based on the flags IsSerializing, 639 // IsMemBarrier, and IsWriteBarrier. In the current 640 // detailed CPU model, the execute() function only gets 641 // called at fetch, so there's no way to generate pipeline 642 // behavior at any other stage. Once we go to an 643 // exec-in-exec CPU model we should be able to get rid of 644 // these flags and implement this behavior via the 645 // execute() methods. 646 647 // trapb is just a barrier on integer traps, where excb is 648 // a barrier on integer and FP traps. "EXCB is thus a 649 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 650 // them the same though. 651 0x0000: trapb({{ }}, IsSerializing, No_OpClass); 652 0x0400: excb({{ }}, IsSerializing, No_OpClass); 653 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 654 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 655 } 656 657#if FULL_SYSTEM 658 format BasicOperate { 659 0xe000: rc({{ 660 Ra = xc->readIntrFlag(); 661 xc->setIntrFlag(0); 662 }}, IsNonSpeculative); 663 0xf000: rs({{ 664 Ra = xc->readIntrFlag(); 665 xc->setIntrFlag(1); 666 }}, IsNonSpeculative); 667 } 668#else 669 format FailUnimpl { 670 0xe000: rc(); 671 0xf000: rs(); 672 } 673#endif 674 } 675 676#if FULL_SYSTEM 677 0x00: CallPal::call_pal({{ 678 if (!palValid || 679 (palPriv 680 && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { 681 // invalid pal function code, or attempt to do privileged 682 // PAL call in non-kernel mode 683 fault = new UnimplementedOpcodeFault; 684 } 685 else { 686 // check to see if simulator wants to do something special 687 // on this PAL call (including maybe suppress it) 688 bool dopal = xc->simPalCheck(palFunc); 689 690 if (dopal) { 691 xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC); 692 NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset; 693 } 694 } 695 }}, IsNonSpeculative); 696#else 697 0x00: decode PALFUNC { 698 format EmulatedCallPal { 699 0x00: halt ({{ 700 exitSimLoop(curTick, "halt instruction encountered"); 701 }}, IsNonSpeculative); 702 0x83: callsys({{ 703 xc->syscall(R0); 704 }}, IsNonSpeculative); 705 // Read uniq reg into ABI return value register (r0) 706 0x9e: rduniq({{ R0 = Runiq; }}); 707 // Write uniq reg with value from ABI arg register (r16) 708 0x9f: wruniq({{ Runiq = R16; }}); 709 } 710 } 711#endif 712 713#if FULL_SYSTEM 714 0x1b: decode PALMODE { 715 0: OpcdecFault::hw_st_quad(); 716 1: decode HW_LDST_QUAD { 717 format HwLoad { 718 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L); 719 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q); 720 } 721 } 722 } 723 724 0x1f: decode PALMODE { 725 0: OpcdecFault::hw_st_cond(); 726 format HwStore { 727 1: decode HW_LDST_COND { 728 0: decode HW_LDST_QUAD { 729 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 730 {{ Mem.ul = Ra<31:0>; }}, L); 731 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 732 {{ Mem.uq = Ra.uq; }}, Q); 733 } 734 735 1: FailUnimpl::hw_st_cond(); 736 } 737 } 738 } 739 740 0x19: decode PALMODE { 741 0: OpcdecFault::hw_mfpr(); 742 format HwMoveIPR { 743 1: hw_mfpr({{ 744 Ra = xc->readMiscRegWithEffect(ipr_index, fault); 745 }}); 746 } 747 } 748 749 0x1d: decode PALMODE { 750 0: OpcdecFault::hw_mtpr(); 751 format HwMoveIPR { 752 1: hw_mtpr({{ 753 xc->setMiscRegWithEffect(ipr_index, Ra); 754 if (traceData) { traceData->setData(Ra); } 755 }}); 756 } 757 } 758 759 format BasicOperate { 760 0x1e: decode PALMODE { 761 0: OpcdecFault::hw_rei(); 762 1:hw_rei({{ xc->hwrei(); }}, IsSerializing); 763 } 764 765 // M5 special opcodes use the reserved 0x01 opcode space 766 0x01: decode M5FUNC { 767 0x00: arm({{ 768 AlphaPseudo::arm(xc->xcBase()); 769 }}, IsNonSpeculative); 770 0x01: quiesce({{ 771 AlphaPseudo::quiesce(xc->xcBase()); 772 }}, IsNonSpeculative); 773 0x02: quiesceNs({{ 774 AlphaPseudo::quiesceNs(xc->xcBase(), R16); 775 }}, IsNonSpeculative); 776 0x03: quiesceCycles({{ 777 AlphaPseudo::quiesceCycles(xc->xcBase(), R16); 778 }}, IsNonSpeculative); 779 0x04: quiesceTime({{ 780 R0 = AlphaPseudo::quiesceTime(xc->xcBase()); 781 }}, IsNonSpeculative); 782 0x10: ivlb({{ 783 AlphaPseudo::ivlb(xc->xcBase()); 784 }}, No_OpClass, IsNonSpeculative); 785 0x11: ivle({{ 786 AlphaPseudo::ivle(xc->xcBase()); 787 }}, No_OpClass, IsNonSpeculative); 788 0x20: m5exit_old({{ 789 AlphaPseudo::m5exit_old(xc->xcBase()); 790 }}, No_OpClass, IsNonSpeculative); 791 0x21: m5exit({{ 792 AlphaPseudo::m5exit(xc->xcBase(), R16); 793 }}, No_OpClass, IsNonSpeculative); 794 0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }}); 795 0x40: resetstats({{ 796 AlphaPseudo::resetstats(xc->xcBase(), R16, R17); 797 }}, IsNonSpeculative); 798 0x41: dumpstats({{ 799 AlphaPseudo::dumpstats(xc->xcBase(), R16, R17); 800 }}, IsNonSpeculative); 801 0x42: dumpresetstats({{ 802 AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17); 803 }}, IsNonSpeculative); 804 0x43: m5checkpoint({{ 805 AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17); 806 }}, IsNonSpeculative); 807 0x50: m5readfile({{ 808 R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18); 809 }}, IsNonSpeculative); 810 0x51: m5break({{ 811 AlphaPseudo::debugbreak(xc->xcBase()); 812 }}, IsNonSpeculative); 813 0x52: m5switchcpu({{ 814 AlphaPseudo::switchcpu(xc->xcBase()); 815 }}, IsNonSpeculative); 816 0x53: m5addsymbol({{ 817 AlphaPseudo::addsymbol(xc->xcBase(), R16, R17); 818 }}, IsNonSpeculative); 819 0x54: m5panic({{ 820 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 821 }}, IsNonSpeculative); 822 823 } 824 } 825#endif 826} 827