decoder.isa revision 2649:2fb859a457a2
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2006 The Regents of The University of Michigan
4// All rights reserved.
5//
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7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
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10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
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15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
29////////////////////////////////////////////////////////////////////
30//
31// The actual decoder specification
32//
33
34decode OPCODE default Unknown::unknown() {
35
36    format LoadAddress {
37        0x08: lda({{ Ra = Rb + disp; }});
38        0x09: ldah({{ Ra = Rb + (disp << 16); }});
39    }
40
41    format LoadOrNop {
42        0x0a: ldbu({{ Ra.uq = Mem.ub; }});
43        0x0c: ldwu({{ Ra.uq = Mem.uw; }});
44        0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
45        0x23: ldt({{ Fa = Mem.df; }});
46        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
47        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
48        0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
49                                      {{ fault = xc->copySrcTranslate(EA); }},
50                                      inst_flags = [IsMemRef, IsLoad, IsCopy]);
51    }
52
53    format LoadOrPrefetch {
54        0x28: ldl({{ Ra.sl = Mem.sl; }});
55        0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
56        // IsFloating flag on lds gets the prefetch to disassemble
57        // using f31 instead of r31... funcitonally it's unnecessary
58        0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
59                  pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
60    }
61
62    format Store {
63        0x0e: stb({{ Mem.ub = Ra<7:0>; }});
64        0x0d: stw({{ Mem.uw = Ra<15:0>; }});
65        0x2c: stl({{ Mem.ul = Ra<31:0>; }});
66        0x2d: stq({{ Mem.uq = Ra.uq; }});
67        0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
68        0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
69        0x27: stt({{ Mem.df = Fa; }});
70        0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
71                                       {{ fault = xc->copy(EA); }},
72                                       inst_flags = [IsMemRef, IsStore, IsCopy]);
73    }
74
75    format StoreCond {
76        0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
77                    {{
78                        uint64_t tmp = write_result;
79                        // see stq_c
80                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
81                    }}, mem_flags = LOCKED);
82        0x2f: stq_c({{ Mem.uq = Ra; }},
83                    {{
84                        uint64_t tmp = write_result;
85                        // If the write operation returns 0 or 1, then
86                        // this was a conventional store conditional,
87                        // and the value indicates the success/failure
88                        // of the operation.  If another value is
89                        // returned, then this was a Turbolaser
90                        // mailbox access, and we don't update the
91                        // result register at all.
92                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
93                    }}, mem_flags = LOCKED);
94    }
95
96    format IntegerOperate {
97
98        0x10: decode INTFUNC {	// integer arithmetic operations
99
100            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
101            0x40: addlv({{
102                uint32_t tmp  = Ra.sl + Rb_or_imm.sl;
103                // signed overflow occurs when operands have same sign
104                // and sign of result does not match.
105                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
106                    fault = new IntegerOverflowFault;
107                Rc.sl = tmp;
108            }});
109            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
110            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
111
112            0x20: addq({{ Rc = Ra + Rb_or_imm; }});
113            0x60: addqv({{
114                uint64_t tmp = Ra + Rb_or_imm;
115                // signed overflow occurs when operands have same sign
116                // and sign of result does not match.
117                if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
118                    fault = new IntegerOverflowFault;
119                Rc = tmp;
120            }});
121            0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
122            0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
123
124            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
125            0x49: sublv({{
126                uint32_t tmp  = Ra.sl - Rb_or_imm.sl;
127                // signed overflow detection is same as for add,
128                // except we need to look at the *complemented*
129                // sign bit of the subtrahend (Rb), i.e., if the initial
130                // signs are the *same* then no overflow can occur
131                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
132                    fault = new IntegerOverflowFault;
133                Rc.sl = tmp;
134            }});
135            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
136            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
137
138            0x29: subq({{ Rc = Ra - Rb_or_imm; }});
139            0x69: subqv({{
140                uint64_t tmp  = Ra - Rb_or_imm;
141                // signed overflow detection is same as for add,
142                // except we need to look at the *complemented*
143                // sign bit of the subtrahend (Rb), i.e., if the initial
144                // signs are the *same* then no overflow can occur
145                if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
146                    fault = new IntegerOverflowFault;
147                Rc = tmp;
148            }});
149            0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
150            0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
151
152            0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
153            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
154            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
155            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
156            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
157
158            0x0f: cmpbge({{
159                int hi = 7;
160                int lo = 0;
161                uint64_t tmp = 0;
162                for (int i = 0; i < 8; ++i) {
163                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
164                    hi += 8;
165                    lo += 8;
166                }
167                Rc = tmp;
168            }});
169        }
170
171        0x11: decode INTFUNC {	// integer logical operations
172
173            0x00: and({{ Rc = Ra & Rb_or_imm; }});
174            0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
175            0x20: bis({{ Rc = Ra | Rb_or_imm; }});
176            0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
177            0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
178            0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
179
180            // conditional moves
181            0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
182            0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
183            0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
184            0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
185            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
186            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
187            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
188            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
189
190            // For AMASK, RA must be R31.
191            0x61: decode RA {
192                31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
193            }
194
195            // For IMPLVER, RA must be R31 and the B operand
196            // must be the immediate value 1.
197            0x6c: decode RA {
198                31: decode IMM {
199                    1: decode INTIMM {
200                        // return EV5 for FULL_SYSTEM and EV6 otherwise
201                        1: implver({{
202#if FULL_SYSTEM
203                             Rc = 1;
204#else
205                             Rc = 2;
206#endif
207                        }});
208                    }
209                }
210            }
211
212#if FULL_SYSTEM
213            // The mysterious 11.25...
214            0x25: WarnUnimpl::eleven25();
215#endif
216        }
217
218        0x12: decode INTFUNC {
219            0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
220            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
221            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
222
223            0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
224            0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
225            0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
226            0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
227
228            0x52: mskwh({{
229                int bv = Rb_or_imm<2:0>;
230                Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
231            }});
232            0x62: msklh({{
233                int bv = Rb_or_imm<2:0>;
234                Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
235            }});
236            0x72: mskqh({{
237                int bv = Rb_or_imm<2:0>;
238                Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
239            }});
240
241            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
242            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
243            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
244            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
245
246            0x5a: extwh({{
247                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
248            0x6a: extlh({{
249                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
250            0x7a: extqh({{
251                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
252
253            0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
254            0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
255            0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
256            0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
257
258            0x57: inswh({{
259                int bv = Rb_or_imm<2:0>;
260                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
261            }});
262            0x67: inslh({{
263                int bv = Rb_or_imm<2:0>;
264                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
265            }});
266            0x77: insqh({{
267                int bv = Rb_or_imm<2:0>;
268                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
269            }});
270
271            0x30: zap({{
272                uint64_t zapmask = 0;
273                for (int i = 0; i < 8; ++i) {
274                    if (Rb_or_imm<i:>)
275                        zapmask |= (mask(8) << (i * 8));
276                }
277                Rc = Ra & ~zapmask;
278            }});
279            0x31: zapnot({{
280                uint64_t zapmask = 0;
281                for (int i = 0; i < 8; ++i) {
282                    if (!Rb_or_imm<i:>)
283                        zapmask |= (mask(8) << (i * 8));
284                }
285                Rc = Ra & ~zapmask;
286            }});
287        }
288
289        0x13: decode INTFUNC {	// integer multiplies
290            0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
291            0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
292            0x30: umulh({{
293                uint64_t hi, lo;
294                mul128(Ra, Rb_or_imm, hi, lo);
295                Rc = hi;
296            }}, IntMultOp);
297            0x40: mullv({{
298                // 32-bit multiply with trap on overflow
299                int64_t Rax = Ra.sl;	// sign extended version of Ra.sl
300                int64_t Rbx = Rb_or_imm.sl;
301                int64_t tmp = Rax * Rbx;
302                // To avoid overflow, all the upper 32 bits must match
303                // the sign bit of the lower 32.  We code this as
304                // checking the upper 33 bits for all 0s or all 1s.
305                uint64_t sign_bits = tmp<63:31>;
306                if (sign_bits != 0 && sign_bits != mask(33))
307                    fault = new IntegerOverflowFault;
308                Rc.sl = tmp<31:0>;
309            }}, IntMultOp);
310            0x60: mulqv({{
311                // 64-bit multiply with trap on overflow
312                uint64_t hi, lo;
313                mul128(Ra, Rb_or_imm, hi, lo);
314                // all the upper 64 bits must match the sign bit of
315                // the lower 64
316                if (!((hi == 0 && lo<63:> == 0) ||
317                      (hi == mask(64) && lo<63:> == 1)))
318                    fault = new IntegerOverflowFault;
319                Rc = lo;
320            }}, IntMultOp);
321        }
322
323        0x1c: decode INTFUNC {
324            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
325            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
326            0x32: ctlz({{
327                             uint64_t count = 0;
328                             uint64_t temp = Rb;
329                             if (temp<63:32>) temp >>= 32; else count += 32;
330                             if (temp<31:16>) temp >>= 16; else count += 16;
331                             if (temp<15:8>) temp >>= 8; else count += 8;
332                             if (temp<7:4>) temp >>= 4; else count += 4;
333                             if (temp<3:2>) temp >>= 2; else count += 2;
334                             if (temp<1:1>) temp >>= 1; else count += 1;
335                             if ((temp<0:0>) != 0x1) count += 1;
336                             Rc = count;
337                           }}, IntAluOp);
338
339            0x33: cttz({{
340                             uint64_t count = 0;
341                             uint64_t temp = Rb;
342                             if (!(temp<31:0>)) { temp >>= 32; count += 32; }
343                             if (!(temp<15:0>)) { temp >>= 16; count += 16; }
344                             if (!(temp<7:0>)) { temp >>= 8; count += 8; }
345                             if (!(temp<3:0>)) { temp >>= 4; count += 4; }
346                             if (!(temp<1:0>)) { temp >>= 2; count += 2; }
347                             if (!(temp<0:0> & ULL(0x1))) count += 1;
348                             Rc = count;
349                           }}, IntAluOp);
350
351            format FailUnimpl {
352                0x30: ctpop();
353                0x31: perr();
354                0x34: unpkbw();
355                0x35: unpkbl();
356                0x36: pkwb();
357                0x37: pklb();
358                0x38: minsb8();
359                0x39: minsw4();
360                0x3a: minub8();
361                0x3b: minuw4();
362                0x3c: maxub8();
363                0x3d: maxuw4();
364                0x3e: maxsb8();
365                0x3f: maxsw4();
366            }
367
368            format BasicOperateWithNopCheck {
369                0x70: decode RB {
370                    31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
371                }
372                0x78: decode RB {
373                    31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
374                              FloatCvtOp);
375                }
376            }
377        }
378    }
379
380    // Conditional branches.
381    format CondBranch {
382        0x39: beq({{ cond = (Ra == 0); }});
383        0x3d: bne({{ cond = (Ra != 0); }});
384        0x3e: bge({{ cond = (Ra.sq >= 0); }});
385        0x3f: bgt({{ cond = (Ra.sq >  0); }});
386        0x3b: ble({{ cond = (Ra.sq <= 0); }});
387        0x3a: blt({{ cond = (Ra.sq < 0); }});
388        0x38: blbc({{ cond = ((Ra & 1) == 0); }});
389        0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
390
391        0x31: fbeq({{ cond = (Fa == 0); }});
392        0x35: fbne({{ cond = (Fa != 0); }});
393        0x36: fbge({{ cond = (Fa >= 0); }});
394        0x37: fbgt({{ cond = (Fa >  0); }});
395        0x33: fble({{ cond = (Fa <= 0); }});
396        0x32: fblt({{ cond = (Fa < 0); }});
397    }
398
399    // unconditional branches
400    format UncondBranch {
401        0x30: br();
402        0x34: bsr(IsCall);
403    }
404
405    // indirect branches
406    0x1a: decode JMPFUNC {
407        format Jump {
408            0: jmp();
409            1: jsr(IsCall);
410            2: ret(IsReturn);
411            3: jsr_coroutine(IsCall, IsReturn);
412        }
413    }
414
415    // Square root and integer-to-FP moves
416    0x14: decode FP_SHORTFUNC {
417        // Integer to FP register moves must have RB == 31
418        0x4: decode RB {
419            31: decode FP_FULLFUNC {
420                format BasicOperateWithNopCheck {
421                    0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
422                    0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
423                    0x014: FailUnimpl::itoff();	// VAX-format conversion
424                }
425            }
426        }
427
428        // Square root instructions must have FA == 31
429        0xb: decode FA {
430            31: decode FP_TYPEFUNC {
431                format FloatingPointOperate {
432#if SS_COMPATIBLE_FP
433                    0x0b: sqrts({{
434                        if (Fb < 0.0)
435                            fault = new ArithmeticFault;
436                        Fc = sqrt(Fb);
437                    }}, FloatSqrtOp);
438#else
439                    0x0b: sqrts({{
440                        if (Fb.sf < 0.0)
441                            fault = new ArithmeticFault;
442                        Fc.sf = sqrt(Fb.sf);
443                    }}, FloatSqrtOp);
444#endif
445                    0x2b: sqrtt({{
446                        if (Fb < 0.0)
447                            fault = new ArithmeticFault;
448                        Fc = sqrt(Fb);
449                    }}, FloatSqrtOp);
450                }
451            }
452        }
453
454        // VAX-format sqrtf and sqrtg are not implemented
455        0xa: FailUnimpl::sqrtfg();
456    }
457
458    // IEEE floating point
459    0x16: decode FP_SHORTFUNC_TOP2 {
460        // The top two bits of the short function code break this
461        // space into four groups: binary ops, compares, reserved, and
462        // conversions.  See Table 4-12 of AHB.  There are different
463        // special cases in these different groups, so we decode on
464        // these top two bits first just to select a decode strategy.
465        // Most of these instructions may have various trapping and
466        // rounding mode flags set; these are decoded in the
467        // FloatingPointDecode template used by the
468        // FloatingPointOperate format.
469
470        // add/sub/mul/div: just decode on the short function code
471        // and source type.  All valid trapping and rounding modes apply.
472        0: decode FP_TRAPMODE {
473            // check for valid trapping modes here
474            0,1,5,7: decode FP_TYPEFUNC {
475                   format FloatingPointOperate {
476#if SS_COMPATIBLE_FP
477                       0x00: adds({{ Fc = Fa + Fb; }});
478                       0x01: subs({{ Fc = Fa - Fb; }});
479                       0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
480                       0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
481#else
482                       0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
483                       0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
484                       0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
485                       0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
486#endif
487
488                       0x20: addt({{ Fc = Fa + Fb; }});
489                       0x21: subt({{ Fc = Fa - Fb; }});
490                       0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
491                       0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
492                   }
493             }
494        }
495
496        // Floating-point compare instructions must have the default
497        // rounding mode, and may use the default trapping mode or
498        // /SU.  Both trapping modes are treated the same by M5; the
499        // only difference on the real hardware (as far a I can tell)
500        // is that without /SU you'd get an imprecise trap if you
501        // tried to compare a NaN with something else (instead of an
502        // "unordered" result).
503        1: decode FP_FULLFUNC {
504            format BasicOperateWithNopCheck {
505                0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
506                                     FloatCmpOp);
507                0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
508                                     FloatCmpOp);
509                0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
510                                     FloatCmpOp);
511                0x0a4, 0x5a4: cmptun({{ // unordered
512                    Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
513                }}, FloatCmpOp);
514            }
515        }
516
517        // The FP-to-integer and integer-to-FP conversion insts
518        // require that FA be 31.
519        3: decode FA {
520            31: decode FP_TYPEFUNC {
521                format FloatingPointOperate {
522                    0x2f: decode FP_ROUNDMODE {
523                        format FPFixedRounding {
524                            // "chopped" i.e. round toward zero
525                            0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
526                                     Chopped);
527                            // round to minus infinity
528                            1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
529                                     MinusInfinity);
530                        }
531                      default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
532                    }
533
534                    // The cvtts opcode is overloaded to be cvtst if the trap
535                    // mode is 2 or 6 (which are not valid otherwise)
536                    0x2c: decode FP_FULLFUNC {
537                        format BasicOperateWithNopCheck {
538                            // trap on denorm version "cvtst/s" is
539                            // simulated same as cvtst
540                            0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
541                        }
542                      default: cvtts({{ Fc.sf = Fb; }});
543                    }
544
545                    // The trapping mode for integer-to-FP conversions
546                    // must be /SUI or nothing; /U and /SU are not
547                    // allowed.  The full set of rounding modes are
548                    // supported though.
549                    0x3c: decode FP_TRAPMODE {
550                        0,7: cvtqs({{ Fc.sf = Fb.sq; }});
551                    }
552                    0x3e: decode FP_TRAPMODE {
553                        0,7: cvtqt({{ Fc    = Fb.sq; }});
554                    }
555                }
556            }
557        }
558    }
559
560    // misc FP operate
561    0x17: decode FP_FULLFUNC {
562        format BasicOperateWithNopCheck {
563            0x010: cvtlq({{
564                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
565            }});
566            0x030: cvtql({{
567                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
568            }});
569
570            // We treat the precise & imprecise trapping versions of
571            // cvtql identically.
572            0x130, 0x530: cvtqlv({{
573                // To avoid overflow, all the upper 32 bits must match
574                // the sign bit of the lower 32.  We code this as
575                // checking the upper 33 bits for all 0s or all 1s.
576                uint64_t sign_bits = Fb.uq<63:31>;
577                if (sign_bits != 0 && sign_bits != mask(33))
578                    fault = new IntegerOverflowFault;
579                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
580            }});
581
582            0x020: cpys({{  // copy sign
583                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
584            }});
585            0x021: cpysn({{ // copy sign negated
586                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
587            }});
588            0x022: cpyse({{ // copy sign and exponent
589                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
590            }});
591
592            0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
593            0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
594            0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
595            0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
596            0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
597            0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
598
599            0x024: mt_fpcr({{ FPCR = Fa.uq; }});
600            0x025: mf_fpcr({{ Fa.uq = FPCR; }});
601        }
602    }
603
604    // miscellaneous mem-format ops
605    0x18: decode MEMFUNC {
606        format WarnUnimpl {
607            0x8000: fetch();
608            0xa000: fetch_m();
609            0xe800: ecb();
610        }
611
612        format MiscPrefetch {
613            0xf800: wh64({{ EA = Rb & ~ULL(63); }},
614                         {{ xc->writeHint(EA, 64, memAccessFlags); }},
615                         mem_flags = NO_FAULT,
616                         inst_flags = [IsMemRef, IsDataPrefetch,
617                                       IsStore, MemWriteOp]);
618        }
619
620        format BasicOperate {
621            0xc000: rpcc({{
622#if FULL_SYSTEM
623        /* Rb is a fake dependency so here is a fun way to get
624         * the parser to understand that.
625         */
626                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
627
628#else
629                Ra = curTick;
630#endif
631            }});
632
633            // All of the barrier instructions below do nothing in
634            // their execute() methods (hence the empty code blocks).
635            // All of their functionality is hard-coded in the
636            // pipeline based on the flags IsSerializing,
637            // IsMemBarrier, and IsWriteBarrier.  In the current
638            // detailed CPU model, the execute() function only gets
639            // called at fetch, so there's no way to generate pipeline
640            // behavior at any other stage.  Once we go to an
641            // exec-in-exec CPU model we should be able to get rid of
642            // these flags and implement this behavior via the
643            // execute() methods.
644
645            // trapb is just a barrier on integer traps, where excb is
646            // a barrier on integer and FP traps.  "EXCB is thus a
647            // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
648            // them the same though.
649            0x0000: trapb({{ }}, IsSerializing, No_OpClass);
650            0x0400: excb({{ }}, IsSerializing, No_OpClass);
651            0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
652            0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
653        }
654
655#if FULL_SYSTEM
656        format BasicOperate {
657            0xe000: rc({{
658                Ra = xc->readIntrFlag();
659                xc->setIntrFlag(0);
660            }}, IsNonSpeculative);
661            0xf000: rs({{
662                Ra = xc->readIntrFlag();
663                xc->setIntrFlag(1);
664            }}, IsNonSpeculative);
665        }
666#else
667        format FailUnimpl {
668            0xe000: rc();
669            0xf000: rs();
670        }
671#endif
672    }
673
674#if FULL_SYSTEM
675    0x00: CallPal::call_pal({{
676        if (!palValid ||
677            (palPriv
678             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
679            // invalid pal function code, or attempt to do privileged
680            // PAL call in non-kernel mode
681            fault = new UnimplementedOpcodeFault;
682        }
683        else {
684            // check to see if simulator wants to do something special
685            // on this PAL call (including maybe suppress it)
686            bool dopal = xc->simPalCheck(palFunc);
687
688            if (dopal) {
689                xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
690                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
691            }
692        }
693    }}, IsNonSpeculative);
694#else
695    0x00: decode PALFUNC {
696        format EmulatedCallPal {
697            0x00: halt ({{
698                SimExit(curTick, "halt instruction encountered");
699            }}, IsNonSpeculative);
700            0x83: callsys({{
701                xc->syscall(R0);
702            }}, IsNonSpeculative);
703            // Read uniq reg into ABI return value register (r0)
704            0x9e: rduniq({{ R0 = Runiq; }});
705            // Write uniq reg with value from ABI arg register (r16)
706            0x9f: wruniq({{ Runiq = R16; }});
707        }
708    }
709#endif
710
711#if FULL_SYSTEM
712    0x1b: decode PALMODE {
713        0: OpcdecFault::hw_st_quad();
714        1: decode HW_LDST_QUAD {
715            format HwLoad {
716                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
717                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
718            }
719        }
720    }
721
722    0x1f: decode PALMODE {
723        0: OpcdecFault::hw_st_cond();
724        format HwStore {
725            1: decode HW_LDST_COND {
726                0: decode HW_LDST_QUAD {
727                    0: hw_st({{ EA = (Rb + disp) & ~3; }},
728                {{ Mem.ul = Ra<31:0>; }}, L);
729                    1: hw_st({{ EA = (Rb + disp) & ~7; }},
730                {{ Mem.uq = Ra.uq; }}, Q);
731                }
732
733                1: FailUnimpl::hw_st_cond();
734            }
735        }
736    }
737
738    0x19: decode PALMODE {
739        0: OpcdecFault::hw_mfpr();
740        format HwMoveIPR {
741            1: hw_mfpr({{
742                Ra = xc->readMiscRegWithEffect(ipr_index, fault);
743            }});
744        }
745    }
746
747    0x1d: decode PALMODE {
748        0: OpcdecFault::hw_mtpr();
749        format HwMoveIPR {
750            1: hw_mtpr({{
751                xc->setMiscRegWithEffect(ipr_index, Ra);
752                if (traceData) { traceData->setData(Ra); }
753            }});
754        }
755    }
756
757    format BasicOperate {
758        0x1e: decode PALMODE {
759            0: OpcdecFault::hw_rei();
760            1:hw_rei({{ xc->hwrei(); }}, IsSerializing);
761        }
762
763        // M5 special opcodes use the reserved 0x01 opcode space
764        0x01: decode M5FUNC {
765            0x00: arm({{
766                AlphaPseudo::arm(xc->xcBase());
767            }}, IsNonSpeculative);
768            0x01: quiesce({{
769                AlphaPseudo::quiesce(xc->xcBase());
770            }}, IsNonSpeculative);
771            0x02: quiesceNs({{
772                AlphaPseudo::quiesceNs(xc->xcBase(), R16);
773            }}, IsNonSpeculative);
774            0x03: quiesceCycles({{
775                AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
776            }}, IsNonSpeculative);
777            0x04: quiesceTime({{
778                R0 = AlphaPseudo::quiesceTime(xc->xcBase());
779            }}, IsNonSpeculative);
780            0x10: ivlb({{
781                AlphaPseudo::ivlb(xc->xcBase());
782            }}, No_OpClass, IsNonSpeculative);
783            0x11: ivle({{
784                AlphaPseudo::ivle(xc->xcBase());
785            }}, No_OpClass, IsNonSpeculative);
786            0x20: m5exit_old({{
787                AlphaPseudo::m5exit_old(xc->xcBase());
788            }}, No_OpClass, IsNonSpeculative);
789            0x21: m5exit({{
790                AlphaPseudo::m5exit(xc->xcBase(), R16);
791            }}, No_OpClass, IsNonSpeculative);
792            0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }});
793            0x40: resetstats({{
794                AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
795            }}, IsNonSpeculative);
796            0x41: dumpstats({{
797                AlphaPseudo::dumpstats(xc->xcBase(), R16, R17);
798            }}, IsNonSpeculative);
799            0x42: dumpresetstats({{
800                AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17);
801            }}, IsNonSpeculative);
802            0x43: m5checkpoint({{
803                AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17);
804            }}, IsNonSpeculative);
805            0x50: m5readfile({{
806                R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18);
807            }}, IsNonSpeculative);
808            0x51: m5break({{
809                AlphaPseudo::debugbreak(xc->xcBase());
810            }}, IsNonSpeculative);
811            0x52: m5switchcpu({{
812                AlphaPseudo::switchcpu(xc->xcBase());
813            }}, IsNonSpeculative);
814            0x53: m5addsymbol({{
815                AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
816            }}, IsNonSpeculative);
817            0x54: m5panic({{
818                panic("M5 panic instruction called at pc=%#x.", xc->readPC());
819            }}, IsNonSpeculative);
820
821        }
822    }
823#endif
824}
825