decoder.isa revision 8780
19520SAndreas.Sandberg@ARM.com// -*- mode:c++ -*- 29520SAndreas.Sandberg@ARM.com 39520SAndreas.Sandberg@ARM.com// Copyright (c) 2003-2006 The Regents of The University of Michigan 49520SAndreas.Sandberg@ARM.com// All rights reserved. 59520SAndreas.Sandberg@ARM.com// 69520SAndreas.Sandberg@ARM.com// Redistribution and use in source and binary forms, with or without 79520SAndreas.Sandberg@ARM.com// modification, are permitted provided that the following conditions are 89520SAndreas.Sandberg@ARM.com// met: redistributions of source code must retain the above copyright 99520SAndreas.Sandberg@ARM.com// notice, this list of conditions and the following disclaimer; 109520SAndreas.Sandberg@ARM.com// redistributions in binary form must reproduce the above copyright 119520SAndreas.Sandberg@ARM.com// notice, this list of conditions and the following disclaimer in the 129520SAndreas.Sandberg@ARM.com// documentation and/or other materials provided with the distribution; 139520SAndreas.Sandberg@ARM.com// neither the name of the copyright holders nor the names of its 149520SAndreas.Sandberg@ARM.com// contributors may be used to endorse or promote products derived from 159520SAndreas.Sandberg@ARM.com// this software without specific prior written permission. 169520SAndreas.Sandberg@ARM.com// 179520SAndreas.Sandberg@ARM.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 189520SAndreas.Sandberg@ARM.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 199520SAndreas.Sandberg@ARM.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 209520SAndreas.Sandberg@ARM.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 219520SAndreas.Sandberg@ARM.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 229520SAndreas.Sandberg@ARM.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 239520SAndreas.Sandberg@ARM.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 249520SAndreas.Sandberg@ARM.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 259520SAndreas.Sandberg@ARM.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 269520SAndreas.Sandberg@ARM.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 279520SAndreas.Sandberg@ARM.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 289520SAndreas.Sandberg@ARM.com// 299520SAndreas.Sandberg@ARM.com// Authors: Steve Reinhardt 309520SAndreas.Sandberg@ARM.com 319520SAndreas.Sandberg@ARM.com//////////////////////////////////////////////////////////////////// 329520SAndreas.Sandberg@ARM.com// 339520SAndreas.Sandberg@ARM.com// The actual decoder specification 349520SAndreas.Sandberg@ARM.com// 359520SAndreas.Sandberg@ARM.com 369520SAndreas.Sandberg@ARM.comdecode OPCODE default Unknown::unknown() { 379520SAndreas.Sandberg@ARM.com 389520SAndreas.Sandberg@ARM.com format LoadAddress { 399520SAndreas.Sandberg@ARM.com 0x08: lda({{ Ra = Rb + disp; }}); 409520SAndreas.Sandberg@ARM.com 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 419520SAndreas.Sandberg@ARM.com } 429520SAndreas.Sandberg@ARM.com 439520SAndreas.Sandberg@ARM.com format LoadOrNop { 449520SAndreas.Sandberg@ARM.com 0x0a: ldbu({{ Ra_uq = Mem_ub; }}); 459520SAndreas.Sandberg@ARM.com 0x0c: ldwu({{ Ra_uq = Mem_uw; }}); 469520SAndreas.Sandberg@ARM.com 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 479520SAndreas.Sandberg@ARM.com 0x23: ldt({{ Fa = Mem_df; }}); 489520SAndreas.Sandberg@ARM.com 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC); 499520SAndreas.Sandberg@ARM.com 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC); 509520SAndreas.Sandberg@ARM.com } 519520SAndreas.Sandberg@ARM.com 529520SAndreas.Sandberg@ARM.com format LoadOrPrefetch { 539520SAndreas.Sandberg@ARM.com 0x28: ldl({{ Ra_sl = Mem_sl; }}); 549520SAndreas.Sandberg@ARM.com 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT); 559520SAndreas.Sandberg@ARM.com // IsFloating flag on lds gets the prefetch to disassemble 569520SAndreas.Sandberg@ARM.com // using f31 instead of r31... funcitonally it's unnecessary 579520SAndreas.Sandberg@ARM.com 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }}, 589520SAndreas.Sandberg@ARM.com pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 599520SAndreas.Sandberg@ARM.com } 609520SAndreas.Sandberg@ARM.com 619520SAndreas.Sandberg@ARM.com format Store { 629520SAndreas.Sandberg@ARM.com 0x0e: stb({{ Mem_ub = Ra<7:0>; }}); 639520SAndreas.Sandberg@ARM.com 0x0d: stw({{ Mem_uw = Ra<15:0>; }}); 649520SAndreas.Sandberg@ARM.com 0x2c: stl({{ Mem_ul = Ra<31:0>; }}); 659520SAndreas.Sandberg@ARM.com 0x2d: stq({{ Mem_uq = Ra_uq; }}); 669520SAndreas.Sandberg@ARM.com 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }}); 679520SAndreas.Sandberg@ARM.com 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }}); 689520SAndreas.Sandberg@ARM.com 0x27: stt({{ Mem_df = Fa; }}); 699520SAndreas.Sandberg@ARM.com } 709520SAndreas.Sandberg@ARM.com 719520SAndreas.Sandberg@ARM.com format StoreCond { 729520SAndreas.Sandberg@ARM.com 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }}, 739520SAndreas.Sandberg@ARM.com {{ 749520SAndreas.Sandberg@ARM.com uint64_t tmp = write_result; 759520SAndreas.Sandberg@ARM.com // see stq_c 769520SAndreas.Sandberg@ARM.com Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 779520SAndreas.Sandberg@ARM.com if (tmp == 1) { 789520SAndreas.Sandberg@ARM.com xc->setStCondFailures(0); 799520SAndreas.Sandberg@ARM.com } 809520SAndreas.Sandberg@ARM.com }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 819520SAndreas.Sandberg@ARM.com 0x2f: stq_c({{ Mem_uq = Ra; }}, 829520SAndreas.Sandberg@ARM.com {{ 839520SAndreas.Sandberg@ARM.com uint64_t tmp = write_result; 849520SAndreas.Sandberg@ARM.com // If the write operation returns 0 or 1, then 859520SAndreas.Sandberg@ARM.com // this was a conventional store conditional, 869520SAndreas.Sandberg@ARM.com // and the value indicates the success/failure 879520SAndreas.Sandberg@ARM.com // of the operation. If another value is 889520SAndreas.Sandberg@ARM.com // returned, then this was a Turbolaser 899520SAndreas.Sandberg@ARM.com // mailbox access, and we don't update the 909520SAndreas.Sandberg@ARM.com // result register at all. 919520SAndreas.Sandberg@ARM.com Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 929520SAndreas.Sandberg@ARM.com if (tmp == 1) { 939520SAndreas.Sandberg@ARM.com // clear failure counter... this is 949520SAndreas.Sandberg@ARM.com // non-architectural and for debugging 959520SAndreas.Sandberg@ARM.com // only. 969520SAndreas.Sandberg@ARM.com xc->setStCondFailures(0); 979520SAndreas.Sandberg@ARM.com } 989520SAndreas.Sandberg@ARM.com }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 999520SAndreas.Sandberg@ARM.com } 1009520SAndreas.Sandberg@ARM.com 1019520SAndreas.Sandberg@ARM.com format IntegerOperate { 1029520SAndreas.Sandberg@ARM.com 1039520SAndreas.Sandberg@ARM.com 0x10: decode INTFUNC { // integer arithmetic operations 1049520SAndreas.Sandberg@ARM.com 1059520SAndreas.Sandberg@ARM.com 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }}); 1069520SAndreas.Sandberg@ARM.com 0x40: addlv({{ 1079520SAndreas.Sandberg@ARM.com int32_t tmp = Ra_sl + Rb_or_imm_sl; 1089520SAndreas.Sandberg@ARM.com // signed overflow occurs when operands have same sign 1099520SAndreas.Sandberg@ARM.com // and sign of result does not match. 1109520SAndreas.Sandberg@ARM.com if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>) 1119520SAndreas.Sandberg@ARM.com fault = new IntegerOverflowFault; 1129520SAndreas.Sandberg@ARM.com Rc_sl = tmp; 1139520SAndreas.Sandberg@ARM.com }}); 1149520SAndreas.Sandberg@ARM.com 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }}); 1159520SAndreas.Sandberg@ARM.com 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }}); 1169520SAndreas.Sandberg@ARM.com 1179520SAndreas.Sandberg@ARM.com 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 1189520SAndreas.Sandberg@ARM.com 0x60: addqv({{ 1199520SAndreas.Sandberg@ARM.com uint64_t tmp = Ra + Rb_or_imm; 1209520SAndreas.Sandberg@ARM.com // signed overflow occurs when operands have same sign 1219520SAndreas.Sandberg@ARM.com // and sign of result does not match. 1229520SAndreas.Sandberg@ARM.com if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1239520SAndreas.Sandberg@ARM.com fault = new IntegerOverflowFault; 1249520SAndreas.Sandberg@ARM.com Rc = tmp; 1259520SAndreas.Sandberg@ARM.com }}); 1269520SAndreas.Sandberg@ARM.com 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 1279520SAndreas.Sandberg@ARM.com 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 1289520SAndreas.Sandberg@ARM.com 1299520SAndreas.Sandberg@ARM.com 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }}); 1309520SAndreas.Sandberg@ARM.com 0x49: sublv({{ 1319520SAndreas.Sandberg@ARM.com int32_t tmp = Ra_sl - Rb_or_imm_sl; 1329520SAndreas.Sandberg@ARM.com // signed overflow detection is same as for add, 133 // except we need to look at the *complemented* 134 // sign bit of the subtrahend (Rb), i.e., if the initial 135 // signs are the *same* then no overflow can occur 136 if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>) 137 fault = new IntegerOverflowFault; 138 Rc_sl = tmp; 139 }}); 140 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }}); 141 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }}); 142 143 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 144 0x69: subqv({{ 145 uint64_t tmp = Ra - Rb_or_imm; 146 // signed overflow detection is same as for add, 147 // except we need to look at the *complemented* 148 // sign bit of the subtrahend (Rb), i.e., if the initial 149 // signs are the *same* then no overflow can occur 150 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 151 fault = new IntegerOverflowFault; 152 Rc = tmp; 153 }}); 154 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 155 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 156 157 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 158 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }}); 159 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }}); 160 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }}); 161 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }}); 162 163 0x0f: cmpbge({{ 164 int hi = 7; 165 int lo = 0; 166 uint64_t tmp = 0; 167 for (int i = 0; i < 8; ++i) { 168 tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i; 169 hi += 8; 170 lo += 8; 171 } 172 Rc = tmp; 173 }}); 174 } 175 176 0x11: decode INTFUNC { // integer logical operations 177 178 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 179 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 180 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 181 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 182 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 183 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 184 185 // conditional moves 186 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 187 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 188 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 189 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 190 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }}); 191 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }}); 192 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }}); 193 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }}); 194 195 // For AMASK, RA must be R31. 196 0x61: decode RA { 197 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 198 } 199 200 // For IMPLVER, RA must be R31 and the B operand 201 // must be the immediate value 1. 202 0x6c: decode RA { 203 31: decode IMM { 204 1: decode INTIMM { 205 // return EV5 for FullSystem and EV6 otherwise 206 1: implver({{ Rc = FullSystem ? 1 : 2 }}); 207 } 208 } 209 } 210 211 // The mysterious 11.25... 212 0x25: WarnUnimpl::eleven25(); 213 } 214 215 0x12: decode INTFUNC { 216 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 217 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }}); 218 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }}); 219 220 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 221 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 222 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 223 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 224 225 0x52: mskwh({{ 226 int bv = Rb_or_imm<2:0>; 227 Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 228 }}); 229 0x62: msklh({{ 230 int bv = Rb_or_imm<2:0>; 231 Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 232 }}); 233 0x72: mskqh({{ 234 int bv = Rb_or_imm<2:0>; 235 Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 236 }}); 237 238 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 239 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 240 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 241 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }}); 242 243 0x5a: extwh({{ 244 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 245 0x6a: extlh({{ 246 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 247 0x7a: extqh({{ 248 Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 249 250 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 251 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 252 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 253 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 254 255 0x57: inswh({{ 256 int bv = Rb_or_imm<2:0>; 257 Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0; 258 }}); 259 0x67: inslh({{ 260 int bv = Rb_or_imm<2:0>; 261 Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0; 262 }}); 263 0x77: insqh({{ 264 int bv = Rb_or_imm<2:0>; 265 Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0; 266 }}); 267 268 0x30: zap({{ 269 uint64_t zapmask = 0; 270 for (int i = 0; i < 8; ++i) { 271 if (Rb_or_imm<i:>) 272 zapmask |= (mask(8) << (i * 8)); 273 } 274 Rc = Ra & ~zapmask; 275 }}); 276 0x31: zapnot({{ 277 uint64_t zapmask = 0; 278 for (int i = 0; i < 8; ++i) { 279 if (!Rb_or_imm<i:>) 280 zapmask |= (mask(8) << (i * 8)); 281 } 282 Rc = Ra & ~zapmask; 283 }}); 284 } 285 286 0x13: decode INTFUNC { // integer multiplies 287 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp); 288 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 289 0x30: umulh({{ 290 uint64_t hi, lo; 291 mul128(Ra, Rb_or_imm, hi, lo); 292 Rc = hi; 293 }}, IntMultOp); 294 0x40: mullv({{ 295 // 32-bit multiply with trap on overflow 296 int64_t Rax = Ra_sl; // sign extended version of Ra_sl 297 int64_t Rbx = Rb_or_imm_sl; 298 int64_t tmp = Rax * Rbx; 299 // To avoid overflow, all the upper 32 bits must match 300 // the sign bit of the lower 32. We code this as 301 // checking the upper 33 bits for all 0s or all 1s. 302 uint64_t sign_bits = tmp<63:31>; 303 if (sign_bits != 0 && sign_bits != mask(33)) 304 fault = new IntegerOverflowFault; 305 Rc_sl = tmp<31:0>; 306 }}, IntMultOp); 307 0x60: mulqv({{ 308 // 64-bit multiply with trap on overflow 309 uint64_t hi, lo; 310 mul128(Ra, Rb_or_imm, hi, lo); 311 // all the upper 64 bits must match the sign bit of 312 // the lower 64 313 if (!((hi == 0 && lo<63:> == 0) || 314 (hi == mask(64) && lo<63:> == 1))) 315 fault = new IntegerOverflowFault; 316 Rc = lo; 317 }}, IntMultOp); 318 } 319 320 0x1c: decode INTFUNC { 321 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); } 322 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); } 323 324 0x30: ctpop({{ 325 uint64_t count = 0; 326 for (int i = 0; Rb<63:i>; ++i) { 327 if (Rb<i:i> == 0x1) 328 ++count; 329 } 330 Rc = count; 331 }}, IntAluOp); 332 333 0x31: perr({{ 334 uint64_t temp = 0; 335 int hi = 7; 336 int lo = 0; 337 for (int i = 0; i < 8; ++i) { 338 uint8_t ra_ub = Ra_uq<hi:lo>; 339 uint8_t rb_ub = Rb_uq<hi:lo>; 340 temp += (ra_ub >= rb_ub) ? 341 (ra_ub - rb_ub) : (rb_ub - ra_ub); 342 hi += 8; 343 lo += 8; 344 } 345 Rc = temp; 346 }}); 347 348 0x32: ctlz({{ 349 uint64_t count = 0; 350 uint64_t temp = Rb; 351 if (temp<63:32>) temp >>= 32; else count += 32; 352 if (temp<31:16>) temp >>= 16; else count += 16; 353 if (temp<15:8>) temp >>= 8; else count += 8; 354 if (temp<7:4>) temp >>= 4; else count += 4; 355 if (temp<3:2>) temp >>= 2; else count += 2; 356 if (temp<1:1>) temp >>= 1; else count += 1; 357 if ((temp<0:0>) != 0x1) count += 1; 358 Rc = count; 359 }}, IntAluOp); 360 361 0x33: cttz({{ 362 uint64_t count = 0; 363 uint64_t temp = Rb; 364 if (!(temp<31:0>)) { temp >>= 32; count += 32; } 365 if (!(temp<15:0>)) { temp >>= 16; count += 16; } 366 if (!(temp<7:0>)) { temp >>= 8; count += 8; } 367 if (!(temp<3:0>)) { temp >>= 4; count += 4; } 368 if (!(temp<1:0>)) { temp >>= 2; count += 2; } 369 if (!(temp<0:0> & ULL(0x1))) { 370 temp >>= 1; count += 1; 371 } 372 if (!(temp<0:0> & ULL(0x1))) count += 1; 373 Rc = count; 374 }}, IntAluOp); 375 376 377 0x34: unpkbw({{ 378 Rc = (Rb_uq<7:0> 379 | (Rb_uq<15:8> << 16) 380 | (Rb_uq<23:16> << 32) 381 | (Rb_uq<31:24> << 48)); 382 }}, IntAluOp); 383 384 0x35: unpkbl({{ 385 Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32)); 386 }}, IntAluOp); 387 388 0x36: pkwb({{ 389 Rc = (Rb_uq<7:0> 390 | (Rb_uq<23:16> << 8) 391 | (Rb_uq<39:32> << 16) 392 | (Rb_uq<55:48> << 24)); 393 }}, IntAluOp); 394 395 0x37: pklb({{ 396 Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8)); 397 }}, IntAluOp); 398 399 0x38: minsb8({{ 400 uint64_t temp = 0; 401 int hi = 63; 402 int lo = 56; 403 for (int i = 7; i >= 0; --i) { 404 int8_t ra_sb = Ra_uq<hi:lo>; 405 int8_t rb_sb = Rb_uq<hi:lo>; 406 temp = ((temp << 8) 407 | ((ra_sb < rb_sb) ? Ra_uq<hi:lo> 408 : Rb_uq<hi:lo>)); 409 hi -= 8; 410 lo -= 8; 411 } 412 Rc = temp; 413 }}); 414 415 0x39: minsw4({{ 416 uint64_t temp = 0; 417 int hi = 63; 418 int lo = 48; 419 for (int i = 3; i >= 0; --i) { 420 int16_t ra_sw = Ra_uq<hi:lo>; 421 int16_t rb_sw = Rb_uq<hi:lo>; 422 temp = ((temp << 16) 423 | ((ra_sw < rb_sw) ? Ra_uq<hi:lo> 424 : Rb_uq<hi:lo>)); 425 hi -= 16; 426 lo -= 16; 427 } 428 Rc = temp; 429 }}); 430 431 0x3a: minub8({{ 432 uint64_t temp = 0; 433 int hi = 63; 434 int lo = 56; 435 for (int i = 7; i >= 0; --i) { 436 uint8_t ra_ub = Ra_uq<hi:lo>; 437 uint8_t rb_ub = Rb_uq<hi:lo>; 438 temp = ((temp << 8) 439 | ((ra_ub < rb_ub) ? Ra_uq<hi:lo> 440 : Rb_uq<hi:lo>)); 441 hi -= 8; 442 lo -= 8; 443 } 444 Rc = temp; 445 }}); 446 447 0x3b: minuw4({{ 448 uint64_t temp = 0; 449 int hi = 63; 450 int lo = 48; 451 for (int i = 3; i >= 0; --i) { 452 uint16_t ra_sw = Ra_uq<hi:lo>; 453 uint16_t rb_sw = Rb_uq<hi:lo>; 454 temp = ((temp << 16) 455 | ((ra_sw < rb_sw) ? Ra_uq<hi:lo> 456 : Rb_uq<hi:lo>)); 457 hi -= 16; 458 lo -= 16; 459 } 460 Rc = temp; 461 }}); 462 463 0x3c: maxub8({{ 464 uint64_t temp = 0; 465 int hi = 63; 466 int lo = 56; 467 for (int i = 7; i >= 0; --i) { 468 uint8_t ra_ub = Ra_uq<hi:lo>; 469 uint8_t rb_ub = Rb_uq<hi:lo>; 470 temp = ((temp << 8) 471 | ((ra_ub > rb_ub) ? Ra_uq<hi:lo> 472 : Rb_uq<hi:lo>)); 473 hi -= 8; 474 lo -= 8; 475 } 476 Rc = temp; 477 }}); 478 479 0x3d: maxuw4({{ 480 uint64_t temp = 0; 481 int hi = 63; 482 int lo = 48; 483 for (int i = 3; i >= 0; --i) { 484 uint16_t ra_uw = Ra_uq<hi:lo>; 485 uint16_t rb_uw = Rb_uq<hi:lo>; 486 temp = ((temp << 16) 487 | ((ra_uw > rb_uw) ? Ra_uq<hi:lo> 488 : Rb_uq<hi:lo>)); 489 hi -= 16; 490 lo -= 16; 491 } 492 Rc = temp; 493 }}); 494 495 0x3e: maxsb8({{ 496 uint64_t temp = 0; 497 int hi = 63; 498 int lo = 56; 499 for (int i = 7; i >= 0; --i) { 500 int8_t ra_sb = Ra_uq<hi:lo>; 501 int8_t rb_sb = Rb_uq<hi:lo>; 502 temp = ((temp << 8) 503 | ((ra_sb > rb_sb) ? Ra_uq<hi:lo> 504 : Rb_uq<hi:lo>)); 505 hi -= 8; 506 lo -= 8; 507 } 508 Rc = temp; 509 }}); 510 511 0x3f: maxsw4({{ 512 uint64_t temp = 0; 513 int hi = 63; 514 int lo = 48; 515 for (int i = 3; i >= 0; --i) { 516 int16_t ra_sw = Ra_uq<hi:lo>; 517 int16_t rb_sw = Rb_uq<hi:lo>; 518 temp = ((temp << 16) 519 | ((ra_sw > rb_sw) ? Ra_uq<hi:lo> 520 : Rb_uq<hi:lo>)); 521 hi -= 16; 522 lo -= 16; 523 } 524 Rc = temp; 525 }}); 526 527 format BasicOperateWithNopCheck { 528 0x70: decode RB { 529 31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp); 530 } 531 0x78: decode RB { 532 31: ftois({{ Rc_sl = t_to_s(Fa_uq); }}, 533 FloatCvtOp); 534 } 535 } 536 } 537 } 538 539 // Conditional branches. 540 format CondBranch { 541 0x39: beq({{ cond = (Ra == 0); }}); 542 0x3d: bne({{ cond = (Ra != 0); }}); 543 0x3e: bge({{ cond = (Ra_sq >= 0); }}); 544 0x3f: bgt({{ cond = (Ra_sq > 0); }}); 545 0x3b: ble({{ cond = (Ra_sq <= 0); }}); 546 0x3a: blt({{ cond = (Ra_sq < 0); }}); 547 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 548 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 549 550 0x31: fbeq({{ cond = (Fa == 0); }}); 551 0x35: fbne({{ cond = (Fa != 0); }}); 552 0x36: fbge({{ cond = (Fa >= 0); }}); 553 0x37: fbgt({{ cond = (Fa > 0); }}); 554 0x33: fble({{ cond = (Fa <= 0); }}); 555 0x32: fblt({{ cond = (Fa < 0); }}); 556 } 557 558 // unconditional branches 559 format UncondBranch { 560 0x30: br(); 561 0x34: bsr(IsCall); 562 } 563 564 // indirect branches 565 0x1a: decode JMPFUNC { 566 format Jump { 567 0: jmp(); 568 1: jsr(IsCall); 569 2: ret(IsReturn); 570 3: jsr_coroutine(IsCall, IsReturn); 571 } 572 } 573 574 // Square root and integer-to-FP moves 575 0x14: decode FP_SHORTFUNC { 576 // Integer to FP register moves must have RB == 31 577 0x4: decode RB { 578 31: decode FP_FULLFUNC { 579 format BasicOperateWithNopCheck { 580 0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp); 581 0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp); 582 0x014: FailUnimpl::itoff(); // VAX-format conversion 583 } 584 } 585 } 586 587 // Square root instructions must have FA == 31 588 0xb: decode FA { 589 31: decode FP_TYPEFUNC { 590 format FloatingPointOperate { 591#if SS_COMPATIBLE_FP 592 0x0b: sqrts({{ 593 if (Fb < 0.0) 594 fault = new ArithmeticFault; 595 Fc = sqrt(Fb); 596 }}, FloatSqrtOp); 597#else 598 0x0b: sqrts({{ 599 if (Fb_sf < 0.0) 600 fault = new ArithmeticFault; 601 Fc_sf = sqrt(Fb_sf); 602 }}, FloatSqrtOp); 603#endif 604 0x2b: sqrtt({{ 605 if (Fb < 0.0) 606 fault = new ArithmeticFault; 607 Fc = sqrt(Fb); 608 }}, FloatSqrtOp); 609 } 610 } 611 } 612 613 // VAX-format sqrtf and sqrtg are not implemented 614 0xa: FailUnimpl::sqrtfg(); 615 } 616 617 // IEEE floating point 618 0x16: decode FP_SHORTFUNC_TOP2 { 619 // The top two bits of the short function code break this 620 // space into four groups: binary ops, compares, reserved, and 621 // conversions. See Table 4-12 of AHB. There are different 622 // special cases in these different groups, so we decode on 623 // these top two bits first just to select a decode strategy. 624 // Most of these instructions may have various trapping and 625 // rounding mode flags set; these are decoded in the 626 // FloatingPointDecode template used by the 627 // FloatingPointOperate format. 628 629 // add/sub/mul/div: just decode on the short function code 630 // and source type. All valid trapping and rounding modes apply. 631 0: decode FP_TRAPMODE { 632 // check for valid trapping modes here 633 0,1,5,7: decode FP_TYPEFUNC { 634 format FloatingPointOperate { 635#if SS_COMPATIBLE_FP 636 0x00: adds({{ Fc = Fa + Fb; }}); 637 0x01: subs({{ Fc = Fa - Fb; }}); 638 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 639 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 640#else 641 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }}); 642 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }}); 643 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp); 644 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp); 645#endif 646 647 0x20: addt({{ Fc = Fa + Fb; }}); 648 0x21: subt({{ Fc = Fa - Fb; }}); 649 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 650 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 651 } 652 } 653 } 654 655 // Floating-point compare instructions must have the default 656 // rounding mode, and may use the default trapping mode or 657 // /SU. Both trapping modes are treated the same by M5; the 658 // only difference on the real hardware (as far a I can tell) 659 // is that without /SU you'd get an imprecise trap if you 660 // tried to compare a NaN with something else (instead of an 661 // "unordered" result). 662 1: decode FP_FULLFUNC { 663 format BasicOperateWithNopCheck { 664 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 665 FloatCmpOp); 666 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 667 FloatCmpOp); 668 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 669 FloatCmpOp); 670 0x0a4, 0x5a4: cmptun({{ // unordered 671 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 672 }}, FloatCmpOp); 673 } 674 } 675 676 // The FP-to-integer and integer-to-FP conversion insts 677 // require that FA be 31. 678 3: decode FA { 679 31: decode FP_TYPEFUNC { 680 format FloatingPointOperate { 681 0x2f: decode FP_ROUNDMODE { 682 format FPFixedRounding { 683 // "chopped" i.e. round toward zero 684 0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }}, 685 Chopped); 686 // round to minus infinity 687 1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }}, 688 MinusInfinity); 689 } 690 default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }}); 691 } 692 693 // The cvtts opcode is overloaded to be cvtst if the trap 694 // mode is 2 or 6 (which are not valid otherwise) 695 0x2c: decode FP_FULLFUNC { 696 format BasicOperateWithNopCheck { 697 // trap on denorm version "cvtst/s" is 698 // simulated same as cvtst 699 0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }}); 700 } 701 default: cvtts({{ Fc_sf = Fb; }}); 702 } 703 704 // The trapping mode for integer-to-FP conversions 705 // must be /SUI or nothing; /U and /SU are not 706 // allowed. The full set of rounding modes are 707 // supported though. 708 0x3c: decode FP_TRAPMODE { 709 0,7: cvtqs({{ Fc_sf = Fb_sq; }}); 710 } 711 0x3e: decode FP_TRAPMODE { 712 0,7: cvtqt({{ Fc = Fb_sq; }}); 713 } 714 } 715 } 716 } 717 } 718 719 // misc FP operate 720 0x17: decode FP_FULLFUNC { 721 format BasicOperateWithNopCheck { 722 0x010: cvtlq({{ 723 Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>; 724 }}); 725 0x030: cvtql({{ 726 Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29); 727 }}); 728 729 // We treat the precise & imprecise trapping versions of 730 // cvtql identically. 731 0x130, 0x530: cvtqlv({{ 732 // To avoid overflow, all the upper 32 bits must match 733 // the sign bit of the lower 32. We code this as 734 // checking the upper 33 bits for all 0s or all 1s. 735 uint64_t sign_bits = Fb_uq<63:31>; 736 if (sign_bits != 0 && sign_bits != mask(33)) 737 fault = new IntegerOverflowFault; 738 Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29); 739 }}); 740 741 0x020: cpys({{ // copy sign 742 Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>; 743 }}); 744 0x021: cpysn({{ // copy sign negated 745 Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>; 746 }}); 747 0x022: cpyse({{ // copy sign and exponent 748 Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>; 749 }}); 750 751 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 752 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 753 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 754 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 755 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 756 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 757 758 0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess); 759 0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess); 760 } 761 } 762 763 // miscellaneous mem-format ops 764 0x18: decode MEMFUNC { 765 format WarnUnimpl { 766 0x8000: fetch(); 767 0xa000: fetch_m(); 768 0xe800: ecb(); 769 } 770 771 format MiscPrefetch { 772 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 773 {{ ; }}, 774 mem_flags = PREFETCH); 775 } 776 777 format BasicOperate { 778 0xc000: rpcc({{ 779 /* Rb is a fake dependency so here is a fun way to get 780 * the parser to understand that. 781 */ 782 uint64_t unused_var M5_VAR_USED = Rb; 783 Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick(); 784 }}, IsUnverifiable); 785 786 // All of the barrier instructions below do nothing in 787 // their execute() methods (hence the empty code blocks). 788 // All of their functionality is hard-coded in the 789 // pipeline based on the flags IsSerializing, 790 // IsMemBarrier, and IsWriteBarrier. In the current 791 // detailed CPU model, the execute() function only gets 792 // called at fetch, so there's no way to generate pipeline 793 // behavior at any other stage. Once we go to an 794 // exec-in-exec CPU model we should be able to get rid of 795 // these flags and implement this behavior via the 796 // execute() methods. 797 798 // trapb is just a barrier on integer traps, where excb is 799 // a barrier on integer and FP traps. "EXCB is thus a 800 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 801 // them the same though. 802 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 803 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 804 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 805 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 806 } 807 808 0xe000: decode FullSystem { 809 0: FailUnimpl::rc_se(); 810 default: BasicOperate::rc({{ 811 Ra = IntrFlag; 812 IntrFlag = 0; 813 }}, IsNonSpeculative, IsUnverifiable); 814 } 815 0xf000: decode FullSystem { 816 0: FailUnimpl::rs_se(); 817 default: BasicOperate::rs({{ 818 Ra = IntrFlag; 819 IntrFlag = 1; 820 }}, IsNonSpeculative, IsUnverifiable); 821 } 822 } 823 824 0x00: decode FullSystem { 825 0: decode PALFUNC { 826 format EmulatedCallPal { 827 0x00: halt ({{ 828 exitSimLoop("halt instruction encountered"); 829 }}, IsNonSpeculative); 830 0x83: callsys({{ 831 xc->syscall(R0); 832 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 833 // Read uniq reg into ABI return value register (r0) 834 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); 835 // Write uniq reg with value from ABI arg register (r16) 836 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess); 837 } 838 } 839 default: CallPal::call_pal({{ 840 if (!palValid || 841 (palPriv 842 && xc->readMiscReg(IPR_ICM) != mode_kernel)) { 843 // invalid pal function code, or attempt to do privileged 844 // PAL call in non-kernel mode 845 fault = new UnimplementedOpcodeFault; 846 } else { 847 // check to see if simulator wants to do something special 848 // on this PAL call (including maybe suppress it) 849 bool dopal = xc->simPalCheck(palFunc); 850 851 if (dopal) { 852 xc->setMiscReg(IPR_EXC_ADDR, NPC); 853 NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset; 854 } 855 } 856 }}, IsNonSpeculative); 857 } 858 859 0x1b: decode PALMODE { 860 0: OpcdecFault::hw_st_quad(); 861 1: decode HW_LDST_QUAD { 862 format HwLoad { 863 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }}, 864 L, IsSerializing, IsSerializeBefore); 865 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }}, 866 Q, IsSerializing, IsSerializeBefore); 867 } 868 } 869 } 870 871 0x1f: decode PALMODE { 872 0: OpcdecFault::hw_st_cond(); 873 format HwStore { 874 1: decode HW_LDST_COND { 875 0: decode HW_LDST_QUAD { 876 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 877 {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore); 878 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 879 {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore); 880 } 881 882 1: FailUnimpl::hw_st_cond(); 883 } 884 } 885 } 886 887 0x19: decode PALMODE { 888 0: OpcdecFault::hw_mfpr(); 889 format HwMoveIPR { 890 1: hw_mfpr({{ 891 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 892 IprToMiscRegIndex[ipr_index] : -1; 893 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || 894 miscRegIndex >= NumInternalProcRegs) 895 fault = new UnimplementedOpcodeFault; 896 else 897 Ra = xc->readMiscReg(miscRegIndex); 898 }}, IsIprAccess); 899 } 900 } 901 902 0x1d: decode PALMODE { 903 0: OpcdecFault::hw_mtpr(); 904 format HwMoveIPR { 905 1: hw_mtpr({{ 906 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 907 IprToMiscRegIndex[ipr_index] : -1; 908 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) || 909 miscRegIndex >= NumInternalProcRegs) 910 fault = new UnimplementedOpcodeFault; 911 else 912 xc->setMiscReg(miscRegIndex, Ra); 913 if (traceData) { traceData->setData(Ra); } 914 }}, IsIprAccess); 915 } 916 } 917 918 0x1e: decode PALMODE { 919 0: OpcdecFault::hw_rei(); 920 format BasicOperate { 921 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); 922 } 923 } 924 925 format BasicOperate { 926 // M5 special opcodes use the reserved 0x01 opcode space 927 0x01: decode M5FUNC { 928 0x00: arm({{ 929 PseudoInst::arm(xc->tcBase()); 930 }}, IsNonSpeculative); 931 0x01: quiesce({{ 932 PseudoInst::quiesce(xc->tcBase()); 933 }}, IsNonSpeculative, IsQuiesce); 934 0x02: quiesceNs({{ 935 PseudoInst::quiesceNs(xc->tcBase(), R16); 936 }}, IsNonSpeculative, IsQuiesce); 937 0x03: quiesceCycles({{ 938 PseudoInst::quiesceCycles(xc->tcBase(), R16); 939 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 940 0x04: quiesceTime({{ 941 R0 = PseudoInst::quiesceTime(xc->tcBase()); 942 }}, IsNonSpeculative, IsUnverifiable); 943 0x07: rpns({{ 944 R0 = PseudoInst::rpns(xc->tcBase()); 945 }}, IsNonSpeculative, IsUnverifiable); 946 0x09: wakeCPU({{ 947 PseudoInst::wakeCPU(xc->tcBase(), R16); 948 }}, IsNonSpeculative, IsUnverifiable); 949 0x10: deprecated_ivlb({{ 950 warn_once("Obsolete M5 ivlb instruction encountered.\n"); 951 }}); 952 0x11: deprecated_ivle({{ 953 warn_once("Obsolete M5 ivlb instruction encountered.\n"); 954 }}); 955 0x20: deprecated_exit ({{ 956 warn_once("deprecated M5 exit instruction encountered.\n"); 957 PseudoInst::m5exit(xc->tcBase(), 0); 958 }}, No_OpClass, IsNonSpeculative); 959 0x21: m5exit({{ 960 PseudoInst::m5exit(xc->tcBase(), R16); 961 }}, No_OpClass, IsNonSpeculative); 962 0x31: loadsymbol({{ 963 PseudoInst::loadsymbol(xc->tcBase()); 964 }}, No_OpClass, IsNonSpeculative); 965 0x30: initparam({{ 966 Ra = PseudoInst::initParam(xc->tcBase()); 967 }}); 968 0x40: resetstats({{ 969 PseudoInst::resetstats(xc->tcBase(), R16, R17); 970 }}, IsNonSpeculative); 971 0x41: dumpstats({{ 972 PseudoInst::dumpstats(xc->tcBase(), R16, R17); 973 }}, IsNonSpeculative); 974 0x42: dumpresetstats({{ 975 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17); 976 }}, IsNonSpeculative); 977 0x43: m5checkpoint({{ 978 PseudoInst::m5checkpoint(xc->tcBase(), R16, R17); 979 }}, IsNonSpeculative); 980 0x50: m5readfile({{ 981 R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18); 982 }}, IsNonSpeculative); 983 0x51: m5break({{ 984 PseudoInst::debugbreak(xc->tcBase()); 985 }}, IsNonSpeculative); 986 0x52: m5switchcpu({{ 987 PseudoInst::switchcpu(xc->tcBase()); 988 }}, IsNonSpeculative); 989 0x53: m5addsymbol({{ 990 PseudoInst::addsymbol(xc->tcBase(), R16, R17); 991 }}, IsNonSpeculative); 992 0x54: m5panic({{ 993 panic("M5 panic instruction called at pc = %#x.", PC); 994 }}, IsNonSpeculative); 995#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase()) 996 0x55: decode RA { 997 0x00: m5a_old({{ 998 panic("Deprecated M5 annotate instruction executed " 999 "at pc = %#x\n", PC); 1000 }}, IsNonSpeculative); 1001 0x01: m5a_bsm({{ 1002 CPANN(swSmBegin); 1003 }}, IsNonSpeculative); 1004 0x02: m5a_esm({{ 1005 CPANN(swSmEnd); 1006 }}, IsNonSpeculative); 1007 0x03: m5a_begin({{ 1008 CPANN(swExplictBegin); 1009 }}, IsNonSpeculative); 1010 0x04: m5a_end({{ 1011 CPANN(swEnd); 1012 }}, IsNonSpeculative); 1013 0x06: m5a_q({{ 1014 CPANN(swQ); 1015 }}, IsNonSpeculative); 1016 0x07: m5a_dq({{ 1017 CPANN(swDq); 1018 }}, IsNonSpeculative); 1019 0x08: m5a_wf({{ 1020 CPANN(swWf); 1021 }}, IsNonSpeculative); 1022 0x09: m5a_we({{ 1023 CPANN(swWe); 1024 }}, IsNonSpeculative); 1025 0x0C: m5a_sq({{ 1026 CPANN(swSq); 1027 }}, IsNonSpeculative); 1028 0x0D: m5a_aq({{ 1029 CPANN(swAq); 1030 }}, IsNonSpeculative); 1031 0x0E: m5a_pq({{ 1032 CPANN(swPq); 1033 }}, IsNonSpeculative); 1034 0x0F: m5a_l({{ 1035 CPANN(swLink); 1036 }}, IsNonSpeculative); 1037 0x10: m5a_identify({{ 1038 CPANN(swIdentify); 1039 }}, IsNonSpeculative); 1040 0x11: m5a_getid({{ 1041 R0 = CPANN(swGetId); 1042 }}, IsNonSpeculative); 1043 0x13: m5a_scl({{ 1044 CPANN(swSyscallLink); 1045 }}, IsNonSpeculative); 1046 0x14: m5a_rq({{ 1047 CPANN(swRq); 1048 }}, IsNonSpeculative); 1049 } // M5 Annotate Operations 1050#undef CPANN 1051 0x56: m5reserved2({{ 1052 warn("M5 reserved opcode ignored"); 1053 }}, IsNonSpeculative); 1054 0x57: m5reserved3({{ 1055 warn("M5 reserved opcode ignored"); 1056 }}, IsNonSpeculative); 1057 0x58: m5reserved4({{ 1058 warn("M5 reserved opcode ignored"); 1059 }}, IsNonSpeculative); 1060 0x59: m5reserved5({{ 1061 warn("M5 reserved opcode ignored"); 1062 }}, IsNonSpeculative); 1063 } 1064 } 1065} 1066