decoder.isa revision 8555
12068SN/A// -*- mode:c++ -*-
22068SN/A
32188SN/A// Copyright (c) 2003-2006 The Regents of The University of Michigan
42068SN/A// All rights reserved.
52068SN/A//
62068SN/A// Redistribution and use in source and binary forms, with or without
72068SN/A// modification, are permitted provided that the following conditions are
82068SN/A// met: redistributions of source code must retain the above copyright
92068SN/A// notice, this list of conditions and the following disclaimer;
102068SN/A// redistributions in binary form must reproduce the above copyright
112068SN/A// notice, this list of conditions and the following disclaimer in the
122068SN/A// documentation and/or other materials provided with the distribution;
132068SN/A// neither the name of the copyright holders nor the names of its
142068SN/A// contributors may be used to endorse or promote products derived from
152068SN/A// this software without specific prior written permission.
162068SN/A//
172068SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182068SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192068SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202068SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212068SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222068SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232068SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242068SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252068SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262068SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272068SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu//
292665Ssaidi@eecs.umich.edu// Authors: Steve Reinhardt
302068SN/A
312649Ssaidi@eecs.umich.edu////////////////////////////////////////////////////////////////////
322649Ssaidi@eecs.umich.edu//
332649Ssaidi@eecs.umich.edu// The actual decoder specification
342649Ssaidi@eecs.umich.edu//
352649Ssaidi@eecs.umich.edu
362068SN/Adecode OPCODE default Unknown::unknown() {
372068SN/A
382068SN/A    format LoadAddress {
392068SN/A        0x08: lda({{ Ra = Rb + disp; }});
402068SN/A        0x09: ldah({{ Ra = Rb + (disp << 16); }});
412068SN/A    }
422068SN/A
432068SN/A    format LoadOrNop {
442075SN/A        0x0a: ldbu({{ Ra.uq = Mem.ub; }});
452075SN/A        0x0c: ldwu({{ Ra.uq = Mem.uw; }});
462075SN/A        0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
472075SN/A        0x23: ldt({{ Fa = Mem.df; }});
486076Sgblack@eecs.umich.edu        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
496076Sgblack@eecs.umich.edu        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
502068SN/A    }
512068SN/A
522068SN/A    format LoadOrPrefetch {
532075SN/A        0x28: ldl({{ Ra.sl = Mem.sl; }});
542075SN/A        0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
552068SN/A        // IsFloating flag on lds gets the prefetch to disassemble
562068SN/A        // using f31 instead of r31... funcitonally it's unnecessary
572075SN/A        0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
582075SN/A                  pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
592068SN/A    }
602068SN/A
612068SN/A    format Store {
622075SN/A        0x0e: stb({{ Mem.ub = Ra<7:0>; }});
632075SN/A        0x0d: stw({{ Mem.uw = Ra<15:0>; }});
642075SN/A        0x2c: stl({{ Mem.ul = Ra<31:0>; }});
652075SN/A        0x2d: stq({{ Mem.uq = Ra.uq; }});
662075SN/A        0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
672075SN/A        0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
682075SN/A        0x27: stt({{ Mem.df = Fa; }});
692068SN/A    }
702068SN/A
712068SN/A    format StoreCond {
722075SN/A        0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
732068SN/A                    {{
742069SN/A                        uint64_t tmp = write_result;
752068SN/A                        // see stq_c
762068SN/A                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
774027Sstever@eecs.umich.edu                        if (tmp == 1) {
784027Sstever@eecs.umich.edu                            xc->setStCondFailures(0);
794027Sstever@eecs.umich.edu                        }
806076Sgblack@eecs.umich.edu                    }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
812075SN/A        0x2f: stq_c({{ Mem.uq = Ra; }},
822068SN/A                    {{
832069SN/A                        uint64_t tmp = write_result;
842068SN/A                        // If the write operation returns 0 or 1, then
852068SN/A                        // this was a conventional store conditional,
862068SN/A                        // and the value indicates the success/failure
872068SN/A                        // of the operation.  If another value is
882068SN/A                        // returned, then this was a Turbolaser
892068SN/A                        // mailbox access, and we don't update the
902068SN/A                        // result register at all.
912068SN/A                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
924027Sstever@eecs.umich.edu                        if (tmp == 1) {
934027Sstever@eecs.umich.edu                            // clear failure counter... this is
944027Sstever@eecs.umich.edu                            // non-architectural and for debugging
954027Sstever@eecs.umich.edu                            // only.
964027Sstever@eecs.umich.edu                            xc->setStCondFailures(0);
974027Sstever@eecs.umich.edu                        }
986076Sgblack@eecs.umich.edu                    }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
992068SN/A    }
1002068SN/A
1012068SN/A    format IntegerOperate {
1022068SN/A
1037799Sgblack@eecs.umich.edu        0x10: decode INTFUNC {  // integer arithmetic operations
1042068SN/A
1052068SN/A            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1062068SN/A            0x40: addlv({{
1076227Snate@binkert.org                int32_t tmp  = Ra.sl + Rb_or_imm.sl;
1082068SN/A                // signed overflow occurs when operands have same sign
1092068SN/A                // and sign of result does not match.
1102068SN/A                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1112147SN/A                    fault = new IntegerOverflowFault;
1122068SN/A                Rc.sl = tmp;
1132068SN/A            }});
1142068SN/A            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1152068SN/A            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1162068SN/A
1172068SN/A            0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1182068SN/A            0x60: addqv({{
1192068SN/A                uint64_t tmp = Ra + Rb_or_imm;
1202068SN/A                // signed overflow occurs when operands have same sign
1212068SN/A                // and sign of result does not match.
1222068SN/A                if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1232147SN/A                    fault = new IntegerOverflowFault;
1242068SN/A                Rc = tmp;
1252068SN/A            }});
1262068SN/A            0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1272068SN/A            0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1282068SN/A
1292068SN/A            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1302068SN/A            0x49: sublv({{
1316227Snate@binkert.org                int32_t tmp  = Ra.sl - Rb_or_imm.sl;
1322068SN/A                // signed overflow detection is same as for add,
1332068SN/A                // except we need to look at the *complemented*
1342068SN/A                // sign bit of the subtrahend (Rb), i.e., if the initial
1352068SN/A                // signs are the *same* then no overflow can occur
1362068SN/A                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1372147SN/A                    fault = new IntegerOverflowFault;
1382068SN/A                Rc.sl = tmp;
1392068SN/A            }});
1402068SN/A            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1412068SN/A            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1422068SN/A
1432068SN/A            0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1442068SN/A            0x69: subqv({{
1452068SN/A                uint64_t tmp  = Ra - Rb_or_imm;
1462068SN/A                // signed overflow detection is same as for add,
1472068SN/A                // except we need to look at the *complemented*
1482068SN/A                // sign bit of the subtrahend (Rb), i.e., if the initial
1492068SN/A                // signs are the *same* then no overflow can occur
1502068SN/A                if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1512147SN/A                    fault = new IntegerOverflowFault;
1522068SN/A                Rc = tmp;
1532068SN/A            }});
1542068SN/A            0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1552068SN/A            0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1562068SN/A
1572068SN/A            0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1582068SN/A            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1592068SN/A            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
1602068SN/A            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1612068SN/A            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
1622068SN/A
1632068SN/A            0x0f: cmpbge({{
1642068SN/A                int hi = 7;
1652068SN/A                int lo = 0;
1662068SN/A                uint64_t tmp = 0;
1672068SN/A                for (int i = 0; i < 8; ++i) {
1682068SN/A                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1692068SN/A                    hi += 8;
1702068SN/A                    lo += 8;
1712068SN/A                }
1722068SN/A                Rc = tmp;
1732068SN/A            }});
1742068SN/A        }
1752068SN/A
1767799Sgblack@eecs.umich.edu        0x11: decode INTFUNC {  // integer logical operations
1772068SN/A
1782068SN/A            0x00: and({{ Rc = Ra & Rb_or_imm; }});
1792068SN/A            0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1802068SN/A            0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1812068SN/A            0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1822068SN/A            0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1832068SN/A            0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1842068SN/A
1852068SN/A            // conditional moves
1862068SN/A            0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
1872068SN/A            0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
1882068SN/A            0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
1892068SN/A            0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
1902068SN/A            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
1912068SN/A            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
1922068SN/A            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
1932068SN/A            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
1942068SN/A
1952068SN/A            // For AMASK, RA must be R31.
1962068SN/A            0x61: decode RA {
1972068SN/A                31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
1982068SN/A            }
1992068SN/A
2002068SN/A            // For IMPLVER, RA must be R31 and the B operand
2012068SN/A            // must be the immediate value 1.
2022068SN/A            0x6c: decode RA {
2032068SN/A                31: decode IMM {
2042068SN/A                    1: decode INTIMM {
2052068SN/A                        // return EV5 for FULL_SYSTEM and EV6 otherwise
2062068SN/A                        1: implver({{
2072068SN/A#if FULL_SYSTEM
2082068SN/A                             Rc = 1;
2092068SN/A#else
2102068SN/A                             Rc = 2;
2112068SN/A#endif
2122068SN/A                        }});
2132068SN/A                    }
2142068SN/A                }
2152068SN/A            }
2162068SN/A
2172068SN/A#if FULL_SYSTEM
2182068SN/A            // The mysterious 11.25...
2192068SN/A            0x25: WarnUnimpl::eleven25();
2202068SN/A#endif
2212068SN/A        }
2222068SN/A
2232068SN/A        0x12: decode INTFUNC {
2242068SN/A            0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
2252068SN/A            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
2262068SN/A            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
2272068SN/A
2282068SN/A            0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
2292068SN/A            0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
2302068SN/A            0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
2312068SN/A            0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
2322068SN/A
2332068SN/A            0x52: mskwh({{
2342068SN/A                int bv = Rb_or_imm<2:0>;
2352068SN/A                Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
2362068SN/A            }});
2372068SN/A            0x62: msklh({{
2382068SN/A                int bv = Rb_or_imm<2:0>;
2392068SN/A                Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
2402068SN/A            }});
2412068SN/A            0x72: mskqh({{
2422068SN/A                int bv = Rb_or_imm<2:0>;
2432068SN/A                Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
2442068SN/A            }});
2452068SN/A
2462068SN/A            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
2472068SN/A            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
2482068SN/A            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
2492068SN/A            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
2502068SN/A
2512068SN/A            0x5a: extwh({{
2522068SN/A                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
2532068SN/A            0x6a: extlh({{
2542068SN/A                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
2552068SN/A            0x7a: extqh({{
2562068SN/A                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
2572068SN/A
2582068SN/A            0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
2592068SN/A            0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
2602068SN/A            0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
2612068SN/A            0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
2622068SN/A
2632068SN/A            0x57: inswh({{
2642068SN/A                int bv = Rb_or_imm<2:0>;
2652068SN/A                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
2662068SN/A            }});
2672068SN/A            0x67: inslh({{
2682068SN/A                int bv = Rb_or_imm<2:0>;
2692068SN/A                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2702068SN/A            }});
2712068SN/A            0x77: insqh({{
2722068SN/A                int bv = Rb_or_imm<2:0>;
2732068SN/A                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
2742068SN/A            }});
2752068SN/A
2762068SN/A            0x30: zap({{
2772068SN/A                uint64_t zapmask = 0;
2782068SN/A                for (int i = 0; i < 8; ++i) {
2792068SN/A                    if (Rb_or_imm<i:>)
2802068SN/A                        zapmask |= (mask(8) << (i * 8));
2812068SN/A                }
2822068SN/A                Rc = Ra & ~zapmask;
2832068SN/A            }});
2842068SN/A            0x31: zapnot({{
2852068SN/A                uint64_t zapmask = 0;
2862068SN/A                for (int i = 0; i < 8; ++i) {
2872068SN/A                    if (!Rb_or_imm<i:>)
2882068SN/A                        zapmask |= (mask(8) << (i * 8));
2892068SN/A                }
2902068SN/A                Rc = Ra & ~zapmask;
2912068SN/A            }});
2922068SN/A        }
2932068SN/A
2947799Sgblack@eecs.umich.edu        0x13: decode INTFUNC {  // integer multiplies
2952068SN/A            0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
2962068SN/A            0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
2972068SN/A            0x30: umulh({{
2982068SN/A                uint64_t hi, lo;
2992068SN/A                mul128(Ra, Rb_or_imm, hi, lo);
3002068SN/A                Rc = hi;
3012068SN/A            }}, IntMultOp);
3022068SN/A            0x40: mullv({{
3032068SN/A                // 32-bit multiply with trap on overflow
3047799Sgblack@eecs.umich.edu                int64_t Rax = Ra.sl;    // sign extended version of Ra.sl
3052068SN/A                int64_t Rbx = Rb_or_imm.sl;
3062068SN/A                int64_t tmp = Rax * Rbx;
3072068SN/A                // To avoid overflow, all the upper 32 bits must match
3082068SN/A                // the sign bit of the lower 32.  We code this as
3092068SN/A                // checking the upper 33 bits for all 0s or all 1s.
3102068SN/A                uint64_t sign_bits = tmp<63:31>;
3112068SN/A                if (sign_bits != 0 && sign_bits != mask(33))
3122147SN/A                    fault = new IntegerOverflowFault;
3132068SN/A                Rc.sl = tmp<31:0>;
3142068SN/A            }}, IntMultOp);
3152068SN/A            0x60: mulqv({{
3162068SN/A                // 64-bit multiply with trap on overflow
3172068SN/A                uint64_t hi, lo;
3182068SN/A                mul128(Ra, Rb_or_imm, hi, lo);
3192068SN/A                // all the upper 64 bits must match the sign bit of
3202068SN/A                // the lower 64
3212068SN/A                if (!((hi == 0 && lo<63:> == 0) ||
3222068SN/A                      (hi == mask(64) && lo<63:> == 1)))
3232147SN/A                    fault = new IntegerOverflowFault;
3242068SN/A                Rc = lo;
3252068SN/A            }}, IntMultOp);
3262068SN/A        }
3272068SN/A
3282068SN/A        0x1c: decode INTFUNC {
3292068SN/A            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
3302068SN/A            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
3316804Ssroy@cse.usf.edu
3326804Ssroy@cse.usf.edu            0x30: ctpop({{
3336804Ssroy@cse.usf.edu                             uint64_t count = 0;
3346804Ssroy@cse.usf.edu                             for (int i = 0; Rb<63:i>; ++i) {
3356804Ssroy@cse.usf.edu                                 if (Rb<i:i> == 0x1)
3366804Ssroy@cse.usf.edu                                     ++count;
3376804Ssroy@cse.usf.edu                             }
3386804Ssroy@cse.usf.edu                             Rc = count;
3396804Ssroy@cse.usf.edu                           }}, IntAluOp);
3406804Ssroy@cse.usf.edu
3416804Ssroy@cse.usf.edu            0x31: perr({{
3426804Ssroy@cse.usf.edu                             uint64_t temp = 0;
3436804Ssroy@cse.usf.edu                             int hi = 7;
3446804Ssroy@cse.usf.edu                             int lo = 0;
3456804Ssroy@cse.usf.edu                             for (int i = 0; i < 8; ++i) {
3466804Ssroy@cse.usf.edu                                 uint8_t ra_ub = Ra.uq<hi:lo>;
3476804Ssroy@cse.usf.edu                                 uint8_t rb_ub = Rb.uq<hi:lo>;
3486804Ssroy@cse.usf.edu                                 temp += (ra_ub >= rb_ub) ? 
3496804Ssroy@cse.usf.edu                                         (ra_ub - rb_ub) : (rb_ub - ra_ub);
3506804Ssroy@cse.usf.edu                                 hi += 8;
3516804Ssroy@cse.usf.edu                                 lo += 8;
3526804Ssroy@cse.usf.edu                             }
3536804Ssroy@cse.usf.edu                             Rc = temp;
3546804Ssroy@cse.usf.edu                           }});
3556804Ssroy@cse.usf.edu
3562068SN/A            0x32: ctlz({{
3572068SN/A                             uint64_t count = 0;
3582068SN/A                             uint64_t temp = Rb;
3592068SN/A                             if (temp<63:32>) temp >>= 32; else count += 32;
3602068SN/A                             if (temp<31:16>) temp >>= 16; else count += 16;
3612068SN/A                             if (temp<15:8>) temp >>= 8; else count += 8;
3622068SN/A                             if (temp<7:4>) temp >>= 4; else count += 4;
3632068SN/A                             if (temp<3:2>) temp >>= 2; else count += 2;
3642068SN/A                             if (temp<1:1>) temp >>= 1; else count += 1;
3652068SN/A                             if ((temp<0:0>) != 0x1) count += 1;
3662068SN/A                             Rc = count;
3672068SN/A                           }}, IntAluOp);
3682068SN/A
3692068SN/A            0x33: cttz({{
3702068SN/A                             uint64_t count = 0;
3712068SN/A                             uint64_t temp = Rb;
3722068SN/A                             if (!(temp<31:0>)) { temp >>= 32; count += 32; }
3732068SN/A                             if (!(temp<15:0>)) { temp >>= 16; count += 16; }
3742068SN/A                             if (!(temp<7:0>)) { temp >>= 8; count += 8; }
3752068SN/A                             if (!(temp<3:0>)) { temp >>= 4; count += 4; }
3762068SN/A                             if (!(temp<1:0>)) { temp >>= 2; count += 2; }
3776804Ssroy@cse.usf.edu                             if (!(temp<0:0> & ULL(0x1))) { 
3786804Ssroy@cse.usf.edu                                 temp >>= 1; count += 1; 
3796804Ssroy@cse.usf.edu                             }
3802068SN/A                             if (!(temp<0:0> & ULL(0x1))) count += 1;
3812068SN/A                             Rc = count;
3822068SN/A                           }}, IntAluOp);
3832068SN/A
3846804Ssroy@cse.usf.edu
3856804Ssroy@cse.usf.edu            0x34: unpkbw({{ 
3866804Ssroy@cse.usf.edu                             Rc = (Rb.uq<7:0> 
3876804Ssroy@cse.usf.edu                                   | (Rb.uq<15:8> << 16) 
3886804Ssroy@cse.usf.edu                                   | (Rb.uq<23:16> << 32) 
3896804Ssroy@cse.usf.edu                                   | (Rb.uq<31:24> << 48)); 
3906804Ssroy@cse.usf.edu                           }}, IntAluOp);
3916804Ssroy@cse.usf.edu
3926804Ssroy@cse.usf.edu            0x35: unpkbl({{
3936804Ssroy@cse.usf.edu                             Rc = (Rb.uq<7:0> | (Rb.uq<15:8> << 32)); 
3946804Ssroy@cse.usf.edu                           }}, IntAluOp);
3956804Ssroy@cse.usf.edu
3966804Ssroy@cse.usf.edu            0x36: pkwb({{
3976804Ssroy@cse.usf.edu                             Rc = (Rb.uq<7:0> 
3986804Ssroy@cse.usf.edu                                   | (Rb.uq<23:16> << 8) 
3996804Ssroy@cse.usf.edu                                   | (Rb.uq<39:32> << 16) 
4006804Ssroy@cse.usf.edu                                   | (Rb.uq<55:48> << 24)); 
4016804Ssroy@cse.usf.edu                           }}, IntAluOp);
4026804Ssroy@cse.usf.edu
4036804Ssroy@cse.usf.edu            0x37: pklb({{
4046804Ssroy@cse.usf.edu                             Rc = (Rb.uq<7:0> | (Rb.uq<39:32> << 8)); 
4056804Ssroy@cse.usf.edu                           }}, IntAluOp);
4066804Ssroy@cse.usf.edu
4076804Ssroy@cse.usf.edu            0x38: minsb8({{
4086804Ssroy@cse.usf.edu                             uint64_t temp = 0;
4096804Ssroy@cse.usf.edu                             int hi = 63;
4106804Ssroy@cse.usf.edu                             int lo = 56;
4116804Ssroy@cse.usf.edu                             for (int i = 7; i >= 0; --i) {
4126804Ssroy@cse.usf.edu                                 int8_t ra_sb = Ra.uq<hi:lo>;
4136804Ssroy@cse.usf.edu                                 int8_t rb_sb = Rb.uq<hi:lo>;
4146804Ssroy@cse.usf.edu                                 temp = ((temp << 8) 
4156804Ssroy@cse.usf.edu                                         | ((ra_sb < rb_sb) ? Ra.uq<hi:lo>
4166804Ssroy@cse.usf.edu                                                          : Rb.uq<hi:lo>));
4176804Ssroy@cse.usf.edu                                 hi -= 8;
4186804Ssroy@cse.usf.edu                                 lo -= 8;
4196804Ssroy@cse.usf.edu                             }
4206804Ssroy@cse.usf.edu                             Rc = temp;
4216804Ssroy@cse.usf.edu                          }});
4226804Ssroy@cse.usf.edu
4236804Ssroy@cse.usf.edu            0x39: minsw4({{
4246804Ssroy@cse.usf.edu                             uint64_t temp = 0;
4256804Ssroy@cse.usf.edu                             int hi = 63;
4266804Ssroy@cse.usf.edu                             int lo = 48;
4276804Ssroy@cse.usf.edu                             for (int i = 3; i >= 0; --i) {
4286804Ssroy@cse.usf.edu                                 int16_t ra_sw = Ra.uq<hi:lo>;
4296804Ssroy@cse.usf.edu                                 int16_t rb_sw = Rb.uq<hi:lo>;
4306804Ssroy@cse.usf.edu                                 temp = ((temp << 16) 
4316804Ssroy@cse.usf.edu                                         | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
4326804Ssroy@cse.usf.edu                                                          : Rb.uq<hi:lo>));
4336804Ssroy@cse.usf.edu                                 hi -= 16;
4346804Ssroy@cse.usf.edu                                 lo -= 16;
4356804Ssroy@cse.usf.edu                             }
4366804Ssroy@cse.usf.edu                             Rc = temp;
4376804Ssroy@cse.usf.edu                          }});
4386804Ssroy@cse.usf.edu
4396804Ssroy@cse.usf.edu            0x3a: minub8({{
4406804Ssroy@cse.usf.edu                             uint64_t temp = 0;
4416804Ssroy@cse.usf.edu                             int hi = 63;
4426804Ssroy@cse.usf.edu                             int lo = 56;
4436804Ssroy@cse.usf.edu                             for (int i = 7; i >= 0; --i) {
4446804Ssroy@cse.usf.edu                                 uint8_t ra_ub = Ra.uq<hi:lo>;
4456804Ssroy@cse.usf.edu                                 uint8_t rb_ub = Rb.uq<hi:lo>;
4466804Ssroy@cse.usf.edu                                 temp = ((temp << 8) 
4476804Ssroy@cse.usf.edu                                         | ((ra_ub < rb_ub) ? Ra.uq<hi:lo>
4486804Ssroy@cse.usf.edu                                                          : Rb.uq<hi:lo>));
4496804Ssroy@cse.usf.edu                                 hi -= 8;
4506804Ssroy@cse.usf.edu                                 lo -= 8;
4516804Ssroy@cse.usf.edu                             }
4526804Ssroy@cse.usf.edu                             Rc = temp;
4536804Ssroy@cse.usf.edu                          }});
4546804Ssroy@cse.usf.edu
4556804Ssroy@cse.usf.edu            0x3b: minuw4({{
4566804Ssroy@cse.usf.edu                             uint64_t temp = 0;
4576804Ssroy@cse.usf.edu                             int hi = 63;
4586804Ssroy@cse.usf.edu                             int lo = 48;
4596804Ssroy@cse.usf.edu                             for (int i = 3; i >= 0; --i) {
4606804Ssroy@cse.usf.edu                                 uint16_t ra_sw = Ra.uq<hi:lo>;
4616804Ssroy@cse.usf.edu                                 uint16_t rb_sw = Rb.uq<hi:lo>;
4626804Ssroy@cse.usf.edu                                 temp = ((temp << 16) 
4636804Ssroy@cse.usf.edu                                         | ((ra_sw < rb_sw) ? Ra.uq<hi:lo>
4646804Ssroy@cse.usf.edu                                                          : Rb.uq<hi:lo>));
4656804Ssroy@cse.usf.edu                                 hi -= 16;
4666804Ssroy@cse.usf.edu                                 lo -= 16;
4676804Ssroy@cse.usf.edu                             }
4686804Ssroy@cse.usf.edu                             Rc = temp;
4696804Ssroy@cse.usf.edu                          }});
4706804Ssroy@cse.usf.edu
4716804Ssroy@cse.usf.edu            0x3c: maxub8({{
4726804Ssroy@cse.usf.edu                             uint64_t temp = 0;
4736804Ssroy@cse.usf.edu                             int hi = 63;
4746804Ssroy@cse.usf.edu                             int lo = 56;
4756804Ssroy@cse.usf.edu                             for (int i = 7; i >= 0; --i) {
4766804Ssroy@cse.usf.edu                                 uint8_t ra_ub = Ra.uq<hi:lo>;
4776804Ssroy@cse.usf.edu                                 uint8_t rb_ub = Rb.uq<hi:lo>;
4786804Ssroy@cse.usf.edu                                 temp = ((temp << 8) 
4796804Ssroy@cse.usf.edu                                         | ((ra_ub > rb_ub) ? Ra.uq<hi:lo>
4806804Ssroy@cse.usf.edu                                                          : Rb.uq<hi:lo>));
4816804Ssroy@cse.usf.edu                                 hi -= 8;
4826804Ssroy@cse.usf.edu                                 lo -= 8;
4836804Ssroy@cse.usf.edu                             }
4846804Ssroy@cse.usf.edu                             Rc = temp;
4856804Ssroy@cse.usf.edu                          }});
4866804Ssroy@cse.usf.edu
4876804Ssroy@cse.usf.edu            0x3d: maxuw4({{
4886804Ssroy@cse.usf.edu                             uint64_t temp = 0;
4896804Ssroy@cse.usf.edu                             int hi = 63;
4906804Ssroy@cse.usf.edu                             int lo = 48;
4916804Ssroy@cse.usf.edu                             for (int i = 3; i >= 0; --i) {
4926804Ssroy@cse.usf.edu                                 uint16_t ra_uw = Ra.uq<hi:lo>;
4936804Ssroy@cse.usf.edu                                 uint16_t rb_uw = Rb.uq<hi:lo>;
4946804Ssroy@cse.usf.edu                                 temp = ((temp << 16) 
4956804Ssroy@cse.usf.edu                                         | ((ra_uw > rb_uw) ? Ra.uq<hi:lo>
4966804Ssroy@cse.usf.edu                                                          : Rb.uq<hi:lo>));
4976804Ssroy@cse.usf.edu                                 hi -= 16;
4986804Ssroy@cse.usf.edu                                 lo -= 16;
4996804Ssroy@cse.usf.edu                             }
5006804Ssroy@cse.usf.edu                             Rc = temp;
5016804Ssroy@cse.usf.edu                          }});
5026804Ssroy@cse.usf.edu
5036804Ssroy@cse.usf.edu            0x3e: maxsb8({{
5046804Ssroy@cse.usf.edu                             uint64_t temp = 0;
5056804Ssroy@cse.usf.edu                             int hi = 63;
5066804Ssroy@cse.usf.edu                             int lo = 56;
5076804Ssroy@cse.usf.edu                             for (int i = 7; i >= 0; --i) {
5086804Ssroy@cse.usf.edu                                 int8_t ra_sb = Ra.uq<hi:lo>;
5096804Ssroy@cse.usf.edu                                 int8_t rb_sb = Rb.uq<hi:lo>;
5106804Ssroy@cse.usf.edu                                 temp = ((temp << 8) 
5116804Ssroy@cse.usf.edu                                         | ((ra_sb > rb_sb) ? Ra.uq<hi:lo>
5126804Ssroy@cse.usf.edu                                                          : Rb.uq<hi:lo>));
5136804Ssroy@cse.usf.edu                                 hi -= 8;
5146804Ssroy@cse.usf.edu                                 lo -= 8;
5156804Ssroy@cse.usf.edu                             }
5166804Ssroy@cse.usf.edu                             Rc = temp;
5176804Ssroy@cse.usf.edu                          }});
5186804Ssroy@cse.usf.edu
5196804Ssroy@cse.usf.edu            0x3f: maxsw4({{
5206804Ssroy@cse.usf.edu                             uint64_t temp = 0;
5216804Ssroy@cse.usf.edu                             int hi = 63;
5226804Ssroy@cse.usf.edu                             int lo = 48;
5236804Ssroy@cse.usf.edu                             for (int i = 3; i >= 0; --i) {
5246804Ssroy@cse.usf.edu                                 int16_t ra_sw = Ra.uq<hi:lo>;
5256804Ssroy@cse.usf.edu                                 int16_t rb_sw = Rb.uq<hi:lo>;
5266804Ssroy@cse.usf.edu                                 temp = ((temp << 16) 
5276804Ssroy@cse.usf.edu                                         | ((ra_sw > rb_sw) ? Ra.uq<hi:lo>
5286804Ssroy@cse.usf.edu                                                          : Rb.uq<hi:lo>));
5296804Ssroy@cse.usf.edu                                 hi -= 16;
5306804Ssroy@cse.usf.edu                                 lo -= 16;
5316804Ssroy@cse.usf.edu                             }
5326804Ssroy@cse.usf.edu                             Rc = temp;
5336804Ssroy@cse.usf.edu                          }});
5342068SN/A
5352068SN/A            format BasicOperateWithNopCheck {
5362068SN/A                0x70: decode RB {
5372068SN/A                    31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
5382068SN/A                }
5392068SN/A                0x78: decode RB {
5402068SN/A                    31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
5412068SN/A                              FloatCvtOp);
5422068SN/A                }
5432068SN/A            }
5442068SN/A        }
5452068SN/A    }
5462068SN/A
5472068SN/A    // Conditional branches.
5482068SN/A    format CondBranch {
5492068SN/A        0x39: beq({{ cond = (Ra == 0); }});
5502068SN/A        0x3d: bne({{ cond = (Ra != 0); }});
5512068SN/A        0x3e: bge({{ cond = (Ra.sq >= 0); }});
5522068SN/A        0x3f: bgt({{ cond = (Ra.sq >  0); }});
5532068SN/A        0x3b: ble({{ cond = (Ra.sq <= 0); }});
5542068SN/A        0x3a: blt({{ cond = (Ra.sq < 0); }});
5552068SN/A        0x38: blbc({{ cond = ((Ra & 1) == 0); }});
5562068SN/A        0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
5572068SN/A
5582068SN/A        0x31: fbeq({{ cond = (Fa == 0); }});
5592068SN/A        0x35: fbne({{ cond = (Fa != 0); }});
5602068SN/A        0x36: fbge({{ cond = (Fa >= 0); }});
5612068SN/A        0x37: fbgt({{ cond = (Fa >  0); }});
5622068SN/A        0x33: fble({{ cond = (Fa <= 0); }});
5632068SN/A        0x32: fblt({{ cond = (Fa < 0); }});
5642068SN/A    }
5652068SN/A
5662068SN/A    // unconditional branches
5672068SN/A    format UncondBranch {
5682068SN/A        0x30: br();
5692068SN/A        0x34: bsr(IsCall);
5702068SN/A    }
5712068SN/A
5722068SN/A    // indirect branches
5732068SN/A    0x1a: decode JMPFUNC {
5742068SN/A        format Jump {
5752068SN/A            0: jmp();
5762068SN/A            1: jsr(IsCall);
5772068SN/A            2: ret(IsReturn);
5782068SN/A            3: jsr_coroutine(IsCall, IsReturn);
5792068SN/A        }
5802068SN/A    }
5812068SN/A
5822068SN/A    // Square root and integer-to-FP moves
5832068SN/A    0x14: decode FP_SHORTFUNC {
5842068SN/A        // Integer to FP register moves must have RB == 31
5852068SN/A        0x4: decode RB {
5862068SN/A            31: decode FP_FULLFUNC {
5872068SN/A                format BasicOperateWithNopCheck {
5882068SN/A                    0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
5892068SN/A                    0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
5907799Sgblack@eecs.umich.edu                    0x014: FailUnimpl::itoff(); // VAX-format conversion
5912068SN/A                }
5922068SN/A            }
5932068SN/A        }
5942068SN/A
5952068SN/A        // Square root instructions must have FA == 31
5962068SN/A        0xb: decode FA {
5972068SN/A            31: decode FP_TYPEFUNC {
5982068SN/A                format FloatingPointOperate {
5992068SN/A#if SS_COMPATIBLE_FP
6002068SN/A                    0x0b: sqrts({{
6012068SN/A                        if (Fb < 0.0)
6022147SN/A                            fault = new ArithmeticFault;
6032068SN/A                        Fc = sqrt(Fb);
6042068SN/A                    }}, FloatSqrtOp);
6052068SN/A#else
6062068SN/A                    0x0b: sqrts({{
6072068SN/A                        if (Fb.sf < 0.0)
6082147SN/A                            fault = new ArithmeticFault;
6092068SN/A                        Fc.sf = sqrt(Fb.sf);
6102068SN/A                    }}, FloatSqrtOp);
6112068SN/A#endif
6122068SN/A                    0x2b: sqrtt({{
6132068SN/A                        if (Fb < 0.0)
6142147SN/A                            fault = new ArithmeticFault;
6152068SN/A                        Fc = sqrt(Fb);
6162068SN/A                    }}, FloatSqrtOp);
6172068SN/A                }
6182068SN/A            }
6192068SN/A        }
6202068SN/A
6212068SN/A        // VAX-format sqrtf and sqrtg are not implemented
6222068SN/A        0xa: FailUnimpl::sqrtfg();
6232068SN/A    }
6242068SN/A
6252068SN/A    // IEEE floating point
6262068SN/A    0x16: decode FP_SHORTFUNC_TOP2 {
6272068SN/A        // The top two bits of the short function code break this
6282068SN/A        // space into four groups: binary ops, compares, reserved, and
6292068SN/A        // conversions.  See Table 4-12 of AHB.  There are different
6302068SN/A        // special cases in these different groups, so we decode on
6312068SN/A        // these top two bits first just to select a decode strategy.
6322068SN/A        // Most of these instructions may have various trapping and
6332068SN/A        // rounding mode flags set; these are decoded in the
6342068SN/A        // FloatingPointDecode template used by the
6352068SN/A        // FloatingPointOperate format.
6362068SN/A
6372068SN/A        // add/sub/mul/div: just decode on the short function code
6382068SN/A        // and source type.  All valid trapping and rounding modes apply.
6392068SN/A        0: decode FP_TRAPMODE {
6402068SN/A            // check for valid trapping modes here
6412068SN/A            0,1,5,7: decode FP_TYPEFUNC {
6422068SN/A                   format FloatingPointOperate {
6432068SN/A#if SS_COMPATIBLE_FP
6442068SN/A                       0x00: adds({{ Fc = Fa + Fb; }});
6452068SN/A                       0x01: subs({{ Fc = Fa - Fb; }});
6462068SN/A                       0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
6472068SN/A                       0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
6482068SN/A#else
6492068SN/A                       0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
6502068SN/A                       0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
6512068SN/A                       0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
6522068SN/A                       0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
6532068SN/A#endif
6542068SN/A
6552068SN/A                       0x20: addt({{ Fc = Fa + Fb; }});
6562068SN/A                       0x21: subt({{ Fc = Fa - Fb; }});
6572068SN/A                       0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
6582068SN/A                       0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
6592068SN/A                   }
6602068SN/A             }
6612068SN/A        }
6622068SN/A
6632068SN/A        // Floating-point compare instructions must have the default
6642068SN/A        // rounding mode, and may use the default trapping mode or
6652068SN/A        // /SU.  Both trapping modes are treated the same by M5; the
6662068SN/A        // only difference on the real hardware (as far a I can tell)
6672068SN/A        // is that without /SU you'd get an imprecise trap if you
6682068SN/A        // tried to compare a NaN with something else (instead of an
6692068SN/A        // "unordered" result).
6702068SN/A        1: decode FP_FULLFUNC {
6712068SN/A            format BasicOperateWithNopCheck {
6722068SN/A                0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
6732068SN/A                                     FloatCmpOp);
6742068SN/A                0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
6752068SN/A                                     FloatCmpOp);
6762068SN/A                0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
6772068SN/A                                     FloatCmpOp);
6782068SN/A                0x0a4, 0x5a4: cmptun({{ // unordered
6792068SN/A                    Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
6802068SN/A                }}, FloatCmpOp);
6812068SN/A            }
6822068SN/A        }
6832068SN/A
6842068SN/A        // The FP-to-integer and integer-to-FP conversion insts
6852068SN/A        // require that FA be 31.
6862068SN/A        3: decode FA {
6872068SN/A            31: decode FP_TYPEFUNC {
6882068SN/A                format FloatingPointOperate {
6892068SN/A                    0x2f: decode FP_ROUNDMODE {
6902068SN/A                        format FPFixedRounding {
6912068SN/A                            // "chopped" i.e. round toward zero
6922068SN/A                            0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
6932068SN/A                                     Chopped);
6942068SN/A                            // round to minus infinity
6952068SN/A                            1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
6962068SN/A                                     MinusInfinity);
6972068SN/A                        }
6982068SN/A                      default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
6992068SN/A                    }
7002068SN/A
7012068SN/A                    // The cvtts opcode is overloaded to be cvtst if the trap
7022068SN/A                    // mode is 2 or 6 (which are not valid otherwise)
7032068SN/A                    0x2c: decode FP_FULLFUNC {
7042068SN/A                        format BasicOperateWithNopCheck {
7052068SN/A                            // trap on denorm version "cvtst/s" is
7062068SN/A                            // simulated same as cvtst
7072068SN/A                            0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
7082068SN/A                        }
7092068SN/A                      default: cvtts({{ Fc.sf = Fb; }});
7102068SN/A                    }
7112068SN/A
7122068SN/A                    // The trapping mode for integer-to-FP conversions
7132068SN/A                    // must be /SUI or nothing; /U and /SU are not
7142068SN/A                    // allowed.  The full set of rounding modes are
7152068SN/A                    // supported though.
7162068SN/A                    0x3c: decode FP_TRAPMODE {
7172068SN/A                        0,7: cvtqs({{ Fc.sf = Fb.sq; }});
7182068SN/A                    }
7192068SN/A                    0x3e: decode FP_TRAPMODE {
7202068SN/A                        0,7: cvtqt({{ Fc    = Fb.sq; }});
7212068SN/A                    }
7222068SN/A                }
7232068SN/A            }
7242068SN/A        }
7252068SN/A    }
7262068SN/A
7272068SN/A    // misc FP operate
7282068SN/A    0x17: decode FP_FULLFUNC {
7292068SN/A        format BasicOperateWithNopCheck {
7302068SN/A            0x010: cvtlq({{
7312068SN/A                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
7322068SN/A            }});
7332068SN/A            0x030: cvtql({{
7342068SN/A                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
7352068SN/A            }});
7362068SN/A
7372068SN/A            // We treat the precise & imprecise trapping versions of
7382068SN/A            // cvtql identically.
7392068SN/A            0x130, 0x530: cvtqlv({{
7402068SN/A                // To avoid overflow, all the upper 32 bits must match
7412068SN/A                // the sign bit of the lower 32.  We code this as
7422068SN/A                // checking the upper 33 bits for all 0s or all 1s.
7432068SN/A                uint64_t sign_bits = Fb.uq<63:31>;
7442068SN/A                if (sign_bits != 0 && sign_bits != mask(33))
7452147SN/A                    fault = new IntegerOverflowFault;
7462068SN/A                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
7472068SN/A            }});
7482068SN/A
7492068SN/A            0x020: cpys({{  // copy sign
7502068SN/A                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
7512068SN/A            }});
7522068SN/A            0x021: cpysn({{ // copy sign negated
7532068SN/A                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
7542068SN/A            }});
7552068SN/A            0x022: cpyse({{ // copy sign and exponent
7562068SN/A                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
7572068SN/A            }});
7582068SN/A
7592068SN/A            0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
7602068SN/A            0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
7612068SN/A            0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
7622068SN/A            0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
7632068SN/A            0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
7642068SN/A            0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
7652068SN/A
7662336SN/A            0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
7672336SN/A            0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
7682068SN/A        }
7692068SN/A    }
7702068SN/A
7712068SN/A    // miscellaneous mem-format ops
7722068SN/A    0x18: decode MEMFUNC {
7732068SN/A        format WarnUnimpl {
7742068SN/A            0x8000: fetch();
7752068SN/A            0xa000: fetch_m();
7762068SN/A            0xe800: ecb();
7772068SN/A        }
7782068SN/A
7792068SN/A        format MiscPrefetch {
7802068SN/A            0xf800: wh64({{ EA = Rb & ~ULL(63); }},
7817725SAli.Saidi@ARM.com                         {{ ; }},
7827725SAli.Saidi@ARM.com                         mem_flags = PREFETCH);
7832068SN/A        }
7842068SN/A
7852068SN/A        format BasicOperate {
7862068SN/A            0xc000: rpcc({{
7872068SN/A#if FULL_SYSTEM
7882068SN/A        /* Rb is a fake dependency so here is a fun way to get
7892068SN/A         * the parser to understand that.
7902068SN/A         */
7915568Snate@binkert.org                Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
7922068SN/A
7932068SN/A#else
7947823Ssteve.reinhardt@amd.com                Ra = curTick();
7952068SN/A#endif
7962312SN/A            }}, IsUnverifiable);
7972068SN/A
7982068SN/A            // All of the barrier instructions below do nothing in
7992068SN/A            // their execute() methods (hence the empty code blocks).
8002068SN/A            // All of their functionality is hard-coded in the
8012068SN/A            // pipeline based on the flags IsSerializing,
8022068SN/A            // IsMemBarrier, and IsWriteBarrier.  In the current
8032068SN/A            // detailed CPU model, the execute() function only gets
8042068SN/A            // called at fetch, so there's no way to generate pipeline
8052068SN/A            // behavior at any other stage.  Once we go to an
8062068SN/A            // exec-in-exec CPU model we should be able to get rid of
8072068SN/A            // these flags and implement this behavior via the
8082068SN/A            // execute() methods.
8092068SN/A
8102068SN/A            // trapb is just a barrier on integer traps, where excb is
8112068SN/A            // a barrier on integer and FP traps.  "EXCB is thus a
8122068SN/A            // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
8132068SN/A            // them the same though.
8142292SN/A            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
8152292SN/A            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
8162068SN/A            0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
8172068SN/A            0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
8182068SN/A        }
8192068SN/A
8202068SN/A#if FULL_SYSTEM
8212068SN/A        format BasicOperate {
8222068SN/A            0xe000: rc({{
8233454Sgblack@eecs.umich.edu                Ra = IntrFlag;
8243454Sgblack@eecs.umich.edu                IntrFlag = 0;
8252704Sktlim@umich.edu            }}, IsNonSpeculative, IsUnverifiable);
8262068SN/A            0xf000: rs({{
8273454Sgblack@eecs.umich.edu                Ra = IntrFlag;
8283454Sgblack@eecs.umich.edu                IntrFlag = 1;
8292704Sktlim@umich.edu            }}, IsNonSpeculative, IsUnverifiable);
8302068SN/A        }
8312068SN/A#else
8322068SN/A        format FailUnimpl {
8332068SN/A            0xe000: rc();
8342068SN/A            0xf000: rs();
8352068SN/A        }
8362068SN/A#endif
8372068SN/A    }
8382068SN/A
8392068SN/A#if FULL_SYSTEM
8402068SN/A    0x00: CallPal::call_pal({{
8412068SN/A        if (!palValid ||
8422068SN/A            (palPriv
8435568Snate@binkert.org             && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
8442068SN/A            // invalid pal function code, or attempt to do privileged
8452068SN/A            // PAL call in non-kernel mode
8462147SN/A            fault = new UnimplementedOpcodeFault;
8477720Sgblack@eecs.umich.edu        } else {
8482068SN/A            // check to see if simulator wants to do something special
8492068SN/A            // on this PAL call (including maybe suppress it)
8505702Ssaidi@eecs.umich.edu            bool dopal = xc->simPalCheck(palFunc);
8512068SN/A
8522068SN/A            if (dopal) {
8537794Sgblack@eecs.umich.edu                xc->setMiscReg(IPR_EXC_ADDR, NPC);
8547794Sgblack@eecs.umich.edu                NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
8552068SN/A            }
8562068SN/A        }
8572068SN/A    }}, IsNonSpeculative);
8582068SN/A#else
8592068SN/A    0x00: decode PALFUNC {
8602068SN/A        format EmulatedCallPal {
8612068SN/A            0x00: halt ({{
8623144Shsul@eecs.umich.edu                exitSimLoop("halt instruction encountered");
8632068SN/A            }}, IsNonSpeculative);
8642068SN/A            0x83: callsys({{
8652562SN/A                xc->syscall(R0);
8664828Sgblack@eecs.umich.edu            }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
8672068SN/A            // Read uniq reg into ABI return value register (r0)
8682336SN/A            0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
8692068SN/A            // Write uniq reg with value from ABI arg register (r16)
8702336SN/A            0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
8712068SN/A        }
8722068SN/A    }
8732068SN/A#endif
8742068SN/A
8752068SN/A#if FULL_SYSTEM
8762227SN/A    0x1b: decode PALMODE {
8772227SN/A        0: OpcdecFault::hw_st_quad();
8782227SN/A        1: decode HW_LDST_QUAD {
8792227SN/A            format HwLoad {
8804036Sktlim@umich.edu                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
8814036Sktlim@umich.edu                         L, IsSerializing, IsSerializeBefore);
8824036Sktlim@umich.edu                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
8834036Sktlim@umich.edu                         Q, IsSerializing, IsSerializeBefore);
8842227SN/A            }
8852068SN/A        }
8862069SN/A    }
8872068SN/A
8882227SN/A    0x1f: decode PALMODE {
8892227SN/A        0: OpcdecFault::hw_st_cond();
8902227SN/A        format HwStore {
8912227SN/A            1: decode HW_LDST_COND {
8922227SN/A                0: decode HW_LDST_QUAD {
8932227SN/A                    0: hw_st({{ EA = (Rb + disp) & ~3; }},
8944036Sktlim@umich.edu                {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
8952227SN/A                    1: hw_st({{ EA = (Rb + disp) & ~7; }},
8964036Sktlim@umich.edu                {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
8972227SN/A                }
8982227SN/A
8992227SN/A                1: FailUnimpl::hw_st_cond();
9002068SN/A            }
9012068SN/A        }
9022068SN/A    }
9032068SN/A
9042227SN/A    0x19: decode PALMODE {
9052227SN/A        0: OpcdecFault::hw_mfpr();
9062227SN/A        format HwMoveIPR {
9072227SN/A            1: hw_mfpr({{
9083469Sgblack@eecs.umich.edu                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
9093464Sgblack@eecs.umich.edu                        IprToMiscRegIndex[ipr_index] : -1;
9103464Sgblack@eecs.umich.edu                if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
9113466Sgblack@eecs.umich.edu                    miscRegIndex >= NumInternalProcRegs)
9123457Sgblack@eecs.umich.edu                        fault = new UnimplementedOpcodeFault;
9133457Sgblack@eecs.umich.edu                else
9144172Ssaidi@eecs.umich.edu                    Ra = xc->readMiscReg(miscRegIndex);
9152336SN/A            }}, IsIprAccess);
9162227SN/A        }
9172227SN/A    }
9182227SN/A
9192227SN/A    0x1d: decode PALMODE {
9202227SN/A        0: OpcdecFault::hw_mtpr();
9212227SN/A        format HwMoveIPR {
9222227SN/A            1: hw_mtpr({{
9233469Sgblack@eecs.umich.edu                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
9243464Sgblack@eecs.umich.edu                        IprToMiscRegIndex[ipr_index] : -1;
9253467Sgblack@eecs.umich.edu                if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
9263466Sgblack@eecs.umich.edu                    miscRegIndex >= NumInternalProcRegs)
9273457Sgblack@eecs.umich.edu                        fault = new UnimplementedOpcodeFault;
9283457Sgblack@eecs.umich.edu                else
9294172Ssaidi@eecs.umich.edu                    xc->setMiscReg(miscRegIndex, Ra);
9302068SN/A                if (traceData) { traceData->setData(Ra); }
9312336SN/A            }}, IsIprAccess);
9322227SN/A        }
9332068SN/A    }
9342068SN/A
9355780Ssteve.reinhardt@amd.com  0x1e: decode PALMODE {
9365780Ssteve.reinhardt@amd.com      0: OpcdecFault::hw_rei();
9375780Ssteve.reinhardt@amd.com        format BasicOperate {
9388457Sksewell@umich.edu          1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
9395780Ssteve.reinhardt@amd.com        }
9405780Ssteve.reinhardt@amd.com    }
9415780Ssteve.reinhardt@amd.com
9425780Ssteve.reinhardt@amd.com#endif
9435780Ssteve.reinhardt@amd.com
9442068SN/A    format BasicOperate {
9452068SN/A        // M5 special opcodes use the reserved 0x01 opcode space
9462068SN/A        0x01: decode M5FUNC {
9475780Ssteve.reinhardt@amd.com#if FULL_SYSTEM
9482068SN/A            0x00: arm({{
9494090Ssaidi@eecs.umich.edu                PseudoInst::arm(xc->tcBase());
9502068SN/A            }}, IsNonSpeculative);
9512068SN/A            0x01: quiesce({{
9524090Ssaidi@eecs.umich.edu                PseudoInst::quiesce(xc->tcBase());
9532292SN/A            }}, IsNonSpeculative, IsQuiesce);
9542188SN/A            0x02: quiesceNs({{
9554090Ssaidi@eecs.umich.edu                PseudoInst::quiesceNs(xc->tcBase(), R16);
9562292SN/A            }}, IsNonSpeculative, IsQuiesce);
9572188SN/A            0x03: quiesceCycles({{
9584090Ssaidi@eecs.umich.edu                PseudoInst::quiesceCycles(xc->tcBase(), R16);
9592355SN/A            }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
9602188SN/A            0x04: quiesceTime({{
9614090Ssaidi@eecs.umich.edu                R0 = PseudoInst::quiesceTime(xc->tcBase());
9622355SN/A            }}, IsNonSpeculative, IsUnverifiable);
9635780Ssteve.reinhardt@amd.com#endif
9645741Snate@binkert.org            0x07: rpns({{
9655741Snate@binkert.org                R0 = PseudoInst::rpns(xc->tcBase());
9665741Snate@binkert.org            }}, IsNonSpeculative, IsUnverifiable);
9675808Snate@binkert.org            0x09: wakeCPU({{
9685808Snate@binkert.org                PseudoInst::wakeCPU(xc->tcBase(), R16);
9695808Snate@binkert.org            }}, IsNonSpeculative, IsUnverifiable);
9705505Snate@binkert.org            0x10: deprecated_ivlb({{
9715505Snate@binkert.org                warn_once("Obsolete M5 ivlb instruction encountered.\n");
9723680Sstever@eecs.umich.edu            }});
9735505Snate@binkert.org            0x11: deprecated_ivle({{
9745505Snate@binkert.org                warn_once("Obsolete M5 ivlb instruction encountered.\n");
9753680Sstever@eecs.umich.edu            }});
9765505Snate@binkert.org            0x20: deprecated_exit ({{
9775505Snate@binkert.org                warn_once("deprecated M5 exit instruction encountered.\n");
9785505Snate@binkert.org                PseudoInst::m5exit(xc->tcBase(), 0);
9792068SN/A            }}, No_OpClass, IsNonSpeculative);
9802068SN/A            0x21: m5exit({{
9814090Ssaidi@eecs.umich.edu                PseudoInst::m5exit(xc->tcBase(), R16);
9822068SN/A            }}, No_OpClass, IsNonSpeculative);
9835780Ssteve.reinhardt@amd.com#if FULL_SYSTEM
9842358SN/A            0x31: loadsymbol({{
9854090Ssaidi@eecs.umich.edu                PseudoInst::loadsymbol(xc->tcBase());
9862358SN/A            }}, No_OpClass, IsNonSpeculative);
9875505Snate@binkert.org            0x30: initparam({{
9888555Sgblack@eecs.umich.edu                Ra = PseudoInst::initParam(xc->tcBase());
9895505Snate@binkert.org            }});
9905780Ssteve.reinhardt@amd.com#endif
9912068SN/A            0x40: resetstats({{
9924090Ssaidi@eecs.umich.edu                PseudoInst::resetstats(xc->tcBase(), R16, R17);
9932068SN/A            }}, IsNonSpeculative);
9942068SN/A            0x41: dumpstats({{
9954090Ssaidi@eecs.umich.edu                PseudoInst::dumpstats(xc->tcBase(), R16, R17);
9962068SN/A            }}, IsNonSpeculative);
9972068SN/A            0x42: dumpresetstats({{
9984090Ssaidi@eecs.umich.edu                PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
9992068SN/A            }}, IsNonSpeculative);
10002068SN/A            0x43: m5checkpoint({{
10014090Ssaidi@eecs.umich.edu                PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
10022068SN/A            }}, IsNonSpeculative);
10035780Ssteve.reinhardt@amd.com#if FULL_SYSTEM
10042068SN/A            0x50: m5readfile({{
10054090Ssaidi@eecs.umich.edu                R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
10062068SN/A            }}, IsNonSpeculative);
10075780Ssteve.reinhardt@amd.com#endif
10082068SN/A            0x51: m5break({{
10094090Ssaidi@eecs.umich.edu                PseudoInst::debugbreak(xc->tcBase());
10102068SN/A            }}, IsNonSpeculative);
10112068SN/A            0x52: m5switchcpu({{
10124090Ssaidi@eecs.umich.edu                PseudoInst::switchcpu(xc->tcBase());
10132068SN/A            }}, IsNonSpeculative);
10145780Ssteve.reinhardt@amd.com#if FULL_SYSTEM
10152068SN/A            0x53: m5addsymbol({{
10164090Ssaidi@eecs.umich.edu                PseudoInst::addsymbol(xc->tcBase(), R16, R17);
10172068SN/A            }}, IsNonSpeculative);
10185780Ssteve.reinhardt@amd.com#endif
10192188SN/A            0x54: m5panic({{
10207794Sgblack@eecs.umich.edu                panic("M5 panic instruction called at pc = %#x.", PC);
10212188SN/A            }}, IsNonSpeculative);
10225952Ssaidi@eecs.umich.edu#define  CPANN(lbl) CPA::cpa()->lbl(xc->tcBase())
10235952Ssaidi@eecs.umich.edu            0x55: decode RA {
10245952Ssaidi@eecs.umich.edu                0x00: m5a_old({{
10257794Sgblack@eecs.umich.edu                    panic("Deprecated M5 annotate instruction executed "
10267794Sgblack@eecs.umich.edu                          "at pc = %#x\n", PC);
10275952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10285952Ssaidi@eecs.umich.edu                0x01: m5a_bsm({{
10295952Ssaidi@eecs.umich.edu                    CPANN(swSmBegin);
10305952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10315952Ssaidi@eecs.umich.edu                0x02: m5a_esm({{
10325952Ssaidi@eecs.umich.edu                    CPANN(swSmEnd);
10335952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10345952Ssaidi@eecs.umich.edu                0x03: m5a_begin({{
10355952Ssaidi@eecs.umich.edu                    CPANN(swExplictBegin);
10365952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10375952Ssaidi@eecs.umich.edu                0x04: m5a_end({{
10385952Ssaidi@eecs.umich.edu                    CPANN(swEnd);
10395952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10405952Ssaidi@eecs.umich.edu                0x06: m5a_q({{
10415952Ssaidi@eecs.umich.edu                    CPANN(swQ);
10425952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10435952Ssaidi@eecs.umich.edu                0x07: m5a_dq({{
10445952Ssaidi@eecs.umich.edu                    CPANN(swDq);
10455952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10465952Ssaidi@eecs.umich.edu                0x08: m5a_wf({{
10475952Ssaidi@eecs.umich.edu                    CPANN(swWf);
10485952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10495952Ssaidi@eecs.umich.edu                0x09: m5a_we({{
10505952Ssaidi@eecs.umich.edu                    CPANN(swWe);
10515952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10525952Ssaidi@eecs.umich.edu                0x0C: m5a_sq({{
10535952Ssaidi@eecs.umich.edu                    CPANN(swSq);
10545952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10555952Ssaidi@eecs.umich.edu                0x0D: m5a_aq({{
10565952Ssaidi@eecs.umich.edu                    CPANN(swAq);
10575952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10585952Ssaidi@eecs.umich.edu                0x0E: m5a_pq({{
10595952Ssaidi@eecs.umich.edu                    CPANN(swPq);
10605952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10615952Ssaidi@eecs.umich.edu                0x0F: m5a_l({{
10625952Ssaidi@eecs.umich.edu                    CPANN(swLink);
10635952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10645952Ssaidi@eecs.umich.edu                0x10: m5a_identify({{
10655952Ssaidi@eecs.umich.edu                    CPANN(swIdentify);
10665952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10675952Ssaidi@eecs.umich.edu                0x11: m5a_getid({{
10685952Ssaidi@eecs.umich.edu                    R0 = CPANN(swGetId);
10695952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10705952Ssaidi@eecs.umich.edu                0x13: m5a_scl({{
10715952Ssaidi@eecs.umich.edu                    CPANN(swSyscallLink);
10725952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10735952Ssaidi@eecs.umich.edu                0x14: m5a_rq({{
10745952Ssaidi@eecs.umich.edu                    CPANN(swRq);
10755952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
10765952Ssaidi@eecs.umich.edu            } // M5 Annotate Operations
10775952Ssaidi@eecs.umich.edu#undef CPANN
10785505Snate@binkert.org            0x56: m5reserved2({{
10795505Snate@binkert.org                warn("M5 reserved opcode ignored");
10805505Snate@binkert.org            }}, IsNonSpeculative);
10815505Snate@binkert.org            0x57: m5reserved3({{
10825505Snate@binkert.org                warn("M5 reserved opcode ignored");
10835505Snate@binkert.org            }}, IsNonSpeculative);
10845505Snate@binkert.org            0x58: m5reserved4({{
10855505Snate@binkert.org                warn("M5 reserved opcode ignored");
10865505Snate@binkert.org            }}, IsNonSpeculative);
10875505Snate@binkert.org            0x59: m5reserved5({{
10885505Snate@binkert.org                warn("M5 reserved opcode ignored");
10893089Ssaidi@eecs.umich.edu            }}, IsNonSpeculative);
10902068SN/A        }
10912068SN/A    }
10922068SN/A}
1093