decoder.isa revision 6076
12068SN/A// -*- mode:c++ -*-
22068SN/A
32188SN/A// Copyright (c) 2003-2006 The Regents of The University of Michigan
42068SN/A// All rights reserved.
52068SN/A//
62068SN/A// Redistribution and use in source and binary forms, with or without
72068SN/A// modification, are permitted provided that the following conditions are
82068SN/A// met: redistributions of source code must retain the above copyright
92068SN/A// notice, this list of conditions and the following disclaimer;
102068SN/A// redistributions in binary form must reproduce the above copyright
112068SN/A// notice, this list of conditions and the following disclaimer in the
122068SN/A// documentation and/or other materials provided with the distribution;
132068SN/A// neither the name of the copyright holders nor the names of its
142068SN/A// contributors may be used to endorse or promote products derived from
152068SN/A// this software without specific prior written permission.
162068SN/A//
172068SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182068SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192068SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202068SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212068SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222068SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232068SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242068SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252068SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262068SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272068SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu//
292665Ssaidi@eecs.umich.edu// Authors: Steve Reinhardt
302068SN/A
312649Ssaidi@eecs.umich.edu////////////////////////////////////////////////////////////////////
322649Ssaidi@eecs.umich.edu//
332649Ssaidi@eecs.umich.edu// The actual decoder specification
342649Ssaidi@eecs.umich.edu//
352649Ssaidi@eecs.umich.edu
362068SN/Adecode OPCODE default Unknown::unknown() {
372068SN/A
382068SN/A    format LoadAddress {
392068SN/A        0x08: lda({{ Ra = Rb + disp; }});
402068SN/A        0x09: ldah({{ Ra = Rb + (disp << 16); }});
412068SN/A    }
422068SN/A
432068SN/A    format LoadOrNop {
442075SN/A        0x0a: ldbu({{ Ra.uq = Mem.ub; }});
452075SN/A        0x0c: ldwu({{ Ra.uq = Mem.uw; }});
462075SN/A        0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
472075SN/A        0x23: ldt({{ Fa = Mem.df; }});
486076Sgblack@eecs.umich.edu        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
496076Sgblack@eecs.umich.edu        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
502735Sktlim@umich.edu#ifdef USE_COPY
512069SN/A        0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
522069SN/A                                      {{ fault = xc->copySrcTranslate(EA); }},
532075SN/A                                      inst_flags = [IsMemRef, IsLoad, IsCopy]);
542735Sktlim@umich.edu#endif
552068SN/A    }
562068SN/A
572068SN/A    format LoadOrPrefetch {
582075SN/A        0x28: ldl({{ Ra.sl = Mem.sl; }});
592075SN/A        0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
602068SN/A        // IsFloating flag on lds gets the prefetch to disassemble
612068SN/A        // using f31 instead of r31... funcitonally it's unnecessary
622075SN/A        0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
632075SN/A                  pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
642068SN/A    }
652068SN/A
662068SN/A    format Store {
672075SN/A        0x0e: stb({{ Mem.ub = Ra<7:0>; }});
682075SN/A        0x0d: stw({{ Mem.uw = Ra<15:0>; }});
692075SN/A        0x2c: stl({{ Mem.ul = Ra<31:0>; }});
702075SN/A        0x2d: stq({{ Mem.uq = Ra.uq; }});
712075SN/A        0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
722075SN/A        0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
732075SN/A        0x27: stt({{ Mem.df = Fa; }});
742735Sktlim@umich.edu#ifdef USE_COPY
752069SN/A        0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
762069SN/A                                       {{ fault = xc->copy(EA); }},
772075SN/A                                       inst_flags = [IsMemRef, IsStore, IsCopy]);
782735Sktlim@umich.edu#endif
792068SN/A    }
802068SN/A
812068SN/A    format StoreCond {
822075SN/A        0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
832068SN/A                    {{
842069SN/A                        uint64_t tmp = write_result;
852068SN/A                        // see stq_c
862068SN/A                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
874027Sstever@eecs.umich.edu                        if (tmp == 1) {
884027Sstever@eecs.umich.edu                            xc->setStCondFailures(0);
894027Sstever@eecs.umich.edu                        }
906076Sgblack@eecs.umich.edu                    }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
912075SN/A        0x2f: stq_c({{ Mem.uq = Ra; }},
922068SN/A                    {{
932069SN/A                        uint64_t tmp = write_result;
942068SN/A                        // If the write operation returns 0 or 1, then
952068SN/A                        // this was a conventional store conditional,
962068SN/A                        // and the value indicates the success/failure
972068SN/A                        // of the operation.  If another value is
982068SN/A                        // returned, then this was a Turbolaser
992068SN/A                        // mailbox access, and we don't update the
1002068SN/A                        // result register at all.
1012068SN/A                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
1024027Sstever@eecs.umich.edu                        if (tmp == 1) {
1034027Sstever@eecs.umich.edu                            // clear failure counter... this is
1044027Sstever@eecs.umich.edu                            // non-architectural and for debugging
1054027Sstever@eecs.umich.edu                            // only.
1064027Sstever@eecs.umich.edu                            xc->setStCondFailures(0);
1074027Sstever@eecs.umich.edu                        }
1086076Sgblack@eecs.umich.edu                    }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
1092068SN/A    }
1102068SN/A
1112068SN/A    format IntegerOperate {
1122068SN/A
1132068SN/A        0x10: decode INTFUNC {	// integer arithmetic operations
1142068SN/A
1152068SN/A            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1162068SN/A            0x40: addlv({{
1172068SN/A                uint32_t tmp  = Ra.sl + Rb_or_imm.sl;
1182068SN/A                // signed overflow occurs when operands have same sign
1192068SN/A                // and sign of result does not match.
1202068SN/A                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1212147SN/A                    fault = new IntegerOverflowFault;
1222068SN/A                Rc.sl = tmp;
1232068SN/A            }});
1242068SN/A            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1252068SN/A            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1262068SN/A
1272068SN/A            0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1282068SN/A            0x60: addqv({{
1292068SN/A                uint64_t tmp = Ra + Rb_or_imm;
1302068SN/A                // signed overflow occurs when operands have same sign
1312068SN/A                // and sign of result does not match.
1322068SN/A                if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1332147SN/A                    fault = new IntegerOverflowFault;
1342068SN/A                Rc = tmp;
1352068SN/A            }});
1362068SN/A            0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1372068SN/A            0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1382068SN/A
1392068SN/A            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1402068SN/A            0x49: sublv({{
1412068SN/A                uint32_t tmp  = Ra.sl - Rb_or_imm.sl;
1422068SN/A                // signed overflow detection is same as for add,
1432068SN/A                // except we need to look at the *complemented*
1442068SN/A                // sign bit of the subtrahend (Rb), i.e., if the initial
1452068SN/A                // signs are the *same* then no overflow can occur
1462068SN/A                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1472147SN/A                    fault = new IntegerOverflowFault;
1482068SN/A                Rc.sl = tmp;
1492068SN/A            }});
1502068SN/A            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1512068SN/A            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1522068SN/A
1532068SN/A            0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1542068SN/A            0x69: subqv({{
1552068SN/A                uint64_t tmp  = Ra - Rb_or_imm;
1562068SN/A                // signed overflow detection is same as for add,
1572068SN/A                // except we need to look at the *complemented*
1582068SN/A                // sign bit of the subtrahend (Rb), i.e., if the initial
1592068SN/A                // signs are the *same* then no overflow can occur
1602068SN/A                if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1612147SN/A                    fault = new IntegerOverflowFault;
1622068SN/A                Rc = tmp;
1632068SN/A            }});
1642068SN/A            0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1652068SN/A            0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1662068SN/A
1672068SN/A            0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1682068SN/A            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1692068SN/A            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
1702068SN/A            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1712068SN/A            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
1722068SN/A
1732068SN/A            0x0f: cmpbge({{
1742068SN/A                int hi = 7;
1752068SN/A                int lo = 0;
1762068SN/A                uint64_t tmp = 0;
1772068SN/A                for (int i = 0; i < 8; ++i) {
1782068SN/A                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1792068SN/A                    hi += 8;
1802068SN/A                    lo += 8;
1812068SN/A                }
1822068SN/A                Rc = tmp;
1832068SN/A            }});
1842068SN/A        }
1852068SN/A
1862068SN/A        0x11: decode INTFUNC {	// integer logical operations
1872068SN/A
1882068SN/A            0x00: and({{ Rc = Ra & Rb_or_imm; }});
1892068SN/A            0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1902068SN/A            0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1912068SN/A            0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1922068SN/A            0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1932068SN/A            0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1942068SN/A
1952068SN/A            // conditional moves
1962068SN/A            0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
1972068SN/A            0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
1982068SN/A            0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
1992068SN/A            0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
2002068SN/A            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
2012068SN/A            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
2022068SN/A            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
2032068SN/A            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
2042068SN/A
2052068SN/A            // For AMASK, RA must be R31.
2062068SN/A            0x61: decode RA {
2072068SN/A                31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
2082068SN/A            }
2092068SN/A
2102068SN/A            // For IMPLVER, RA must be R31 and the B operand
2112068SN/A            // must be the immediate value 1.
2122068SN/A            0x6c: decode RA {
2132068SN/A                31: decode IMM {
2142068SN/A                    1: decode INTIMM {
2152068SN/A                        // return EV5 for FULL_SYSTEM and EV6 otherwise
2162068SN/A                        1: implver({{
2172068SN/A#if FULL_SYSTEM
2182068SN/A                             Rc = 1;
2192068SN/A#else
2202068SN/A                             Rc = 2;
2212068SN/A#endif
2222068SN/A                        }});
2232068SN/A                    }
2242068SN/A                }
2252068SN/A            }
2262068SN/A
2272068SN/A#if FULL_SYSTEM
2282068SN/A            // The mysterious 11.25...
2292068SN/A            0x25: WarnUnimpl::eleven25();
2302068SN/A#endif
2312068SN/A        }
2322068SN/A
2332068SN/A        0x12: decode INTFUNC {
2342068SN/A            0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
2352068SN/A            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
2362068SN/A            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
2372068SN/A
2382068SN/A            0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
2392068SN/A            0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
2402068SN/A            0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
2412068SN/A            0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
2422068SN/A
2432068SN/A            0x52: mskwh({{
2442068SN/A                int bv = Rb_or_imm<2:0>;
2452068SN/A                Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
2462068SN/A            }});
2472068SN/A            0x62: msklh({{
2482068SN/A                int bv = Rb_or_imm<2:0>;
2492068SN/A                Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
2502068SN/A            }});
2512068SN/A            0x72: mskqh({{
2522068SN/A                int bv = Rb_or_imm<2:0>;
2532068SN/A                Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
2542068SN/A            }});
2552068SN/A
2562068SN/A            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
2572068SN/A            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
2582068SN/A            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
2592068SN/A            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
2602068SN/A
2612068SN/A            0x5a: extwh({{
2622068SN/A                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
2632068SN/A            0x6a: extlh({{
2642068SN/A                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
2652068SN/A            0x7a: extqh({{
2662068SN/A                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
2672068SN/A
2682068SN/A            0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
2692068SN/A            0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
2702068SN/A            0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
2712068SN/A            0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
2722068SN/A
2732068SN/A            0x57: inswh({{
2742068SN/A                int bv = Rb_or_imm<2:0>;
2752068SN/A                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
2762068SN/A            }});
2772068SN/A            0x67: inslh({{
2782068SN/A                int bv = Rb_or_imm<2:0>;
2792068SN/A                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2802068SN/A            }});
2812068SN/A            0x77: insqh({{
2822068SN/A                int bv = Rb_or_imm<2:0>;
2832068SN/A                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
2842068SN/A            }});
2852068SN/A
2862068SN/A            0x30: zap({{
2872068SN/A                uint64_t zapmask = 0;
2882068SN/A                for (int i = 0; i < 8; ++i) {
2892068SN/A                    if (Rb_or_imm<i:>)
2902068SN/A                        zapmask |= (mask(8) << (i * 8));
2912068SN/A                }
2922068SN/A                Rc = Ra & ~zapmask;
2932068SN/A            }});
2942068SN/A            0x31: zapnot({{
2952068SN/A                uint64_t zapmask = 0;
2962068SN/A                for (int i = 0; i < 8; ++i) {
2972068SN/A                    if (!Rb_or_imm<i:>)
2982068SN/A                        zapmask |= (mask(8) << (i * 8));
2992068SN/A                }
3002068SN/A                Rc = Ra & ~zapmask;
3012068SN/A            }});
3022068SN/A        }
3032068SN/A
3042068SN/A        0x13: decode INTFUNC {	// integer multiplies
3052068SN/A            0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
3062068SN/A            0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
3072068SN/A            0x30: umulh({{
3082068SN/A                uint64_t hi, lo;
3092068SN/A                mul128(Ra, Rb_or_imm, hi, lo);
3102068SN/A                Rc = hi;
3112068SN/A            }}, IntMultOp);
3122068SN/A            0x40: mullv({{
3132068SN/A                // 32-bit multiply with trap on overflow
3142068SN/A                int64_t Rax = Ra.sl;	// sign extended version of Ra.sl
3152068SN/A                int64_t Rbx = Rb_or_imm.sl;
3162068SN/A                int64_t tmp = Rax * Rbx;
3172068SN/A                // To avoid overflow, all the upper 32 bits must match
3182068SN/A                // the sign bit of the lower 32.  We code this as
3192068SN/A                // checking the upper 33 bits for all 0s or all 1s.
3202068SN/A                uint64_t sign_bits = tmp<63:31>;
3212068SN/A                if (sign_bits != 0 && sign_bits != mask(33))
3222147SN/A                    fault = new IntegerOverflowFault;
3232068SN/A                Rc.sl = tmp<31:0>;
3242068SN/A            }}, IntMultOp);
3252068SN/A            0x60: mulqv({{
3262068SN/A                // 64-bit multiply with trap on overflow
3272068SN/A                uint64_t hi, lo;
3282068SN/A                mul128(Ra, Rb_or_imm, hi, lo);
3292068SN/A                // all the upper 64 bits must match the sign bit of
3302068SN/A                // the lower 64
3312068SN/A                if (!((hi == 0 && lo<63:> == 0) ||
3322068SN/A                      (hi == mask(64) && lo<63:> == 1)))
3332147SN/A                    fault = new IntegerOverflowFault;
3342068SN/A                Rc = lo;
3352068SN/A            }}, IntMultOp);
3362068SN/A        }
3372068SN/A
3382068SN/A        0x1c: decode INTFUNC {
3392068SN/A            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
3402068SN/A            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
3412068SN/A            0x32: ctlz({{
3422068SN/A                             uint64_t count = 0;
3432068SN/A                             uint64_t temp = Rb;
3442068SN/A                             if (temp<63:32>) temp >>= 32; else count += 32;
3452068SN/A                             if (temp<31:16>) temp >>= 16; else count += 16;
3462068SN/A                             if (temp<15:8>) temp >>= 8; else count += 8;
3472068SN/A                             if (temp<7:4>) temp >>= 4; else count += 4;
3482068SN/A                             if (temp<3:2>) temp >>= 2; else count += 2;
3492068SN/A                             if (temp<1:1>) temp >>= 1; else count += 1;
3502068SN/A                             if ((temp<0:0>) != 0x1) count += 1;
3512068SN/A                             Rc = count;
3522068SN/A                           }}, IntAluOp);
3532068SN/A
3542068SN/A            0x33: cttz({{
3552068SN/A                             uint64_t count = 0;
3562068SN/A                             uint64_t temp = Rb;
3572068SN/A                             if (!(temp<31:0>)) { temp >>= 32; count += 32; }
3582068SN/A                             if (!(temp<15:0>)) { temp >>= 16; count += 16; }
3592068SN/A                             if (!(temp<7:0>)) { temp >>= 8; count += 8; }
3602068SN/A                             if (!(temp<3:0>)) { temp >>= 4; count += 4; }
3612068SN/A                             if (!(temp<1:0>)) { temp >>= 2; count += 2; }
3622068SN/A                             if (!(temp<0:0> & ULL(0x1))) count += 1;
3632068SN/A                             Rc = count;
3642068SN/A                           }}, IntAluOp);
3652068SN/A
3662068SN/A            format FailUnimpl {
3672068SN/A                0x30: ctpop();
3682068SN/A                0x31: perr();
3692068SN/A                0x34: unpkbw();
3702068SN/A                0x35: unpkbl();
3712068SN/A                0x36: pkwb();
3722068SN/A                0x37: pklb();
3732068SN/A                0x38: minsb8();
3742068SN/A                0x39: minsw4();
3752068SN/A                0x3a: minub8();
3762068SN/A                0x3b: minuw4();
3772068SN/A                0x3c: maxub8();
3782068SN/A                0x3d: maxuw4();
3792068SN/A                0x3e: maxsb8();
3802068SN/A                0x3f: maxsw4();
3812068SN/A            }
3822068SN/A
3832068SN/A            format BasicOperateWithNopCheck {
3842068SN/A                0x70: decode RB {
3852068SN/A                    31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
3862068SN/A                }
3872068SN/A                0x78: decode RB {
3882068SN/A                    31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
3892068SN/A                              FloatCvtOp);
3902068SN/A                }
3912068SN/A            }
3922068SN/A        }
3932068SN/A    }
3942068SN/A
3952068SN/A    // Conditional branches.
3962068SN/A    format CondBranch {
3972068SN/A        0x39: beq({{ cond = (Ra == 0); }});
3982068SN/A        0x3d: bne({{ cond = (Ra != 0); }});
3992068SN/A        0x3e: bge({{ cond = (Ra.sq >= 0); }});
4002068SN/A        0x3f: bgt({{ cond = (Ra.sq >  0); }});
4012068SN/A        0x3b: ble({{ cond = (Ra.sq <= 0); }});
4022068SN/A        0x3a: blt({{ cond = (Ra.sq < 0); }});
4032068SN/A        0x38: blbc({{ cond = ((Ra & 1) == 0); }});
4042068SN/A        0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
4052068SN/A
4062068SN/A        0x31: fbeq({{ cond = (Fa == 0); }});
4072068SN/A        0x35: fbne({{ cond = (Fa != 0); }});
4082068SN/A        0x36: fbge({{ cond = (Fa >= 0); }});
4092068SN/A        0x37: fbgt({{ cond = (Fa >  0); }});
4102068SN/A        0x33: fble({{ cond = (Fa <= 0); }});
4112068SN/A        0x32: fblt({{ cond = (Fa < 0); }});
4122068SN/A    }
4132068SN/A
4142068SN/A    // unconditional branches
4152068SN/A    format UncondBranch {
4162068SN/A        0x30: br();
4172068SN/A        0x34: bsr(IsCall);
4182068SN/A    }
4192068SN/A
4202068SN/A    // indirect branches
4212068SN/A    0x1a: decode JMPFUNC {
4222068SN/A        format Jump {
4232068SN/A            0: jmp();
4242068SN/A            1: jsr(IsCall);
4252068SN/A            2: ret(IsReturn);
4262068SN/A            3: jsr_coroutine(IsCall, IsReturn);
4272068SN/A        }
4282068SN/A    }
4292068SN/A
4302068SN/A    // Square root and integer-to-FP moves
4312068SN/A    0x14: decode FP_SHORTFUNC {
4322068SN/A        // Integer to FP register moves must have RB == 31
4332068SN/A        0x4: decode RB {
4342068SN/A            31: decode FP_FULLFUNC {
4352068SN/A                format BasicOperateWithNopCheck {
4362068SN/A                    0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
4372068SN/A                    0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
4382068SN/A                    0x014: FailUnimpl::itoff();	// VAX-format conversion
4392068SN/A                }
4402068SN/A            }
4412068SN/A        }
4422068SN/A
4432068SN/A        // Square root instructions must have FA == 31
4442068SN/A        0xb: decode FA {
4452068SN/A            31: decode FP_TYPEFUNC {
4462068SN/A                format FloatingPointOperate {
4472068SN/A#if SS_COMPATIBLE_FP
4482068SN/A                    0x0b: sqrts({{
4492068SN/A                        if (Fb < 0.0)
4502147SN/A                            fault = new ArithmeticFault;
4512068SN/A                        Fc = sqrt(Fb);
4522068SN/A                    }}, FloatSqrtOp);
4532068SN/A#else
4542068SN/A                    0x0b: sqrts({{
4552068SN/A                        if (Fb.sf < 0.0)
4562147SN/A                            fault = new ArithmeticFault;
4572068SN/A                        Fc.sf = sqrt(Fb.sf);
4582068SN/A                    }}, FloatSqrtOp);
4592068SN/A#endif
4602068SN/A                    0x2b: sqrtt({{
4612068SN/A                        if (Fb < 0.0)
4622147SN/A                            fault = new ArithmeticFault;
4632068SN/A                        Fc = sqrt(Fb);
4642068SN/A                    }}, FloatSqrtOp);
4652068SN/A                }
4662068SN/A            }
4672068SN/A        }
4682068SN/A
4692068SN/A        // VAX-format sqrtf and sqrtg are not implemented
4702068SN/A        0xa: FailUnimpl::sqrtfg();
4712068SN/A    }
4722068SN/A
4732068SN/A    // IEEE floating point
4742068SN/A    0x16: decode FP_SHORTFUNC_TOP2 {
4752068SN/A        // The top two bits of the short function code break this
4762068SN/A        // space into four groups: binary ops, compares, reserved, and
4772068SN/A        // conversions.  See Table 4-12 of AHB.  There are different
4782068SN/A        // special cases in these different groups, so we decode on
4792068SN/A        // these top two bits first just to select a decode strategy.
4802068SN/A        // Most of these instructions may have various trapping and
4812068SN/A        // rounding mode flags set; these are decoded in the
4822068SN/A        // FloatingPointDecode template used by the
4832068SN/A        // FloatingPointOperate format.
4842068SN/A
4852068SN/A        // add/sub/mul/div: just decode on the short function code
4862068SN/A        // and source type.  All valid trapping and rounding modes apply.
4872068SN/A        0: decode FP_TRAPMODE {
4882068SN/A            // check for valid trapping modes here
4892068SN/A            0,1,5,7: decode FP_TYPEFUNC {
4902068SN/A                   format FloatingPointOperate {
4912068SN/A#if SS_COMPATIBLE_FP
4922068SN/A                       0x00: adds({{ Fc = Fa + Fb; }});
4932068SN/A                       0x01: subs({{ Fc = Fa - Fb; }});
4942068SN/A                       0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
4952068SN/A                       0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
4962068SN/A#else
4972068SN/A                       0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
4982068SN/A                       0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
4992068SN/A                       0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
5002068SN/A                       0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
5012068SN/A#endif
5022068SN/A
5032068SN/A                       0x20: addt({{ Fc = Fa + Fb; }});
5042068SN/A                       0x21: subt({{ Fc = Fa - Fb; }});
5052068SN/A                       0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
5062068SN/A                       0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
5072068SN/A                   }
5082068SN/A             }
5092068SN/A        }
5102068SN/A
5112068SN/A        // Floating-point compare instructions must have the default
5122068SN/A        // rounding mode, and may use the default trapping mode or
5132068SN/A        // /SU.  Both trapping modes are treated the same by M5; the
5142068SN/A        // only difference on the real hardware (as far a I can tell)
5152068SN/A        // is that without /SU you'd get an imprecise trap if you
5162068SN/A        // tried to compare a NaN with something else (instead of an
5172068SN/A        // "unordered" result).
5182068SN/A        1: decode FP_FULLFUNC {
5192068SN/A            format BasicOperateWithNopCheck {
5202068SN/A                0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
5212068SN/A                                     FloatCmpOp);
5222068SN/A                0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
5232068SN/A                                     FloatCmpOp);
5242068SN/A                0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
5252068SN/A                                     FloatCmpOp);
5262068SN/A                0x0a4, 0x5a4: cmptun({{ // unordered
5272068SN/A                    Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
5282068SN/A                }}, FloatCmpOp);
5292068SN/A            }
5302068SN/A        }
5312068SN/A
5322068SN/A        // The FP-to-integer and integer-to-FP conversion insts
5332068SN/A        // require that FA be 31.
5342068SN/A        3: decode FA {
5352068SN/A            31: decode FP_TYPEFUNC {
5362068SN/A                format FloatingPointOperate {
5372068SN/A                    0x2f: decode FP_ROUNDMODE {
5382068SN/A                        format FPFixedRounding {
5392068SN/A                            // "chopped" i.e. round toward zero
5402068SN/A                            0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
5412068SN/A                                     Chopped);
5422068SN/A                            // round to minus infinity
5432068SN/A                            1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
5442068SN/A                                     MinusInfinity);
5452068SN/A                        }
5462068SN/A                      default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
5472068SN/A                    }
5482068SN/A
5492068SN/A                    // The cvtts opcode is overloaded to be cvtst if the trap
5502068SN/A                    // mode is 2 or 6 (which are not valid otherwise)
5512068SN/A                    0x2c: decode FP_FULLFUNC {
5522068SN/A                        format BasicOperateWithNopCheck {
5532068SN/A                            // trap on denorm version "cvtst/s" is
5542068SN/A                            // simulated same as cvtst
5552068SN/A                            0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
5562068SN/A                        }
5572068SN/A                      default: cvtts({{ Fc.sf = Fb; }});
5582068SN/A                    }
5592068SN/A
5602068SN/A                    // The trapping mode for integer-to-FP conversions
5612068SN/A                    // must be /SUI or nothing; /U and /SU are not
5622068SN/A                    // allowed.  The full set of rounding modes are
5632068SN/A                    // supported though.
5642068SN/A                    0x3c: decode FP_TRAPMODE {
5652068SN/A                        0,7: cvtqs({{ Fc.sf = Fb.sq; }});
5662068SN/A                    }
5672068SN/A                    0x3e: decode FP_TRAPMODE {
5682068SN/A                        0,7: cvtqt({{ Fc    = Fb.sq; }});
5692068SN/A                    }
5702068SN/A                }
5712068SN/A            }
5722068SN/A        }
5732068SN/A    }
5742068SN/A
5752068SN/A    // misc FP operate
5762068SN/A    0x17: decode FP_FULLFUNC {
5772068SN/A        format BasicOperateWithNopCheck {
5782068SN/A            0x010: cvtlq({{
5792068SN/A                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
5802068SN/A            }});
5812068SN/A            0x030: cvtql({{
5822068SN/A                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
5832068SN/A            }});
5842068SN/A
5852068SN/A            // We treat the precise & imprecise trapping versions of
5862068SN/A            // cvtql identically.
5872068SN/A            0x130, 0x530: cvtqlv({{
5882068SN/A                // To avoid overflow, all the upper 32 bits must match
5892068SN/A                // the sign bit of the lower 32.  We code this as
5902068SN/A                // checking the upper 33 bits for all 0s or all 1s.
5912068SN/A                uint64_t sign_bits = Fb.uq<63:31>;
5922068SN/A                if (sign_bits != 0 && sign_bits != mask(33))
5932147SN/A                    fault = new IntegerOverflowFault;
5942068SN/A                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
5952068SN/A            }});
5962068SN/A
5972068SN/A            0x020: cpys({{  // copy sign
5982068SN/A                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
5992068SN/A            }});
6002068SN/A            0x021: cpysn({{ // copy sign negated
6012068SN/A                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
6022068SN/A            }});
6032068SN/A            0x022: cpyse({{ // copy sign and exponent
6042068SN/A                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
6052068SN/A            }});
6062068SN/A
6072068SN/A            0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
6082068SN/A            0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
6092068SN/A            0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
6102068SN/A            0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
6112068SN/A            0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
6122068SN/A            0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
6132068SN/A
6142336SN/A            0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
6152336SN/A            0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
6162068SN/A        }
6172068SN/A    }
6182068SN/A
6192068SN/A    // miscellaneous mem-format ops
6202068SN/A    0x18: decode MEMFUNC {
6212068SN/A        format WarnUnimpl {
6222068SN/A            0x8000: fetch();
6232068SN/A            0xa000: fetch_m();
6242068SN/A            0xe800: ecb();
6252068SN/A        }
6262068SN/A
6272068SN/A        format MiscPrefetch {
6282068SN/A            0xf800: wh64({{ EA = Rb & ~ULL(63); }},
6292068SN/A                         {{ xc->writeHint(EA, 64, memAccessFlags); }},
6302075SN/A                         mem_flags = NO_FAULT,
6312075SN/A                         inst_flags = [IsMemRef, IsDataPrefetch,
6322075SN/A                                       IsStore, MemWriteOp]);
6332068SN/A        }
6342068SN/A
6352068SN/A        format BasicOperate {
6362068SN/A            0xc000: rpcc({{
6372068SN/A#if FULL_SYSTEM
6382068SN/A        /* Rb is a fake dependency so here is a fun way to get
6392068SN/A         * the parser to understand that.
6402068SN/A         */
6415568Snate@binkert.org                Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
6422068SN/A
6432068SN/A#else
6442068SN/A                Ra = curTick;
6452068SN/A#endif
6462312SN/A            }}, IsUnverifiable);
6472068SN/A
6482068SN/A            // All of the barrier instructions below do nothing in
6492068SN/A            // their execute() methods (hence the empty code blocks).
6502068SN/A            // All of their functionality is hard-coded in the
6512068SN/A            // pipeline based on the flags IsSerializing,
6522068SN/A            // IsMemBarrier, and IsWriteBarrier.  In the current
6532068SN/A            // detailed CPU model, the execute() function only gets
6542068SN/A            // called at fetch, so there's no way to generate pipeline
6552068SN/A            // behavior at any other stage.  Once we go to an
6562068SN/A            // exec-in-exec CPU model we should be able to get rid of
6572068SN/A            // these flags and implement this behavior via the
6582068SN/A            // execute() methods.
6592068SN/A
6602068SN/A            // trapb is just a barrier on integer traps, where excb is
6612068SN/A            // a barrier on integer and FP traps.  "EXCB is thus a
6622068SN/A            // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
6632068SN/A            // them the same though.
6642292SN/A            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
6652292SN/A            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
6662068SN/A            0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
6672068SN/A            0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
6682068SN/A        }
6692068SN/A
6702068SN/A#if FULL_SYSTEM
6712068SN/A        format BasicOperate {
6722068SN/A            0xe000: rc({{
6733454Sgblack@eecs.umich.edu                Ra = IntrFlag;
6743454Sgblack@eecs.umich.edu                IntrFlag = 0;
6752704Sktlim@umich.edu            }}, IsNonSpeculative, IsUnverifiable);
6762068SN/A            0xf000: rs({{
6773454Sgblack@eecs.umich.edu                Ra = IntrFlag;
6783454Sgblack@eecs.umich.edu                IntrFlag = 1;
6792704Sktlim@umich.edu            }}, IsNonSpeculative, IsUnverifiable);
6802068SN/A        }
6812068SN/A#else
6822068SN/A        format FailUnimpl {
6832068SN/A            0xe000: rc();
6842068SN/A            0xf000: rs();
6852068SN/A        }
6862068SN/A#endif
6872068SN/A    }
6882068SN/A
6892068SN/A#if FULL_SYSTEM
6902068SN/A    0x00: CallPal::call_pal({{
6912068SN/A        if (!palValid ||
6922068SN/A            (palPriv
6935568Snate@binkert.org             && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
6942068SN/A            // invalid pal function code, or attempt to do privileged
6952068SN/A            // PAL call in non-kernel mode
6962147SN/A            fault = new UnimplementedOpcodeFault;
6972068SN/A        }
6982068SN/A        else {
6992068SN/A            // check to see if simulator wants to do something special
7002068SN/A            // on this PAL call (including maybe suppress it)
7015702Ssaidi@eecs.umich.edu            bool dopal = xc->simPalCheck(palFunc);
7022068SN/A
7032068SN/A            if (dopal) {
7045568Snate@binkert.org                xc->setMiscReg(IPR_EXC_ADDR, NPC);
7055568Snate@binkert.org                NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
7062068SN/A            }
7072068SN/A        }
7082068SN/A    }}, IsNonSpeculative);
7092068SN/A#else
7102068SN/A    0x00: decode PALFUNC {
7112068SN/A        format EmulatedCallPal {
7122068SN/A            0x00: halt ({{
7133144Shsul@eecs.umich.edu                exitSimLoop("halt instruction encountered");
7142068SN/A            }}, IsNonSpeculative);
7152068SN/A            0x83: callsys({{
7162562SN/A                xc->syscall(R0);
7174828Sgblack@eecs.umich.edu            }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
7182068SN/A            // Read uniq reg into ABI return value register (r0)
7192336SN/A            0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
7202068SN/A            // Write uniq reg with value from ABI arg register (r16)
7212336SN/A            0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
7222068SN/A        }
7232068SN/A    }
7242068SN/A#endif
7252068SN/A
7262068SN/A#if FULL_SYSTEM
7272227SN/A    0x1b: decode PALMODE {
7282227SN/A        0: OpcdecFault::hw_st_quad();
7292227SN/A        1: decode HW_LDST_QUAD {
7302227SN/A            format HwLoad {
7314036Sktlim@umich.edu                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }},
7324036Sktlim@umich.edu                         L, IsSerializing, IsSerializeBefore);
7334036Sktlim@umich.edu                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }},
7344036Sktlim@umich.edu                         Q, IsSerializing, IsSerializeBefore);
7352227SN/A            }
7362068SN/A        }
7372069SN/A    }
7382068SN/A
7392227SN/A    0x1f: decode PALMODE {
7402227SN/A        0: OpcdecFault::hw_st_cond();
7412227SN/A        format HwStore {
7422227SN/A            1: decode HW_LDST_COND {
7432227SN/A                0: decode HW_LDST_QUAD {
7442227SN/A                    0: hw_st({{ EA = (Rb + disp) & ~3; }},
7454036Sktlim@umich.edu                {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
7462227SN/A                    1: hw_st({{ EA = (Rb + disp) & ~7; }},
7474036Sktlim@umich.edu                {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore);
7482227SN/A                }
7492227SN/A
7502227SN/A                1: FailUnimpl::hw_st_cond();
7512068SN/A            }
7522068SN/A        }
7532068SN/A    }
7542068SN/A
7552227SN/A    0x19: decode PALMODE {
7562227SN/A        0: OpcdecFault::hw_mfpr();
7572227SN/A        format HwMoveIPR {
7582227SN/A            1: hw_mfpr({{
7593469Sgblack@eecs.umich.edu                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
7603464Sgblack@eecs.umich.edu                        IprToMiscRegIndex[ipr_index] : -1;
7613464Sgblack@eecs.umich.edu                if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
7623466Sgblack@eecs.umich.edu                    miscRegIndex >= NumInternalProcRegs)
7633457Sgblack@eecs.umich.edu                        fault = new UnimplementedOpcodeFault;
7643457Sgblack@eecs.umich.edu                else
7654172Ssaidi@eecs.umich.edu                    Ra = xc->readMiscReg(miscRegIndex);
7662336SN/A            }}, IsIprAccess);
7672227SN/A        }
7682227SN/A    }
7692227SN/A
7702227SN/A    0x1d: decode PALMODE {
7712227SN/A        0: OpcdecFault::hw_mtpr();
7722227SN/A        format HwMoveIPR {
7732227SN/A            1: hw_mtpr({{
7743469Sgblack@eecs.umich.edu                int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
7753464Sgblack@eecs.umich.edu                        IprToMiscRegIndex[ipr_index] : -1;
7763467Sgblack@eecs.umich.edu                if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
7773466Sgblack@eecs.umich.edu                    miscRegIndex >= NumInternalProcRegs)
7783457Sgblack@eecs.umich.edu                        fault = new UnimplementedOpcodeFault;
7793457Sgblack@eecs.umich.edu                else
7804172Ssaidi@eecs.umich.edu                    xc->setMiscReg(miscRegIndex, Ra);
7812068SN/A                if (traceData) { traceData->setData(Ra); }
7822336SN/A            }}, IsIprAccess);
7832227SN/A        }
7842068SN/A    }
7852068SN/A
7865780Ssteve.reinhardt@amd.com  0x1e: decode PALMODE {
7875780Ssteve.reinhardt@amd.com      0: OpcdecFault::hw_rei();
7885780Ssteve.reinhardt@amd.com        format BasicOperate {
7895780Ssteve.reinhardt@amd.com          1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
7905780Ssteve.reinhardt@amd.com        }
7915780Ssteve.reinhardt@amd.com    }
7925780Ssteve.reinhardt@amd.com
7935780Ssteve.reinhardt@amd.com#endif
7945780Ssteve.reinhardt@amd.com
7952068SN/A    format BasicOperate {
7962068SN/A        // M5 special opcodes use the reserved 0x01 opcode space
7972068SN/A        0x01: decode M5FUNC {
7985780Ssteve.reinhardt@amd.com#if FULL_SYSTEM
7992068SN/A            0x00: arm({{
8004090Ssaidi@eecs.umich.edu                PseudoInst::arm(xc->tcBase());
8012068SN/A            }}, IsNonSpeculative);
8022068SN/A            0x01: quiesce({{
8034090Ssaidi@eecs.umich.edu                PseudoInst::quiesce(xc->tcBase());
8042292SN/A            }}, IsNonSpeculative, IsQuiesce);
8052188SN/A            0x02: quiesceNs({{
8064090Ssaidi@eecs.umich.edu                PseudoInst::quiesceNs(xc->tcBase(), R16);
8072292SN/A            }}, IsNonSpeculative, IsQuiesce);
8082188SN/A            0x03: quiesceCycles({{
8094090Ssaidi@eecs.umich.edu                PseudoInst::quiesceCycles(xc->tcBase(), R16);
8102355SN/A            }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
8112188SN/A            0x04: quiesceTime({{
8124090Ssaidi@eecs.umich.edu                R0 = PseudoInst::quiesceTime(xc->tcBase());
8132355SN/A            }}, IsNonSpeculative, IsUnverifiable);
8145780Ssteve.reinhardt@amd.com#endif
8155741Snate@binkert.org            0x07: rpns({{
8165741Snate@binkert.org                R0 = PseudoInst::rpns(xc->tcBase());
8175741Snate@binkert.org            }}, IsNonSpeculative, IsUnverifiable);
8185808Snate@binkert.org            0x09: wakeCPU({{
8195808Snate@binkert.org                PseudoInst::wakeCPU(xc->tcBase(), R16);
8205808Snate@binkert.org            }}, IsNonSpeculative, IsUnverifiable);
8215505Snate@binkert.org            0x10: deprecated_ivlb({{
8225505Snate@binkert.org                warn_once("Obsolete M5 ivlb instruction encountered.\n");
8233680Sstever@eecs.umich.edu            }});
8245505Snate@binkert.org            0x11: deprecated_ivle({{
8255505Snate@binkert.org                warn_once("Obsolete M5 ivlb instruction encountered.\n");
8263680Sstever@eecs.umich.edu            }});
8275505Snate@binkert.org            0x20: deprecated_exit ({{
8285505Snate@binkert.org                warn_once("deprecated M5 exit instruction encountered.\n");
8295505Snate@binkert.org                PseudoInst::m5exit(xc->tcBase(), 0);
8302068SN/A            }}, No_OpClass, IsNonSpeculative);
8312068SN/A            0x21: m5exit({{
8324090Ssaidi@eecs.umich.edu                PseudoInst::m5exit(xc->tcBase(), R16);
8332068SN/A            }}, No_OpClass, IsNonSpeculative);
8345780Ssteve.reinhardt@amd.com#if FULL_SYSTEM
8352358SN/A            0x31: loadsymbol({{
8364090Ssaidi@eecs.umich.edu                PseudoInst::loadsymbol(xc->tcBase());
8372358SN/A            }}, No_OpClass, IsNonSpeculative);
8385505Snate@binkert.org            0x30: initparam({{
8395505Snate@binkert.org                Ra = xc->tcBase()->getCpuPtr()->system->init_param;
8405505Snate@binkert.org            }});
8415780Ssteve.reinhardt@amd.com#endif
8422068SN/A            0x40: resetstats({{
8434090Ssaidi@eecs.umich.edu                PseudoInst::resetstats(xc->tcBase(), R16, R17);
8442068SN/A            }}, IsNonSpeculative);
8452068SN/A            0x41: dumpstats({{
8464090Ssaidi@eecs.umich.edu                PseudoInst::dumpstats(xc->tcBase(), R16, R17);
8472068SN/A            }}, IsNonSpeculative);
8482068SN/A            0x42: dumpresetstats({{
8494090Ssaidi@eecs.umich.edu                PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
8502068SN/A            }}, IsNonSpeculative);
8512068SN/A            0x43: m5checkpoint({{
8524090Ssaidi@eecs.umich.edu                PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
8532068SN/A            }}, IsNonSpeculative);
8545780Ssteve.reinhardt@amd.com#if FULL_SYSTEM
8552068SN/A            0x50: m5readfile({{
8564090Ssaidi@eecs.umich.edu                R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
8572068SN/A            }}, IsNonSpeculative);
8585780Ssteve.reinhardt@amd.com#endif
8592068SN/A            0x51: m5break({{
8604090Ssaidi@eecs.umich.edu                PseudoInst::debugbreak(xc->tcBase());
8612068SN/A            }}, IsNonSpeculative);
8622068SN/A            0x52: m5switchcpu({{
8634090Ssaidi@eecs.umich.edu                PseudoInst::switchcpu(xc->tcBase());
8642068SN/A            }}, IsNonSpeculative);
8655780Ssteve.reinhardt@amd.com#if FULL_SYSTEM
8662068SN/A            0x53: m5addsymbol({{
8674090Ssaidi@eecs.umich.edu                PseudoInst::addsymbol(xc->tcBase(), R16, R17);
8682068SN/A            }}, IsNonSpeculative);
8695780Ssteve.reinhardt@amd.com#endif
8702188SN/A            0x54: m5panic({{
8712284SN/A                panic("M5 panic instruction called at pc=%#x.", xc->readPC());
8722188SN/A            }}, IsNonSpeculative);
8735952Ssaidi@eecs.umich.edu#define  CPANN(lbl) CPA::cpa()->lbl(xc->tcBase())
8745952Ssaidi@eecs.umich.edu            0x55: decode RA {
8755952Ssaidi@eecs.umich.edu                0x00: m5a_old({{
8765952Ssaidi@eecs.umich.edu                    panic("Deprecated M5 annotate instruction executed at pc=%#x\n",
8775952Ssaidi@eecs.umich.edu                        xc->readPC());
8785952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
8795952Ssaidi@eecs.umich.edu                0x01: m5a_bsm({{
8805952Ssaidi@eecs.umich.edu                    CPANN(swSmBegin);
8815952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
8825952Ssaidi@eecs.umich.edu                0x02: m5a_esm({{
8835952Ssaidi@eecs.umich.edu                    CPANN(swSmEnd);
8845952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
8855952Ssaidi@eecs.umich.edu                0x03: m5a_begin({{
8865952Ssaidi@eecs.umich.edu                    CPANN(swExplictBegin);
8875952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
8885952Ssaidi@eecs.umich.edu                0x04: m5a_end({{
8895952Ssaidi@eecs.umich.edu                    CPANN(swEnd);
8905952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
8915952Ssaidi@eecs.umich.edu                0x06: m5a_q({{
8925952Ssaidi@eecs.umich.edu                    CPANN(swQ);
8935952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
8945952Ssaidi@eecs.umich.edu                0x07: m5a_dq({{
8955952Ssaidi@eecs.umich.edu                    CPANN(swDq);
8965952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
8975952Ssaidi@eecs.umich.edu                0x08: m5a_wf({{
8985952Ssaidi@eecs.umich.edu                    CPANN(swWf);
8995952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
9005952Ssaidi@eecs.umich.edu                0x09: m5a_we({{
9015952Ssaidi@eecs.umich.edu                    CPANN(swWe);
9025952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
9035952Ssaidi@eecs.umich.edu                0x0C: m5a_sq({{
9045952Ssaidi@eecs.umich.edu                    CPANN(swSq);
9055952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
9065952Ssaidi@eecs.umich.edu                0x0D: m5a_aq({{
9075952Ssaidi@eecs.umich.edu                    CPANN(swAq);
9085952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
9095952Ssaidi@eecs.umich.edu                0x0E: m5a_pq({{
9105952Ssaidi@eecs.umich.edu                    CPANN(swPq);
9115952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
9125952Ssaidi@eecs.umich.edu                0x0F: m5a_l({{
9135952Ssaidi@eecs.umich.edu                    CPANN(swLink);
9145952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
9155952Ssaidi@eecs.umich.edu                0x10: m5a_identify({{
9165952Ssaidi@eecs.umich.edu                    CPANN(swIdentify);
9175952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
9185952Ssaidi@eecs.umich.edu                0x11: m5a_getid({{
9195952Ssaidi@eecs.umich.edu                    R0 = CPANN(swGetId);
9205952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
9215952Ssaidi@eecs.umich.edu                0x13: m5a_scl({{
9225952Ssaidi@eecs.umich.edu                    CPANN(swSyscallLink);
9235952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
9245952Ssaidi@eecs.umich.edu                0x14: m5a_rq({{
9255952Ssaidi@eecs.umich.edu                    CPANN(swRq);
9265952Ssaidi@eecs.umich.edu                }}, IsNonSpeculative);
9275952Ssaidi@eecs.umich.edu            } // M5 Annotate Operations
9285952Ssaidi@eecs.umich.edu#undef CPANN
9295505Snate@binkert.org            0x56: m5reserved2({{
9305505Snate@binkert.org                warn("M5 reserved opcode ignored");
9315505Snate@binkert.org            }}, IsNonSpeculative);
9325505Snate@binkert.org            0x57: m5reserved3({{
9335505Snate@binkert.org                warn("M5 reserved opcode ignored");
9345505Snate@binkert.org            }}, IsNonSpeculative);
9355505Snate@binkert.org            0x58: m5reserved4({{
9365505Snate@binkert.org                warn("M5 reserved opcode ignored");
9375505Snate@binkert.org            }}, IsNonSpeculative);
9385505Snate@binkert.org            0x59: m5reserved5({{
9395505Snate@binkert.org                warn("M5 reserved opcode ignored");
9403089Ssaidi@eecs.umich.edu            }}, IsNonSpeculative);
9412068SN/A        }
9422068SN/A    }
9432068SN/A}
944