decoder.isa revision 4027
16691Stjones1@inf.ed.ac.uk// -*- mode:c++ -*- 26691Stjones1@inf.ed.ac.uk 36691Stjones1@inf.ed.ac.uk// Copyright (c) 2003-2006 The Regents of The University of Michigan 46691Stjones1@inf.ed.ac.uk// All rights reserved. 56691Stjones1@inf.ed.ac.uk// 66691Stjones1@inf.ed.ac.uk// Redistribution and use in source and binary forms, with or without 76691Stjones1@inf.ed.ac.uk// modification, are permitted provided that the following conditions are 86691Stjones1@inf.ed.ac.uk// met: redistributions of source code must retain the above copyright 96691Stjones1@inf.ed.ac.uk// notice, this list of conditions and the following disclaimer; 106691Stjones1@inf.ed.ac.uk// redistributions in binary form must reproduce the above copyright 116691Stjones1@inf.ed.ac.uk// notice, this list of conditions and the following disclaimer in the 126691Stjones1@inf.ed.ac.uk// documentation and/or other materials provided with the distribution; 136691Stjones1@inf.ed.ac.uk// neither the name of the copyright holders nor the names of its 146691Stjones1@inf.ed.ac.uk// contributors may be used to endorse or promote products derived from 156691Stjones1@inf.ed.ac.uk// this software without specific prior written permission. 166691Stjones1@inf.ed.ac.uk// 176691Stjones1@inf.ed.ac.uk// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186691Stjones1@inf.ed.ac.uk// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196691Stjones1@inf.ed.ac.uk// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206691Stjones1@inf.ed.ac.uk// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216691Stjones1@inf.ed.ac.uk// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226691Stjones1@inf.ed.ac.uk// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236691Stjones1@inf.ed.ac.uk// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246691Stjones1@inf.ed.ac.uk// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256691Stjones1@inf.ed.ac.uk// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266691Stjones1@inf.ed.ac.uk// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276691Stjones1@inf.ed.ac.uk// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286691Stjones1@inf.ed.ac.uk// 296691Stjones1@inf.ed.ac.uk// Authors: Steve Reinhardt 306691Stjones1@inf.ed.ac.uk 316691Stjones1@inf.ed.ac.uk//////////////////////////////////////////////////////////////////// 326691Stjones1@inf.ed.ac.uk// 336691Stjones1@inf.ed.ac.uk// The actual decoder specification 346691Stjones1@inf.ed.ac.uk// 3511793Sbrandon.potter@amd.com 3611793Sbrandon.potter@amd.comdecode OPCODE default Unknown::unknown() { 3711793Sbrandon.potter@amd.com 386691Stjones1@inf.ed.ac.uk format LoadAddress { 396691Stjones1@inf.ed.ac.uk 0x08: lda({{ Ra = Rb + disp; }}); 406691Stjones1@inf.ed.ac.uk 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 416691Stjones1@inf.ed.ac.uk } 426691Stjones1@inf.ed.ac.uk 4311794Sbrandon.potter@amd.com format LoadOrNop { 446691Stjones1@inf.ed.ac.uk 0x0a: ldbu({{ Ra.uq = Mem.ub; }}); 456691Stjones1@inf.ed.ac.uk 0x0c: ldwu({{ Ra.uq = Mem.uw; }}); 466691Stjones1@inf.ed.ac.uk 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 476691Stjones1@inf.ed.ac.uk 0x23: ldt({{ Fa = Mem.df; }}); 486691Stjones1@inf.ed.ac.uk 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED); 496691Stjones1@inf.ed.ac.uk 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED); 506691Stjones1@inf.ed.ac.uk#ifdef USE_COPY 516691Stjones1@inf.ed.ac.uk 0x20: MiscPrefetch::copy_load({{ EA = Ra; }}, 5211851Sbrandon.potter@amd.com {{ fault = xc->copySrcTranslate(EA); }}, 536691Stjones1@inf.ed.ac.uk inst_flags = [IsMemRef, IsLoad, IsCopy]); 546691Stjones1@inf.ed.ac.uk#endif 556701Sgblack@eecs.umich.edu } 566701Sgblack@eecs.umich.edu 576691Stjones1@inf.ed.ac.uk format LoadOrPrefetch { 586691Stjones1@inf.ed.ac.uk 0x28: ldl({{ Ra.sl = Mem.sl; }}); 599149SAli.Saidi@ARM.com 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT); 609149SAli.Saidi@ARM.com // IsFloating flag on lds gets the prefetch to disassemble 616691Stjones1@inf.ed.ac.uk // using f31 instead of r31... funcitonally it's unnecessary 626691Stjones1@inf.ed.ac.uk 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }}, 636691Stjones1@inf.ed.ac.uk pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 648706Sandreas.hansson@arm.com } 656691Stjones1@inf.ed.ac.uk 666691Stjones1@inf.ed.ac.uk format Store { 676691Stjones1@inf.ed.ac.uk 0x0e: stb({{ Mem.ub = Ra<7:0>; }}); 686691Stjones1@inf.ed.ac.uk 0x0d: stw({{ Mem.uw = Ra<15:0>; }}); 696691Stjones1@inf.ed.ac.uk 0x2c: stl({{ Mem.ul = Ra<31:0>; }}); 706691Stjones1@inf.ed.ac.uk 0x2d: stq({{ Mem.uq = Ra.uq; }}); 716691Stjones1@inf.ed.ac.uk 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 726691Stjones1@inf.ed.ac.uk 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 736691Stjones1@inf.ed.ac.uk 0x27: stt({{ Mem.df = Fa; }}); 746691Stjones1@inf.ed.ac.uk#ifdef USE_COPY 756691Stjones1@inf.ed.ac.uk 0x24: MiscPrefetch::copy_store({{ EA = Rb; }}, 766691Stjones1@inf.ed.ac.uk {{ fault = xc->copy(EA); }}, 776691Stjones1@inf.ed.ac.uk inst_flags = [IsMemRef, IsStore, IsCopy]); 786691Stjones1@inf.ed.ac.uk#endif 796691Stjones1@inf.ed.ac.uk } 806691Stjones1@inf.ed.ac.uk 816691Stjones1@inf.ed.ac.uk format StoreCond { 826691Stjones1@inf.ed.ac.uk 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }}, 836691Stjones1@inf.ed.ac.uk {{ 846691Stjones1@inf.ed.ac.uk uint64_t tmp = write_result; 856691Stjones1@inf.ed.ac.uk // see stq_c 866691Stjones1@inf.ed.ac.uk Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 876691Stjones1@inf.ed.ac.uk if (tmp == 1) { 886691Stjones1@inf.ed.ac.uk xc->setStCondFailures(0); 896691Stjones1@inf.ed.ac.uk } 906691Stjones1@inf.ed.ac.uk }}, mem_flags = LOCKED, inst_flags = IsStoreConditional); 916691Stjones1@inf.ed.ac.uk 0x2f: stq_c({{ Mem.uq = Ra; }}, 926691Stjones1@inf.ed.ac.uk {{ 936691Stjones1@inf.ed.ac.uk uint64_t tmp = write_result; 946691Stjones1@inf.ed.ac.uk // If the write operation returns 0 or 1, then 956691Stjones1@inf.ed.ac.uk // this was a conventional store conditional, 966691Stjones1@inf.ed.ac.uk // and the value indicates the success/failure 976691Stjones1@inf.ed.ac.uk // of the operation. If another value is 986691Stjones1@inf.ed.ac.uk // returned, then this was a Turbolaser 996691Stjones1@inf.ed.ac.uk // mailbox access, and we don't update the 1006691Stjones1@inf.ed.ac.uk // result register at all. 1016691Stjones1@inf.ed.ac.uk Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 1026691Stjones1@inf.ed.ac.uk if (tmp == 1) { 1036691Stjones1@inf.ed.ac.uk // clear failure counter... this is 1046691Stjones1@inf.ed.ac.uk // non-architectural and for debugging 1056691Stjones1@inf.ed.ac.uk // only. 1066691Stjones1@inf.ed.ac.uk xc->setStCondFailures(0); 1076691Stjones1@inf.ed.ac.uk } 1086691Stjones1@inf.ed.ac.uk }}, mem_flags = LOCKED, inst_flags = IsStoreConditional); 1096691Stjones1@inf.ed.ac.uk } 1106691Stjones1@inf.ed.ac.uk 1116691Stjones1@inf.ed.ac.uk format IntegerOperate { 1126691Stjones1@inf.ed.ac.uk 1136691Stjones1@inf.ed.ac.uk 0x10: decode INTFUNC { // integer arithmetic operations 1146691Stjones1@inf.ed.ac.uk 1156691Stjones1@inf.ed.ac.uk 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 1166691Stjones1@inf.ed.ac.uk 0x40: addlv({{ 1176691Stjones1@inf.ed.ac.uk uint32_t tmp = Ra.sl + Rb_or_imm.sl; 1186691Stjones1@inf.ed.ac.uk // signed overflow occurs when operands have same sign 1196691Stjones1@inf.ed.ac.uk // and sign of result does not match. 1206691Stjones1@inf.ed.ac.uk if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1216691Stjones1@inf.ed.ac.uk fault = new IntegerOverflowFault; 1226691Stjones1@inf.ed.ac.uk Rc.sl = tmp; 1236691Stjones1@inf.ed.ac.uk }}); 1246691Stjones1@inf.ed.ac.uk 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); 1256691Stjones1@inf.ed.ac.uk 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }}); 1266691Stjones1@inf.ed.ac.uk 1276691Stjones1@inf.ed.ac.uk 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 1286691Stjones1@inf.ed.ac.uk 0x60: addqv({{ 1296691Stjones1@inf.ed.ac.uk uint64_t tmp = Ra + Rb_or_imm; 1306691Stjones1@inf.ed.ac.uk // signed overflow occurs when operands have same sign 1316691Stjones1@inf.ed.ac.uk // and sign of result does not match. 1326691Stjones1@inf.ed.ac.uk if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1336691Stjones1@inf.ed.ac.uk fault = new IntegerOverflowFault; 1346691Stjones1@inf.ed.ac.uk Rc = tmp; 1356691Stjones1@inf.ed.ac.uk }}); 1366691Stjones1@inf.ed.ac.uk 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 1376691Stjones1@inf.ed.ac.uk 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 1386691Stjones1@inf.ed.ac.uk 1396691Stjones1@inf.ed.ac.uk 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }}); 1406691Stjones1@inf.ed.ac.uk 0x49: sublv({{ 1416691Stjones1@inf.ed.ac.uk uint32_t tmp = Ra.sl - Rb_or_imm.sl; 1426691Stjones1@inf.ed.ac.uk // signed overflow detection is same as for add, 1436691Stjones1@inf.ed.ac.uk // except we need to look at the *complemented* 1446691Stjones1@inf.ed.ac.uk // sign bit of the subtrahend (Rb), i.e., if the initial 1456691Stjones1@inf.ed.ac.uk // signs are the *same* then no overflow can occur 1466691Stjones1@inf.ed.ac.uk if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1476691Stjones1@inf.ed.ac.uk fault = new IntegerOverflowFault; 1486691Stjones1@inf.ed.ac.uk Rc.sl = tmp; 1496691Stjones1@inf.ed.ac.uk }}); 1506691Stjones1@inf.ed.ac.uk 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); 1516691Stjones1@inf.ed.ac.uk 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }}); 1526691Stjones1@inf.ed.ac.uk 1536691Stjones1@inf.ed.ac.uk 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 1546691Stjones1@inf.ed.ac.uk 0x69: subqv({{ 1556691Stjones1@inf.ed.ac.uk uint64_t tmp = Ra - Rb_or_imm; 1566691Stjones1@inf.ed.ac.uk // signed overflow detection is same as for add, 1576691Stjones1@inf.ed.ac.uk // except we need to look at the *complemented* 1586691Stjones1@inf.ed.ac.uk // sign bit of the subtrahend (Rb), i.e., if the initial 1596691Stjones1@inf.ed.ac.uk // signs are the *same* then no overflow can occur 1606691Stjones1@inf.ed.ac.uk if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1616691Stjones1@inf.ed.ac.uk fault = new IntegerOverflowFault; 1626691Stjones1@inf.ed.ac.uk Rc = tmp; 1636691Stjones1@inf.ed.ac.uk }}); 1646691Stjones1@inf.ed.ac.uk 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 1656691Stjones1@inf.ed.ac.uk 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 1666691Stjones1@inf.ed.ac.uk 1676691Stjones1@inf.ed.ac.uk 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 1686691Stjones1@inf.ed.ac.uk 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }}); 1696691Stjones1@inf.ed.ac.uk 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }}); 1706691Stjones1@inf.ed.ac.uk 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }}); 1716691Stjones1@inf.ed.ac.uk 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }}); 1726691Stjones1@inf.ed.ac.uk 1736691Stjones1@inf.ed.ac.uk 0x0f: cmpbge({{ 1746691Stjones1@inf.ed.ac.uk int hi = 7; 1756691Stjones1@inf.ed.ac.uk int lo = 0; 1766691Stjones1@inf.ed.ac.uk uint64_t tmp = 0; 1776691Stjones1@inf.ed.ac.uk for (int i = 0; i < 8; ++i) { 1786691Stjones1@inf.ed.ac.uk tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i; 1796691Stjones1@inf.ed.ac.uk hi += 8; 1806691Stjones1@inf.ed.ac.uk lo += 8; 1816691Stjones1@inf.ed.ac.uk } 1826691Stjones1@inf.ed.ac.uk Rc = tmp; 1836691Stjones1@inf.ed.ac.uk }}); 1846691Stjones1@inf.ed.ac.uk } 1856691Stjones1@inf.ed.ac.uk 1866691Stjones1@inf.ed.ac.uk 0x11: decode INTFUNC { // integer logical operations 1876691Stjones1@inf.ed.ac.uk 1886691Stjones1@inf.ed.ac.uk 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 1896691Stjones1@inf.ed.ac.uk 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 1906691Stjones1@inf.ed.ac.uk 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 1916691Stjones1@inf.ed.ac.uk 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 1926691Stjones1@inf.ed.ac.uk 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 1936691Stjones1@inf.ed.ac.uk 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 1946691Stjones1@inf.ed.ac.uk 1956691Stjones1@inf.ed.ac.uk // conditional moves 1966691Stjones1@inf.ed.ac.uk 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 1976691Stjones1@inf.ed.ac.uk 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 1986691Stjones1@inf.ed.ac.uk 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 1996691Stjones1@inf.ed.ac.uk 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 2006691Stjones1@inf.ed.ac.uk 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }}); 2016691Stjones1@inf.ed.ac.uk 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }}); 2026691Stjones1@inf.ed.ac.uk 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }}); 2036691Stjones1@inf.ed.ac.uk 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }}); 2046691Stjones1@inf.ed.ac.uk 2056691Stjones1@inf.ed.ac.uk // For AMASK, RA must be R31. 2066691Stjones1@inf.ed.ac.uk 0x61: decode RA { 2076691Stjones1@inf.ed.ac.uk 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 2086691Stjones1@inf.ed.ac.uk } 2096691Stjones1@inf.ed.ac.uk 21010495Snilay@cs.wisc.edu // For IMPLVER, RA must be R31 and the B operand 2116691Stjones1@inf.ed.ac.uk // must be the immediate value 1. 2126691Stjones1@inf.ed.ac.uk 0x6c: decode RA { 2136691Stjones1@inf.ed.ac.uk 31: decode IMM { 2146691Stjones1@inf.ed.ac.uk 1: decode INTIMM { 2156691Stjones1@inf.ed.ac.uk // return EV5 for FULL_SYSTEM and EV6 otherwise 2166691Stjones1@inf.ed.ac.uk 1: implver({{ 2176691Stjones1@inf.ed.ac.uk#if FULL_SYSTEM 2186691Stjones1@inf.ed.ac.uk Rc = 1; 2196691Stjones1@inf.ed.ac.uk#else 2206691Stjones1@inf.ed.ac.uk Rc = 2; 2216691Stjones1@inf.ed.ac.uk#endif 2226691Stjones1@inf.ed.ac.uk }}); 2236691Stjones1@inf.ed.ac.uk } 2246691Stjones1@inf.ed.ac.uk } 2256691Stjones1@inf.ed.ac.uk } 2266691Stjones1@inf.ed.ac.uk 2276691Stjones1@inf.ed.ac.uk#if FULL_SYSTEM 2286691Stjones1@inf.ed.ac.uk // The mysterious 11.25... 2296691Stjones1@inf.ed.ac.uk 0x25: WarnUnimpl::eleven25(); 2306691Stjones1@inf.ed.ac.uk#endif 2316691Stjones1@inf.ed.ac.uk } 2326691Stjones1@inf.ed.ac.uk 2336691Stjones1@inf.ed.ac.uk 0x12: decode INTFUNC { 2346691Stjones1@inf.ed.ac.uk 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 2356691Stjones1@inf.ed.ac.uk 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }}); 2366691Stjones1@inf.ed.ac.uk 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }}); 2376691Stjones1@inf.ed.ac.uk 2386691Stjones1@inf.ed.ac.uk 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 2396691Stjones1@inf.ed.ac.uk 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 2406691Stjones1@inf.ed.ac.uk 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 2416691Stjones1@inf.ed.ac.uk 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 2426691Stjones1@inf.ed.ac.uk 2436691Stjones1@inf.ed.ac.uk 0x52: mskwh({{ 2446691Stjones1@inf.ed.ac.uk int bv = Rb_or_imm<2:0>; 2456691Stjones1@inf.ed.ac.uk Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 2466691Stjones1@inf.ed.ac.uk }}); 2476691Stjones1@inf.ed.ac.uk 0x62: msklh({{ 2486691Stjones1@inf.ed.ac.uk int bv = Rb_or_imm<2:0>; 2496691Stjones1@inf.ed.ac.uk Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 2506691Stjones1@inf.ed.ac.uk }}); 2516691Stjones1@inf.ed.ac.uk 0x72: mskqh({{ 2526691Stjones1@inf.ed.ac.uk int bv = Rb_or_imm<2:0>; 2536691Stjones1@inf.ed.ac.uk Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 2546691Stjones1@inf.ed.ac.uk }}); 2556691Stjones1@inf.ed.ac.uk 2566691Stjones1@inf.ed.ac.uk 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 2576691Stjones1@inf.ed.ac.uk 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 2586691Stjones1@inf.ed.ac.uk 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 2596691Stjones1@inf.ed.ac.uk 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }}); 2606691Stjones1@inf.ed.ac.uk 2616691Stjones1@inf.ed.ac.uk 0x5a: extwh({{ 2626691Stjones1@inf.ed.ac.uk Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 2636691Stjones1@inf.ed.ac.uk 0x6a: extlh({{ 2646691Stjones1@inf.ed.ac.uk Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 2656691Stjones1@inf.ed.ac.uk 0x7a: extqh({{ 2666691Stjones1@inf.ed.ac.uk Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 2676691Stjones1@inf.ed.ac.uk 2686691Stjones1@inf.ed.ac.uk 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 2696691Stjones1@inf.ed.ac.uk 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 2706691Stjones1@inf.ed.ac.uk 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 2716691Stjones1@inf.ed.ac.uk 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 2726691Stjones1@inf.ed.ac.uk 2736691Stjones1@inf.ed.ac.uk 0x57: inswh({{ 2746691Stjones1@inf.ed.ac.uk int bv = Rb_or_imm<2:0>; 2756691Stjones1@inf.ed.ac.uk Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0; 2766691Stjones1@inf.ed.ac.uk }}); 2776691Stjones1@inf.ed.ac.uk 0x67: inslh({{ 2786691Stjones1@inf.ed.ac.uk int bv = Rb_or_imm<2:0>; 2796691Stjones1@inf.ed.ac.uk Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0; 2806691Stjones1@inf.ed.ac.uk }}); 2816691Stjones1@inf.ed.ac.uk 0x77: insqh({{ 2826691Stjones1@inf.ed.ac.uk int bv = Rb_or_imm<2:0>; 2836691Stjones1@inf.ed.ac.uk Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0; 2846691Stjones1@inf.ed.ac.uk }}); 2856691Stjones1@inf.ed.ac.uk 28610495Snilay@cs.wisc.edu 0x30: zap({{ 2876691Stjones1@inf.ed.ac.uk uint64_t zapmask = 0; 2886691Stjones1@inf.ed.ac.uk for (int i = 0; i < 8; ++i) { 2896691Stjones1@inf.ed.ac.uk if (Rb_or_imm<i:>) 2906691Stjones1@inf.ed.ac.uk zapmask |= (mask(8) << (i * 8)); 2916691Stjones1@inf.ed.ac.uk } 2926691Stjones1@inf.ed.ac.uk Rc = Ra & ~zapmask; 2936691Stjones1@inf.ed.ac.uk }}); 2946691Stjones1@inf.ed.ac.uk 0x31: zapnot({{ 2956691Stjones1@inf.ed.ac.uk uint64_t zapmask = 0; 2966691Stjones1@inf.ed.ac.uk for (int i = 0; i < 8; ++i) { 2976691Stjones1@inf.ed.ac.uk if (!Rb_or_imm<i:>) 2986691Stjones1@inf.ed.ac.uk zapmask |= (mask(8) << (i * 8)); 2996691Stjones1@inf.ed.ac.uk } 3006691Stjones1@inf.ed.ac.uk Rc = Ra & ~zapmask; 3016691Stjones1@inf.ed.ac.uk }}); 3026691Stjones1@inf.ed.ac.uk } 3036691Stjones1@inf.ed.ac.uk 3046691Stjones1@inf.ed.ac.uk 0x13: decode INTFUNC { // integer multiplies 3056691Stjones1@inf.ed.ac.uk 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 3066691Stjones1@inf.ed.ac.uk 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 3076691Stjones1@inf.ed.ac.uk 0x30: umulh({{ 3086691Stjones1@inf.ed.ac.uk uint64_t hi, lo; 3096691Stjones1@inf.ed.ac.uk mul128(Ra, Rb_or_imm, hi, lo); 3106691Stjones1@inf.ed.ac.uk Rc = hi; 3116691Stjones1@inf.ed.ac.uk }}, IntMultOp); 3126691Stjones1@inf.ed.ac.uk 0x40: mullv({{ 3136691Stjones1@inf.ed.ac.uk // 32-bit multiply with trap on overflow 3146691Stjones1@inf.ed.ac.uk int64_t Rax = Ra.sl; // sign extended version of Ra.sl 3156691Stjones1@inf.ed.ac.uk int64_t Rbx = Rb_or_imm.sl; 3166691Stjones1@inf.ed.ac.uk int64_t tmp = Rax * Rbx; 3176691Stjones1@inf.ed.ac.uk // To avoid overflow, all the upper 32 bits must match 3186691Stjones1@inf.ed.ac.uk // the sign bit of the lower 32. We code this as 3196691Stjones1@inf.ed.ac.uk // checking the upper 33 bits for all 0s or all 1s. 3206691Stjones1@inf.ed.ac.uk uint64_t sign_bits = tmp<63:31>; 3216691Stjones1@inf.ed.ac.uk if (sign_bits != 0 && sign_bits != mask(33)) 3226691Stjones1@inf.ed.ac.uk fault = new IntegerOverflowFault; 3236691Stjones1@inf.ed.ac.uk Rc.sl = tmp<31:0>; 3246691Stjones1@inf.ed.ac.uk }}, IntMultOp); 3256691Stjones1@inf.ed.ac.uk 0x60: mulqv({{ 3266691Stjones1@inf.ed.ac.uk // 64-bit multiply with trap on overflow 3276691Stjones1@inf.ed.ac.uk uint64_t hi, lo; 3286691Stjones1@inf.ed.ac.uk mul128(Ra, Rb_or_imm, hi, lo); 3296691Stjones1@inf.ed.ac.uk // all the upper 64 bits must match the sign bit of 3306691Stjones1@inf.ed.ac.uk // the lower 64 3316691Stjones1@inf.ed.ac.uk if (!((hi == 0 && lo<63:> == 0) || 3326691Stjones1@inf.ed.ac.uk (hi == mask(64) && lo<63:> == 1))) 3336691Stjones1@inf.ed.ac.uk fault = new IntegerOverflowFault; 3346691Stjones1@inf.ed.ac.uk Rc = lo; 3356691Stjones1@inf.ed.ac.uk }}, IntMultOp); 3366691Stjones1@inf.ed.ac.uk } 3376691Stjones1@inf.ed.ac.uk 3386691Stjones1@inf.ed.ac.uk 0x1c: decode INTFUNC { 3396691Stjones1@inf.ed.ac.uk 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 3406691Stjones1@inf.ed.ac.uk 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } 3416691Stjones1@inf.ed.ac.uk 0x32: ctlz({{ 3426691Stjones1@inf.ed.ac.uk uint64_t count = 0; 3436691Stjones1@inf.ed.ac.uk uint64_t temp = Rb; 3446691Stjones1@inf.ed.ac.uk if (temp<63:32>) temp >>= 32; else count += 32; 3456691Stjones1@inf.ed.ac.uk if (temp<31:16>) temp >>= 16; else count += 16; 3466691Stjones1@inf.ed.ac.uk if (temp<15:8>) temp >>= 8; else count += 8; 3476691Stjones1@inf.ed.ac.uk if (temp<7:4>) temp >>= 4; else count += 4; 3486691Stjones1@inf.ed.ac.uk if (temp<3:2>) temp >>= 2; else count += 2; 3496691Stjones1@inf.ed.ac.uk if (temp<1:1>) temp >>= 1; else count += 1; 3506691Stjones1@inf.ed.ac.uk if ((temp<0:0>) != 0x1) count += 1; 3516691Stjones1@inf.ed.ac.uk Rc = count; 3526691Stjones1@inf.ed.ac.uk }}, IntAluOp); 3536691Stjones1@inf.ed.ac.uk 3546691Stjones1@inf.ed.ac.uk 0x33: cttz({{ 3556691Stjones1@inf.ed.ac.uk uint64_t count = 0; 3566691Stjones1@inf.ed.ac.uk uint64_t temp = Rb; 3576691Stjones1@inf.ed.ac.uk if (!(temp<31:0>)) { temp >>= 32; count += 32; } 3586691Stjones1@inf.ed.ac.uk if (!(temp<15:0>)) { temp >>= 16; count += 16; } 3596691Stjones1@inf.ed.ac.uk if (!(temp<7:0>)) { temp >>= 8; count += 8; } 3606691Stjones1@inf.ed.ac.uk if (!(temp<3:0>)) { temp >>= 4; count += 4; } 3616691Stjones1@inf.ed.ac.uk if (!(temp<1:0>)) { temp >>= 2; count += 2; } 3626691Stjones1@inf.ed.ac.uk if (!(temp<0:0> & ULL(0x1))) count += 1; 3636691Stjones1@inf.ed.ac.uk Rc = count; 3646691Stjones1@inf.ed.ac.uk }}, IntAluOp); 3656691Stjones1@inf.ed.ac.uk 3666691Stjones1@inf.ed.ac.uk format FailUnimpl { 3676691Stjones1@inf.ed.ac.uk 0x30: ctpop(); 3686691Stjones1@inf.ed.ac.uk 0x31: perr(); 3696691Stjones1@inf.ed.ac.uk 0x34: unpkbw(); 3706691Stjones1@inf.ed.ac.uk 0x35: unpkbl(); 3716691Stjones1@inf.ed.ac.uk 0x36: pkwb(); 3726691Stjones1@inf.ed.ac.uk 0x37: pklb(); 3736691Stjones1@inf.ed.ac.uk 0x38: minsb8(); 3746691Stjones1@inf.ed.ac.uk 0x39: minsw4(); 3756691Stjones1@inf.ed.ac.uk 0x3a: minub8(); 3766691Stjones1@inf.ed.ac.uk 0x3b: minuw4(); 3776691Stjones1@inf.ed.ac.uk 0x3c: maxub8(); 3786691Stjones1@inf.ed.ac.uk 0x3d: maxuw4(); 3796691Stjones1@inf.ed.ac.uk 0x3e: maxsb8(); 3806691Stjones1@inf.ed.ac.uk 0x3f: maxsw4(); 3816691Stjones1@inf.ed.ac.uk } 3826691Stjones1@inf.ed.ac.uk 3836691Stjones1@inf.ed.ac.uk format BasicOperateWithNopCheck { 3846691Stjones1@inf.ed.ac.uk 0x70: decode RB { 3856691Stjones1@inf.ed.ac.uk 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp); 3866691Stjones1@inf.ed.ac.uk } 3876691Stjones1@inf.ed.ac.uk 0x78: decode RB { 3886691Stjones1@inf.ed.ac.uk 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }}, 3896691Stjones1@inf.ed.ac.uk FloatCvtOp); 3906691Stjones1@inf.ed.ac.uk } 3916691Stjones1@inf.ed.ac.uk } 3926691Stjones1@inf.ed.ac.uk } 3936691Stjones1@inf.ed.ac.uk } 3946691Stjones1@inf.ed.ac.uk 3956691Stjones1@inf.ed.ac.uk // Conditional branches. 3966691Stjones1@inf.ed.ac.uk format CondBranch { 3976691Stjones1@inf.ed.ac.uk 0x39: beq({{ cond = (Ra == 0); }}); 3986691Stjones1@inf.ed.ac.uk 0x3d: bne({{ cond = (Ra != 0); }}); 3996691Stjones1@inf.ed.ac.uk 0x3e: bge({{ cond = (Ra.sq >= 0); }}); 4006691Stjones1@inf.ed.ac.uk 0x3f: bgt({{ cond = (Ra.sq > 0); }}); 4016691Stjones1@inf.ed.ac.uk 0x3b: ble({{ cond = (Ra.sq <= 0); }}); 4026691Stjones1@inf.ed.ac.uk 0x3a: blt({{ cond = (Ra.sq < 0); }}); 4036691Stjones1@inf.ed.ac.uk 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 4046691Stjones1@inf.ed.ac.uk 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 4056691Stjones1@inf.ed.ac.uk 4066691Stjones1@inf.ed.ac.uk 0x31: fbeq({{ cond = (Fa == 0); }}); 4076691Stjones1@inf.ed.ac.uk 0x35: fbne({{ cond = (Fa != 0); }}); 4086691Stjones1@inf.ed.ac.uk 0x36: fbge({{ cond = (Fa >= 0); }}); 4096691Stjones1@inf.ed.ac.uk 0x37: fbgt({{ cond = (Fa > 0); }}); 4106691Stjones1@inf.ed.ac.uk 0x33: fble({{ cond = (Fa <= 0); }}); 4116691Stjones1@inf.ed.ac.uk 0x32: fblt({{ cond = (Fa < 0); }}); 4126691Stjones1@inf.ed.ac.uk } 4136691Stjones1@inf.ed.ac.uk 4146691Stjones1@inf.ed.ac.uk // unconditional branches 4156691Stjones1@inf.ed.ac.uk format UncondBranch { 4166691Stjones1@inf.ed.ac.uk 0x30: br(); 4176691Stjones1@inf.ed.ac.uk 0x34: bsr(IsCall); 41811851Sbrandon.potter@amd.com } 4196691Stjones1@inf.ed.ac.uk 42011851Sbrandon.potter@amd.com // indirect branches 42111851Sbrandon.potter@amd.com 0x1a: decode JMPFUNC { 4226691Stjones1@inf.ed.ac.uk format Jump { 4236691Stjones1@inf.ed.ac.uk 0: jmp(); 4246691Stjones1@inf.ed.ac.uk 1: jsr(IsCall); 4256691Stjones1@inf.ed.ac.uk 2: ret(IsReturn); 4266691Stjones1@inf.ed.ac.uk 3: jsr_coroutine(IsCall, IsReturn); 4276691Stjones1@inf.ed.ac.uk } 4286691Stjones1@inf.ed.ac.uk } 4296691Stjones1@inf.ed.ac.uk 4306691Stjones1@inf.ed.ac.uk // Square root and integer-to-FP moves 4316691Stjones1@inf.ed.ac.uk 0x14: decode FP_SHORTFUNC { 4326691Stjones1@inf.ed.ac.uk // Integer to FP register moves must have RB == 31 4336691Stjones1@inf.ed.ac.uk 0x4: decode RB { 4346691Stjones1@inf.ed.ac.uk 31: decode FP_FULLFUNC { 4357532Ssteve.reinhardt@amd.com format BasicOperateWithNopCheck { 4366691Stjones1@inf.ed.ac.uk 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 43711851Sbrandon.potter@amd.com 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 4386691Stjones1@inf.ed.ac.uk 0x014: FailUnimpl::itoff(); // VAX-format conversion 4396691Stjones1@inf.ed.ac.uk } 4406691Stjones1@inf.ed.ac.uk } 4416701Sgblack@eecs.umich.edu } 4426691Stjones1@inf.ed.ac.uk 4436691Stjones1@inf.ed.ac.uk // Square root instructions must have FA == 31 4446691Stjones1@inf.ed.ac.uk 0xb: decode FA { 4456691Stjones1@inf.ed.ac.uk 31: decode FP_TYPEFUNC { 4466701Sgblack@eecs.umich.edu format FloatingPointOperate { 4476691Stjones1@inf.ed.ac.uk#if SS_COMPATIBLE_FP 4486691Stjones1@inf.ed.ac.uk 0x0b: sqrts({{ 4496691Stjones1@inf.ed.ac.uk if (Fb < 0.0) 4506691Stjones1@inf.ed.ac.uk fault = new ArithmeticFault; 4516691Stjones1@inf.ed.ac.uk Fc = sqrt(Fb); 4526691Stjones1@inf.ed.ac.uk }}, FloatSqrtOp); 4536691Stjones1@inf.ed.ac.uk#else 4546691Stjones1@inf.ed.ac.uk 0x0b: sqrts({{ 4556691Stjones1@inf.ed.ac.uk if (Fb.sf < 0.0) 4566691Stjones1@inf.ed.ac.uk fault = new ArithmeticFault; 457 Fc.sf = sqrt(Fb.sf); 458 }}, FloatSqrtOp); 459#endif 460 0x2b: sqrtt({{ 461 if (Fb < 0.0) 462 fault = new ArithmeticFault; 463 Fc = sqrt(Fb); 464 }}, FloatSqrtOp); 465 } 466 } 467 } 468 469 // VAX-format sqrtf and sqrtg are not implemented 470 0xa: FailUnimpl::sqrtfg(); 471 } 472 473 // IEEE floating point 474 0x16: decode FP_SHORTFUNC_TOP2 { 475 // The top two bits of the short function code break this 476 // space into four groups: binary ops, compares, reserved, and 477 // conversions. See Table 4-12 of AHB. There are different 478 // special cases in these different groups, so we decode on 479 // these top two bits first just to select a decode strategy. 480 // Most of these instructions may have various trapping and 481 // rounding mode flags set; these are decoded in the 482 // FloatingPointDecode template used by the 483 // FloatingPointOperate format. 484 485 // add/sub/mul/div: just decode on the short function code 486 // and source type. All valid trapping and rounding modes apply. 487 0: decode FP_TRAPMODE { 488 // check for valid trapping modes here 489 0,1,5,7: decode FP_TYPEFUNC { 490 format FloatingPointOperate { 491#if SS_COMPATIBLE_FP 492 0x00: adds({{ Fc = Fa + Fb; }}); 493 0x01: subs({{ Fc = Fa - Fb; }}); 494 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 495 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 496#else 497 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }}); 498 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }}); 499 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); 500 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp); 501#endif 502 503 0x20: addt({{ Fc = Fa + Fb; }}); 504 0x21: subt({{ Fc = Fa - Fb; }}); 505 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 506 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 507 } 508 } 509 } 510 511 // Floating-point compare instructions must have the default 512 // rounding mode, and may use the default trapping mode or 513 // /SU. Both trapping modes are treated the same by M5; the 514 // only difference on the real hardware (as far a I can tell) 515 // is that without /SU you'd get an imprecise trap if you 516 // tried to compare a NaN with something else (instead of an 517 // "unordered" result). 518 1: decode FP_FULLFUNC { 519 format BasicOperateWithNopCheck { 520 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 521 FloatCmpOp); 522 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 523 FloatCmpOp); 524 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 525 FloatCmpOp); 526 0x0a4, 0x5a4: cmptun({{ // unordered 527 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 528 }}, FloatCmpOp); 529 } 530 } 531 532 // The FP-to-integer and integer-to-FP conversion insts 533 // require that FA be 31. 534 3: decode FA { 535 31: decode FP_TYPEFUNC { 536 format FloatingPointOperate { 537 0x2f: decode FP_ROUNDMODE { 538 format FPFixedRounding { 539 // "chopped" i.e. round toward zero 540 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }}, 541 Chopped); 542 // round to minus infinity 543 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }}, 544 MinusInfinity); 545 } 546 default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }}); 547 } 548 549 // The cvtts opcode is overloaded to be cvtst if the trap 550 // mode is 2 or 6 (which are not valid otherwise) 551 0x2c: decode FP_FULLFUNC { 552 format BasicOperateWithNopCheck { 553 // trap on denorm version "cvtst/s" is 554 // simulated same as cvtst 555 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }}); 556 } 557 default: cvtts({{ Fc.sf = Fb; }}); 558 } 559 560 // The trapping mode for integer-to-FP conversions 561 // must be /SUI or nothing; /U and /SU are not 562 // allowed. The full set of rounding modes are 563 // supported though. 564 0x3c: decode FP_TRAPMODE { 565 0,7: cvtqs({{ Fc.sf = Fb.sq; }}); 566 } 567 0x3e: decode FP_TRAPMODE { 568 0,7: cvtqt({{ Fc = Fb.sq; }}); 569 } 570 } 571 } 572 } 573 } 574 575 // misc FP operate 576 0x17: decode FP_FULLFUNC { 577 format BasicOperateWithNopCheck { 578 0x010: cvtlq({{ 579 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>; 580 }}); 581 0x030: cvtql({{ 582 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 583 }}); 584 585 // We treat the precise & imprecise trapping versions of 586 // cvtql identically. 587 0x130, 0x530: cvtqlv({{ 588 // To avoid overflow, all the upper 32 bits must match 589 // the sign bit of the lower 32. We code this as 590 // checking the upper 33 bits for all 0s or all 1s. 591 uint64_t sign_bits = Fb.uq<63:31>; 592 if (sign_bits != 0 && sign_bits != mask(33)) 593 fault = new IntegerOverflowFault; 594 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 595 }}); 596 597 0x020: cpys({{ // copy sign 598 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>; 599 }}); 600 0x021: cpysn({{ // copy sign negated 601 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>; 602 }}); 603 0x022: cpyse({{ // copy sign and exponent 604 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>; 605 }}); 606 607 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 608 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 609 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 610 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 611 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 612 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 613 614 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess); 615 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess); 616 } 617 } 618 619 // miscellaneous mem-format ops 620 0x18: decode MEMFUNC { 621 format WarnUnimpl { 622 0x8000: fetch(); 623 0xa000: fetch_m(); 624 0xe800: ecb(); 625 } 626 627 format MiscPrefetch { 628 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 629 {{ xc->writeHint(EA, 64, memAccessFlags); }}, 630 mem_flags = NO_FAULT, 631 inst_flags = [IsMemRef, IsDataPrefetch, 632 IsStore, MemWriteOp]); 633 } 634 635 format BasicOperate { 636 0xc000: rpcc({{ 637#if FULL_SYSTEM 638 /* Rb is a fake dependency so here is a fun way to get 639 * the parser to understand that. 640 */ 641 Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC) + (Rb & 0); 642 643#else 644 Ra = curTick; 645#endif 646 }}, IsUnverifiable); 647 648 // All of the barrier instructions below do nothing in 649 // their execute() methods (hence the empty code blocks). 650 // All of their functionality is hard-coded in the 651 // pipeline based on the flags IsSerializing, 652 // IsMemBarrier, and IsWriteBarrier. In the current 653 // detailed CPU model, the execute() function only gets 654 // called at fetch, so there's no way to generate pipeline 655 // behavior at any other stage. Once we go to an 656 // exec-in-exec CPU model we should be able to get rid of 657 // these flags and implement this behavior via the 658 // execute() methods. 659 660 // trapb is just a barrier on integer traps, where excb is 661 // a barrier on integer and FP traps. "EXCB is thus a 662 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 663 // them the same though. 664 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 665 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 666 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 667 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 668 } 669 670#if FULL_SYSTEM 671 format BasicOperate { 672 0xe000: rc({{ 673 Ra = IntrFlag; 674 IntrFlag = 0; 675 }}, IsNonSpeculative, IsUnverifiable); 676 0xf000: rs({{ 677 Ra = IntrFlag; 678 IntrFlag = 1; 679 }}, IsNonSpeculative, IsUnverifiable); 680 } 681#else 682 format FailUnimpl { 683 0xe000: rc(); 684 0xf000: rs(); 685 } 686#endif 687 } 688 689#if FULL_SYSTEM 690 0x00: CallPal::call_pal({{ 691 if (!palValid || 692 (palPriv 693 && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) { 694 // invalid pal function code, or attempt to do privileged 695 // PAL call in non-kernel mode 696 fault = new UnimplementedOpcodeFault; 697 } 698 else { 699 // check to see if simulator wants to do something special 700 // on this PAL call (including maybe suppress it) 701 bool dopal = xc->simPalCheck(palFunc); 702 703 if (dopal) { 704 xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC); 705 NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE) + palOffset; 706 } 707 } 708 }}, IsNonSpeculative); 709#else 710 0x00: decode PALFUNC { 711 format EmulatedCallPal { 712 0x00: halt ({{ 713 exitSimLoop("halt instruction encountered"); 714 }}, IsNonSpeculative); 715 0x83: callsys({{ 716 xc->syscall(R0); 717 }}, IsSerializeAfter, IsNonSpeculative); 718 // Read uniq reg into ABI return value register (r0) 719 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); 720 // Write uniq reg with value from ABI arg register (r16) 721 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess); 722 } 723 } 724#endif 725 726#if FULL_SYSTEM 727 0x1b: decode PALMODE { 728 0: OpcdecFault::hw_st_quad(); 729 1: decode HW_LDST_QUAD { 730 format HwLoad { 731 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L); 732 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q); 733 } 734 } 735 } 736 737 0x1f: decode PALMODE { 738 0: OpcdecFault::hw_st_cond(); 739 format HwStore { 740 1: decode HW_LDST_COND { 741 0: decode HW_LDST_QUAD { 742 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 743 {{ Mem.ul = Ra<31:0>; }}, L); 744 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 745 {{ Mem.uq = Ra.uq; }}, Q); 746 } 747 748 1: FailUnimpl::hw_st_cond(); 749 } 750 } 751 } 752 753 0x19: decode PALMODE { 754 0: OpcdecFault::hw_mfpr(); 755 format HwMoveIPR { 756 1: hw_mfpr({{ 757 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 758 IprToMiscRegIndex[ipr_index] : -1; 759 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || 760 miscRegIndex >= NumInternalProcRegs) 761 fault = new UnimplementedOpcodeFault; 762 else 763 Ra = xc->readMiscRegWithEffect(miscRegIndex); 764 }}, IsIprAccess); 765 } 766 } 767 768 0x1d: decode PALMODE { 769 0: OpcdecFault::hw_mtpr(); 770 format HwMoveIPR { 771 1: hw_mtpr({{ 772 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 773 IprToMiscRegIndex[ipr_index] : -1; 774 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) || 775 miscRegIndex >= NumInternalProcRegs) 776 fault = new UnimplementedOpcodeFault; 777 else 778 xc->setMiscRegWithEffect(miscRegIndex, Ra); 779 if (traceData) { traceData->setData(Ra); } 780 }}, IsIprAccess); 781 } 782 } 783 784 format BasicOperate { 785 0x1e: decode PALMODE { 786 0: OpcdecFault::hw_rei(); 787 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); 788 } 789 790 // M5 special opcodes use the reserved 0x01 opcode space 791 0x01: decode M5FUNC { 792 0x00: arm({{ 793 AlphaPseudo::arm(xc->tcBase()); 794 }}, IsNonSpeculative); 795 0x01: quiesce({{ 796 AlphaPseudo::quiesce(xc->tcBase()); 797 }}, IsNonSpeculative, IsQuiesce); 798 0x02: quiesceNs({{ 799 AlphaPseudo::quiesceNs(xc->tcBase(), R16); 800 }}, IsNonSpeculative, IsQuiesce); 801 0x03: quiesceCycles({{ 802 AlphaPseudo::quiesceCycles(xc->tcBase(), R16); 803 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 804 0x04: quiesceTime({{ 805 R0 = AlphaPseudo::quiesceTime(xc->tcBase()); 806 }}, IsNonSpeculative, IsUnverifiable); 807 0x10: ivlb({{ 808 warn_once("Obsolete M5 instruction ivlb encountered.\n"); 809 }}); 810 0x11: ivle({{ 811 warn_once("Obsolete M5 instruction ivlb encountered.\n"); 812 }}); 813 0x20: m5exit_old({{ 814 AlphaPseudo::m5exit_old(xc->tcBase()); 815 }}, No_OpClass, IsNonSpeculative); 816 0x21: m5exit({{ 817 AlphaPseudo::m5exit(xc->tcBase(), R16); 818 }}, No_OpClass, IsNonSpeculative); 819 0x31: loadsymbol({{ 820 AlphaPseudo::loadsymbol(xc->tcBase()); 821 }}, No_OpClass, IsNonSpeculative); 822 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }}); 823 0x40: resetstats({{ 824 AlphaPseudo::resetstats(xc->tcBase(), R16, R17); 825 }}, IsNonSpeculative); 826 0x41: dumpstats({{ 827 AlphaPseudo::dumpstats(xc->tcBase(), R16, R17); 828 }}, IsNonSpeculative); 829 0x42: dumpresetstats({{ 830 AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17); 831 }}, IsNonSpeculative); 832 0x43: m5checkpoint({{ 833 AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17); 834 }}, IsNonSpeculative); 835 0x50: m5readfile({{ 836 R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18); 837 }}, IsNonSpeculative); 838 0x51: m5break({{ 839 AlphaPseudo::debugbreak(xc->tcBase()); 840 }}, IsNonSpeculative); 841 0x52: m5switchcpu({{ 842 AlphaPseudo::switchcpu(xc->tcBase()); 843 }}, IsNonSpeculative); 844 0x53: m5addsymbol({{ 845 AlphaPseudo::addsymbol(xc->tcBase(), R16, R17); 846 }}, IsNonSpeculative); 847 0x54: m5panic({{ 848 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 849 }}, IsNonSpeculative); 850 0x55: m5anBegin({{ 851 AlphaPseudo::anBegin(xc->tcBase(), R16); 852 }}, IsNonSpeculative); 853 0x56: m5anWait({{ 854 AlphaPseudo::anWait(xc->tcBase(), R16, R17); 855 }}, IsNonSpeculative); 856 } 857 } 858#endif 859} 860