decoder.isa revision 2284
1955SN/A// -*- mode:c++ -*- 2955SN/A 31762SN/A// Copyright (c) 2003-2006 The Regents of The University of Michigan 4955SN/A// All rights reserved. 5955SN/A// 6955SN/A// Redistribution and use in source and binary forms, with or without 7955SN/A// modification, are permitted provided that the following conditions are 8955SN/A// met: redistributions of source code must retain the above copyright 9955SN/A// notice, this list of conditions and the following disclaimer; 10955SN/A// redistributions in binary form must reproduce the above copyright 11955SN/A// notice, this list of conditions and the following disclaimer in the 12955SN/A// documentation and/or other materials provided with the distribution; 13955SN/A// neither the name of the copyright holders nor the names of its 14955SN/A// contributors may be used to endorse or promote products derived from 15955SN/A// this software without specific prior written permission. 16955SN/A// 17955SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18955SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19955SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20955SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21955SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22955SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23955SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24955SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25955SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26955SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27955SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edudecode OPCODE default Unknown::unknown() { 30955SN/A 31955SN/A format LoadAddress { 32955SN/A 0x08: lda({{ Ra = Rb + disp; }}); 331608SN/A 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 34955SN/A } 35955SN/A 36955SN/A format LoadOrNop { 37955SN/A 0x0a: ldbu({{ Ra.uq = Mem.ub; }}); 38955SN/A 0x0c: ldwu({{ Ra.uq = Mem.uw; }}); 39955SN/A 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 40955SN/A 0x23: ldt({{ Fa = Mem.df; }}); 41955SN/A 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED); 42955SN/A 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED); 43955SN/A 0x20: MiscPrefetch::copy_load({{ EA = Ra; }}, 44955SN/A {{ fault = xc->copySrcTranslate(EA); }}, 45955SN/A inst_flags = [IsMemRef, IsLoad, IsCopy]); 46955SN/A } 47955SN/A 482023SN/A format LoadOrPrefetch { 49955SN/A 0x28: ldl({{ Ra.sl = Mem.sl; }}); 50955SN/A 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT); 51955SN/A // IsFloating flag on lds gets the prefetch to disassemble 52955SN/A // using f31 instead of r31... funcitonally it's unnecessary 53955SN/A 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }}, 54955SN/A pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 55955SN/A } 56955SN/A 57955SN/A format Store { 581031SN/A 0x0e: stb({{ Mem.ub = Ra<7:0>; }}); 59955SN/A 0x0d: stw({{ Mem.uw = Ra<15:0>; }}); 601388SN/A 0x2c: stl({{ Mem.ul = Ra<31:0>; }}); 61955SN/A 0x2d: stq({{ Mem.uq = Ra.uq; }}); 62955SN/A 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 631296SN/A 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 64955SN/A 0x27: stt({{ Mem.df = Fa; }}); 65955SN/A 0x24: MiscPrefetch::copy_store({{ EA = Rb; }}, 66955SN/A {{ fault = xc->copy(EA); }}, 67955SN/A inst_flags = [IsMemRef, IsStore, IsCopy]); 68955SN/A } 69955SN/A 70955SN/A format StoreCond { 71955SN/A 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }}, 72955SN/A {{ 73955SN/A uint64_t tmp = write_result; 74955SN/A // see stq_c 75955SN/A Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 76955SN/A }}, mem_flags = LOCKED); 77955SN/A 0x2f: stq_c({{ Mem.uq = Ra; }}, 78955SN/A {{ 79955SN/A uint64_t tmp = write_result; 80955SN/A // If the write operation returns 0 or 1, then 81955SN/A // this was a conventional store conditional, 82955SN/A // and the value indicates the success/failure 832325SN/A // of the operation. If another value is 841717SN/A // returned, then this was a Turbolaser 852652Ssaidi@eecs.umich.edu // mailbox access, and we don't update the 86955SN/A // result register at all. 872736Sktlim@umich.edu Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 882410SN/A }}, mem_flags = LOCKED); 89955SN/A } 902290SN/A 91955SN/A format IntegerOperate { 922683Sktlim@umich.edu 932683Sktlim@umich.edu 0x10: decode INTFUNC { // integer arithmetic operations 942669Sktlim@umich.edu 952568SN/A 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 962568SN/A 0x40: addlv({{ 972462SN/A uint32_t tmp = Ra.sl + Rb_or_imm.sl; 982568SN/A // signed overflow occurs when operands have same sign 992395SN/A // and sign of result does not match. 1002405SN/A if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1012914Ssaidi@eecs.umich.edu fault = new IntegerOverflowFault; 102955SN/A Rc.sl = tmp; 1032811Srdreslin@umich.edu }}); 1042811Srdreslin@umich.edu 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); 1052811Srdreslin@umich.edu 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }}); 1062811Srdreslin@umich.edu 1072811Srdreslin@umich.edu 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 1082811Srdreslin@umich.edu 0x60: addqv({{ 1092811Srdreslin@umich.edu uint64_t tmp = Ra + Rb_or_imm; 1102811Srdreslin@umich.edu // signed overflow occurs when operands have same sign 1112811Srdreslin@umich.edu // and sign of result does not match. 1122811Srdreslin@umich.edu if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1132811Srdreslin@umich.edu fault = new IntegerOverflowFault; 1142811Srdreslin@umich.edu Rc = tmp; 1152811Srdreslin@umich.edu }}); 1162811Srdreslin@umich.edu 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 1172811Srdreslin@umich.edu 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 1182811Srdreslin@umich.edu 1192814Srdreslin@umich.edu 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }}); 1202811Srdreslin@umich.edu 0x49: sublv({{ 1212811Srdreslin@umich.edu uint32_t tmp = Ra.sl - Rb_or_imm.sl; 1222811Srdreslin@umich.edu // signed overflow detection is same as for add, 1232811Srdreslin@umich.edu // except we need to look at the *complemented* 1242811Srdreslin@umich.edu // sign bit of the subtrahend (Rb), i.e., if the initial 1252811Srdreslin@umich.edu // signs are the *same* then no overflow can occur 1262811Srdreslin@umich.edu if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1272813Srdreslin@umich.edu fault = new IntegerOverflowFault; 1282813Srdreslin@umich.edu Rc.sl = tmp; 129955SN/A }}); 130955SN/A 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); 131955SN/A 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }}); 1322090SN/A 133955SN/A 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 1342763Sstever@eecs.umich.edu 0x69: subqv({{ 135955SN/A uint64_t tmp = Ra - Rb_or_imm; 1361696SN/A // signed overflow detection is same as for add, 137955SN/A // except we need to look at the *complemented* 138955SN/A // sign bit of the subtrahend (Rb), i.e., if the initial 139955SN/A // signs are the *same* then no overflow can occur 1401127SN/A if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 141955SN/A fault = new IntegerOverflowFault; 142955SN/A Rc = tmp; 1432379SN/A }}); 144955SN/A 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 145955SN/A 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 146955SN/A 1472155SN/A 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 1482155SN/A 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }}); 1492155SN/A 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }}); 1502155SN/A 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }}); 1512155SN/A 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }}); 1522155SN/A 1532155SN/A 0x0f: cmpbge({{ 1542155SN/A int hi = 7; 1552155SN/A int lo = 0; 1562155SN/A uint64_t tmp = 0; 1572155SN/A for (int i = 0; i < 8; ++i) { 1582155SN/A tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i; 1592155SN/A hi += 8; 1602155SN/A lo += 8; 1612155SN/A } 1622155SN/A Rc = tmp; 1632155SN/A }}); 1642155SN/A } 1652155SN/A 1662155SN/A 0x11: decode INTFUNC { // integer logical operations 1672155SN/A 1682155SN/A 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 1692155SN/A 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 1702155SN/A 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 1712155SN/A 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 1722155SN/A 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 1732155SN/A 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 1742155SN/A 1752155SN/A // conditional moves 1762155SN/A 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 1772155SN/A 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 1782155SN/A 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 1792155SN/A 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 1802155SN/A 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }}); 1812155SN/A 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }}); 1822155SN/A 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }}); 1832155SN/A 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }}); 1842155SN/A 1852155SN/A // For AMASK, RA must be R31. 1862422SN/A 0x61: decode RA { 1872422SN/A 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 1882422SN/A } 1892422SN/A 1902422SN/A // For IMPLVER, RA must be R31 and the B operand 1912422SN/A // must be the immediate value 1. 1922422SN/A 0x6c: decode RA { 1932397SN/A 31: decode IMM { 1942397SN/A 1: decode INTIMM { 1952422SN/A // return EV5 for FULL_SYSTEM and EV6 otherwise 1962422SN/A 1: implver({{ 197955SN/A#if FULL_SYSTEM 198955SN/A Rc = 1; 199955SN/A#else 200955SN/A Rc = 2; 201955SN/A#endif 202955SN/A }}); 203955SN/A } 204955SN/A } 2051078SN/A } 206955SN/A 207955SN/A#if FULL_SYSTEM 208955SN/A // The mysterious 11.25... 209955SN/A 0x25: WarnUnimpl::eleven25(); 2101917SN/A#endif 211955SN/A } 212955SN/A 213955SN/A 0x12: decode INTFUNC { 214955SN/A 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 215974SN/A 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }}); 216955SN/A 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }}); 217955SN/A 218955SN/A 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 219955SN/A 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 2202566SN/A 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 2212566SN/A 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 222955SN/A 223955SN/A 0x52: mskwh({{ 2242539SN/A int bv = Rb_or_imm<2:0>; 225955SN/A Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 226955SN/A }}); 227955SN/A 0x62: msklh({{ 2281817SN/A int bv = Rb_or_imm<2:0>; 2291154SN/A Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 2301840SN/A }}); 2312522SN/A 0x72: mskqh({{ 2322522SN/A int bv = Rb_or_imm<2:0>; 233955SN/A Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 234955SN/A }}); 235955SN/A 2362539SN/A 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 237955SN/A 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 2382539SN/A 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 239955SN/A 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }}); 2401730SN/A 241955SN/A 0x5a: extwh({{ 242955SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 243955SN/A 0x6a: extlh({{ 2442212SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 245955SN/A 0x7a: extqh({{ 2461040SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 2472507SN/A 2482521SN/A 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 2492521SN/A 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 2502507SN/A 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 2512507SN/A 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 2522989Ssaidi@eecs.umich.edu 2532507SN/A 0x57: inswh({{ 2542521SN/A int bv = Rb_or_imm<2:0>; 2552507SN/A Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0; 2562507SN/A }}); 257955SN/A 0x67: inslh({{ 258955SN/A int bv = Rb_or_imm<2:0>; 259955SN/A Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0; 260955SN/A }}); 261955SN/A 0x77: insqh({{ 262955SN/A int bv = Rb_or_imm<2:0>; 2631742SN/A Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0; 2641742SN/A }}); 2651742SN/A 2661742SN/A 0x30: zap({{ 2671742SN/A uint64_t zapmask = 0; 2681742SN/A for (int i = 0; i < 8; ++i) { 2691742SN/A if (Rb_or_imm<i:>) 2701742SN/A zapmask |= (mask(8) << (i * 8)); 2711742SN/A } 2721742SN/A Rc = Ra & ~zapmask; 2731742SN/A }}); 2741742SN/A 0x31: zapnot({{ 2751742SN/A uint64_t zapmask = 0; 2761742SN/A for (int i = 0; i < 8; ++i) { 2771742SN/A if (!Rb_or_imm<i:>) 2781742SN/A zapmask |= (mask(8) << (i * 8)); 2791742SN/A } 2801742SN/A Rc = Ra & ~zapmask; 2811742SN/A }}); 2821742SN/A } 283955SN/A 284955SN/A 0x13: decode INTFUNC { // integer multiplies 2852520SN/A 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 2862517SN/A 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 2872253SN/A 0x30: umulh({{ 2882253SN/A uint64_t hi, lo; 2892253SN/A mul128(Ra, Rb_or_imm, hi, lo); 2902253SN/A Rc = hi; 2912553SN/A }}, IntMultOp); 2922553SN/A 0x40: mullv({{ 2932553SN/A // 32-bit multiply with trap on overflow 2942553SN/A int64_t Rax = Ra.sl; // sign extended version of Ra.sl 2952507SN/A int64_t Rbx = Rb_or_imm.sl; 2962470SN/A int64_t tmp = Rax * Rbx; 2971744SN/A // To avoid overflow, all the upper 32 bits must match 2981744SN/A // the sign bit of the lower 32. We code this as 2992470SN/A // checking the upper 33 bits for all 0s or all 1s. 3002470SN/A uint64_t sign_bits = tmp<63:31>; 3012470SN/A if (sign_bits != 0 && sign_bits != mask(33)) 3022919Sktlim@umich.edu fault = new IntegerOverflowFault; 3032470SN/A Rc.sl = tmp<31:0>; 3042470SN/A }}, IntMultOp); 3052400SN/A 0x60: mulqv({{ 3062400SN/A // 64-bit multiply with trap on overflow 307955SN/A uint64_t hi, lo; 308955SN/A mul128(Ra, Rb_or_imm, hi, lo); 3092667Sstever@eecs.umich.edu // all the upper 64 bits must match the sign bit of 3102667Sstever@eecs.umich.edu // the lower 64 3112667Sstever@eecs.umich.edu if (!((hi == 0 && lo<63:> == 0) || 3122667Sstever@eecs.umich.edu (hi == mask(64) && lo<63:> == 1))) 3132667Sstever@eecs.umich.edu fault = new IntegerOverflowFault; 3142667Sstever@eecs.umich.edu Rc = lo; 3152037SN/A }}, IntMultOp); 3162037SN/A } 3172037SN/A 3182667Sstever@eecs.umich.edu 0x1c: decode INTFUNC { 3192139SN/A 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 3202667Sstever@eecs.umich.edu 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } 3212155SN/A 0x32: ctlz({{ 3222155SN/A uint64_t count = 0; 3232155SN/A uint64_t temp = Rb; 3242155SN/A if (temp<63:32>) temp >>= 32; else count += 32; 3252155SN/A if (temp<31:16>) temp >>= 16; else count += 16; 3262155SN/A if (temp<15:8>) temp >>= 8; else count += 8; 327955SN/A if (temp<7:4>) temp >>= 4; else count += 4; 3282155SN/A if (temp<3:2>) temp >>= 2; else count += 2; 329955SN/A if (temp<1:1>) temp >>= 1; else count += 1; 330955SN/A if ((temp<0:0>) != 0x1) count += 1; 331955SN/A Rc = count; 3321742SN/A }}, IntAluOp); 3331742SN/A 334955SN/A 0x33: cttz({{ 335955SN/A uint64_t count = 0; 336955SN/A uint64_t temp = Rb; 3371858SN/A if (!(temp<31:0>)) { temp >>= 32; count += 32; } 338955SN/A if (!(temp<15:0>)) { temp >>= 16; count += 16; } 3391858SN/A if (!(temp<7:0>)) { temp >>= 8; count += 8; } 3401858SN/A if (!(temp<3:0>)) { temp >>= 4; count += 4; } 3411858SN/A if (!(temp<1:0>)) { temp >>= 2; count += 2; } 3421085SN/A if (!(temp<0:0> & ULL(0x1))) count += 1; 343955SN/A Rc = count; 344955SN/A }}, IntAluOp); 345955SN/A 346955SN/A format FailUnimpl { 347955SN/A 0x30: ctpop(); 348955SN/A 0x31: perr(); 349955SN/A 0x34: unpkbw(); 350955SN/A 0x35: unpkbl(); 351955SN/A 0x36: pkwb(); 352955SN/A 0x37: pklb(); 353955SN/A 0x38: minsb8(); 354955SN/A 0x39: minsw4(); 3552667Sstever@eecs.umich.edu 0x3a: minub8(); 3561045SN/A 0x3b: minuw4(); 357955SN/A 0x3c: maxub8(); 358955SN/A 0x3d: maxuw4(); 359955SN/A 0x3e: maxsb8(); 360955SN/A 0x3f: maxsw4(); 3611108SN/A } 362955SN/A 363955SN/A format BasicOperateWithNopCheck { 364955SN/A 0x70: decode RB { 365955SN/A 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp); 366955SN/A } 367955SN/A 0x78: decode RB { 368955SN/A 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }}, 369955SN/A FloatCvtOp); 370955SN/A } 371955SN/A } 372955SN/A } 373955SN/A } 374955SN/A 375955SN/A // Conditional branches. 376955SN/A format CondBranch { 377955SN/A 0x39: beq({{ cond = (Ra == 0); }}); 3782655Sstever@eecs.umich.edu 0x3d: bne({{ cond = (Ra != 0); }}); 3792655Sstever@eecs.umich.edu 0x3e: bge({{ cond = (Ra.sq >= 0); }}); 3802655Sstever@eecs.umich.edu 0x3f: bgt({{ cond = (Ra.sq > 0); }}); 3812655Sstever@eecs.umich.edu 0x3b: ble({{ cond = (Ra.sq <= 0); }}); 3822655Sstever@eecs.umich.edu 0x3a: blt({{ cond = (Ra.sq < 0); }}); 3832655Sstever@eecs.umich.edu 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 3842655Sstever@eecs.umich.edu 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 3852655Sstever@eecs.umich.edu 3862655Sstever@eecs.umich.edu 0x31: fbeq({{ cond = (Fa == 0); }}); 3872655Sstever@eecs.umich.edu 0x35: fbne({{ cond = (Fa != 0); }}); 3882655Sstever@eecs.umich.edu 0x36: fbge({{ cond = (Fa >= 0); }}); 3892655Sstever@eecs.umich.edu 0x37: fbgt({{ cond = (Fa > 0); }}); 3902655Sstever@eecs.umich.edu 0x33: fble({{ cond = (Fa <= 0); }}); 3912655Sstever@eecs.umich.edu 0x32: fblt({{ cond = (Fa < 0); }}); 3922655Sstever@eecs.umich.edu } 3932655Sstever@eecs.umich.edu 3942655Sstever@eecs.umich.edu // unconditional branches 3952655Sstever@eecs.umich.edu format UncondBranch { 3962655Sstever@eecs.umich.edu 0x30: br(); 3972655Sstever@eecs.umich.edu 0x34: bsr(IsCall); 3982655Sstever@eecs.umich.edu } 3992655Sstever@eecs.umich.edu 400955SN/A // indirect branches 4012655Sstever@eecs.umich.edu 0x1a: decode JMPFUNC { 4022655Sstever@eecs.umich.edu format Jump { 4032655Sstever@eecs.umich.edu 0: jmp(); 404955SN/A 1: jsr(IsCall); 405955SN/A 2: ret(IsReturn); 4062655Sstever@eecs.umich.edu 3: jsr_coroutine(IsCall, IsReturn); 4072655Sstever@eecs.umich.edu } 408955SN/A } 409955SN/A 4102655Sstever@eecs.umich.edu // Square root and integer-to-FP moves 4112655Sstever@eecs.umich.edu 0x14: decode FP_SHORTFUNC { 4122655Sstever@eecs.umich.edu // Integer to FP register moves must have RB == 31 413955SN/A 0x4: decode RB { 414955SN/A 31: decode FP_FULLFUNC { 4152655Sstever@eecs.umich.edu format BasicOperateWithNopCheck { 4162655Sstever@eecs.umich.edu 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 4172655Sstever@eecs.umich.edu 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 4181869SN/A 0x014: FailUnimpl::itoff(); // VAX-format conversion 4191869SN/A } 420 } 421 } 422 423 // Square root instructions must have FA == 31 424 0xb: decode FA { 425 31: decode FP_TYPEFUNC { 426 format FloatingPointOperate { 427#if SS_COMPATIBLE_FP 428 0x0b: sqrts({{ 429 if (Fb < 0.0) 430 fault = new ArithmeticFault; 431 Fc = sqrt(Fb); 432 }}, FloatSqrtOp); 433#else 434 0x0b: sqrts({{ 435 if (Fb.sf < 0.0) 436 fault = new ArithmeticFault; 437 Fc.sf = sqrt(Fb.sf); 438 }}, FloatSqrtOp); 439#endif 440 0x2b: sqrtt({{ 441 if (Fb < 0.0) 442 fault = new ArithmeticFault; 443 Fc = sqrt(Fb); 444 }}, FloatSqrtOp); 445 } 446 } 447 } 448 449 // VAX-format sqrtf and sqrtg are not implemented 450 0xa: FailUnimpl::sqrtfg(); 451 } 452 453 // IEEE floating point 454 0x16: decode FP_SHORTFUNC_TOP2 { 455 // The top two bits of the short function code break this 456 // space into four groups: binary ops, compares, reserved, and 457 // conversions. See Table 4-12 of AHB. There are different 458 // special cases in these different groups, so we decode on 459 // these top two bits first just to select a decode strategy. 460 // Most of these instructions may have various trapping and 461 // rounding mode flags set; these are decoded in the 462 // FloatingPointDecode template used by the 463 // FloatingPointOperate format. 464 465 // add/sub/mul/div: just decode on the short function code 466 // and source type. All valid trapping and rounding modes apply. 467 0: decode FP_TRAPMODE { 468 // check for valid trapping modes here 469 0,1,5,7: decode FP_TYPEFUNC { 470 format FloatingPointOperate { 471#if SS_COMPATIBLE_FP 472 0x00: adds({{ Fc = Fa + Fb; }}); 473 0x01: subs({{ Fc = Fa - Fb; }}); 474 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 475 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 476#else 477 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }}); 478 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }}); 479 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); 480 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp); 481#endif 482 483 0x20: addt({{ Fc = Fa + Fb; }}); 484 0x21: subt({{ Fc = Fa - Fb; }}); 485 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 486 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 487 } 488 } 489 } 490 491 // Floating-point compare instructions must have the default 492 // rounding mode, and may use the default trapping mode or 493 // /SU. Both trapping modes are treated the same by M5; the 494 // only difference on the real hardware (as far a I can tell) 495 // is that without /SU you'd get an imprecise trap if you 496 // tried to compare a NaN with something else (instead of an 497 // "unordered" result). 498 1: decode FP_FULLFUNC { 499 format BasicOperateWithNopCheck { 500 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 501 FloatCmpOp); 502 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 503 FloatCmpOp); 504 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 505 FloatCmpOp); 506 0x0a4, 0x5a4: cmptun({{ // unordered 507 Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 508 }}, FloatCmpOp); 509 } 510 } 511 512 // The FP-to-integer and integer-to-FP conversion insts 513 // require that FA be 31. 514 3: decode FA { 515 31: decode FP_TYPEFUNC { 516 format FloatingPointOperate { 517 0x2f: decode FP_ROUNDMODE { 518 format FPFixedRounding { 519 // "chopped" i.e. round toward zero 520 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }}, 521 Chopped); 522 // round to minus infinity 523 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }}, 524 MinusInfinity); 525 } 526 default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }}); 527 } 528 529 // The cvtts opcode is overloaded to be cvtst if the trap 530 // mode is 2 or 6 (which are not valid otherwise) 531 0x2c: decode FP_FULLFUNC { 532 format BasicOperateWithNopCheck { 533 // trap on denorm version "cvtst/s" is 534 // simulated same as cvtst 535 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }}); 536 } 537 default: cvtts({{ Fc.sf = Fb; }}); 538 } 539 540 // The trapping mode for integer-to-FP conversions 541 // must be /SUI or nothing; /U and /SU are not 542 // allowed. The full set of rounding modes are 543 // supported though. 544 0x3c: decode FP_TRAPMODE { 545 0,7: cvtqs({{ Fc.sf = Fb.sq; }}); 546 } 547 0x3e: decode FP_TRAPMODE { 548 0,7: cvtqt({{ Fc = Fb.sq; }}); 549 } 550 } 551 } 552 } 553 } 554 555 // misc FP operate 556 0x17: decode FP_FULLFUNC { 557 format BasicOperateWithNopCheck { 558 0x010: cvtlq({{ 559 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>; 560 }}); 561 0x030: cvtql({{ 562 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 563 }}); 564 565 // We treat the precise & imprecise trapping versions of 566 // cvtql identically. 567 0x130, 0x530: cvtqlv({{ 568 // To avoid overflow, all the upper 32 bits must match 569 // the sign bit of the lower 32. We code this as 570 // checking the upper 33 bits for all 0s or all 1s. 571 uint64_t sign_bits = Fb.uq<63:31>; 572 if (sign_bits != 0 && sign_bits != mask(33)) 573 fault = new IntegerOverflowFault; 574 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 575 }}); 576 577 0x020: cpys({{ // copy sign 578 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>; 579 }}); 580 0x021: cpysn({{ // copy sign negated 581 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>; 582 }}); 583 0x022: cpyse({{ // copy sign and exponent 584 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>; 585 }}); 586 587 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 588 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 589 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 590 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 591 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 592 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 593 594 0x024: mt_fpcr({{ FPCR = Fa.uq; }}); 595 0x025: mf_fpcr({{ Fa.uq = FPCR; }}); 596 } 597 } 598 599 // miscellaneous mem-format ops 600 0x18: decode MEMFUNC { 601 format WarnUnimpl { 602 0x8000: fetch(); 603 0xa000: fetch_m(); 604 0xe800: ecb(); 605 } 606 607 format MiscPrefetch { 608 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 609 {{ xc->writeHint(EA, 64, memAccessFlags); }}, 610 mem_flags = NO_FAULT, 611 inst_flags = [IsMemRef, IsDataPrefetch, 612 IsStore, MemWriteOp]); 613 } 614 615 format BasicOperate { 616 0xc000: rpcc({{ 617#if FULL_SYSTEM 618 /* Rb is a fake dependency so here is a fun way to get 619 * the parser to understand that. 620 */ 621 Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0); 622 623#else 624 Ra = curTick; 625#endif 626 }}); 627 628 // All of the barrier instructions below do nothing in 629 // their execute() methods (hence the empty code blocks). 630 // All of their functionality is hard-coded in the 631 // pipeline based on the flags IsSerializing, 632 // IsMemBarrier, and IsWriteBarrier. In the current 633 // detailed CPU model, the execute() function only gets 634 // called at fetch, so there's no way to generate pipeline 635 // behavior at any other stage. Once we go to an 636 // exec-in-exec CPU model we should be able to get rid of 637 // these flags and implement this behavior via the 638 // execute() methods. 639 640 // trapb is just a barrier on integer traps, where excb is 641 // a barrier on integer and FP traps. "EXCB is thus a 642 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 643 // them the same though. 644 0x0000: trapb({{ }}, IsSerializing, No_OpClass); 645 0x0400: excb({{ }}, IsSerializing, No_OpClass); 646 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 647 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 648 } 649 650#if FULL_SYSTEM 651 format BasicOperate { 652 0xe000: rc({{ 653 Ra = xc->readIntrFlag(); 654 xc->setIntrFlag(0); 655 }}, IsNonSpeculative); 656 0xf000: rs({{ 657 Ra = xc->readIntrFlag(); 658 xc->setIntrFlag(1); 659 }}, IsNonSpeculative); 660 } 661#else 662 format FailUnimpl { 663 0xe000: rc(); 664 0xf000: rs(); 665 } 666#endif 667 } 668 669#if FULL_SYSTEM 670 0x00: CallPal::call_pal({{ 671 if (!palValid || 672 (palPriv 673 && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { 674 // invalid pal function code, or attempt to do privileged 675 // PAL call in non-kernel mode 676 fault = new UnimplementedOpcodeFault; 677 } 678 else { 679 // check to see if simulator wants to do something special 680 // on this PAL call (including maybe suppress it) 681 bool dopal = xc->simPalCheck(palFunc); 682 683 if (dopal) { 684 xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC); 685 NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset; 686 } 687 } 688 }}, IsNonSpeculative); 689#else 690 0x00: decode PALFUNC { 691 format EmulatedCallPal { 692 0x00: halt ({{ 693 SimExit(curTick, "halt instruction encountered"); 694 }}, IsNonSpeculative); 695 0x83: callsys({{ 696 xc->syscall(); 697 }}, IsNonSpeculative); 698 // Read uniq reg into ABI return value register (r0) 699 0x9e: rduniq({{ R0 = Runiq; }}); 700 // Write uniq reg with value from ABI arg register (r16) 701 0x9f: wruniq({{ Runiq = R16; }}); 702 } 703 } 704#endif 705 706#if FULL_SYSTEM 707 0x1b: decode PALMODE { 708 0: OpcdecFault::hw_st_quad(); 709 1: decode HW_LDST_QUAD { 710 format HwLoad { 711 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L); 712 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q); 713 } 714 } 715 } 716 717 0x1f: decode PALMODE { 718 0: OpcdecFault::hw_st_cond(); 719 format HwStore { 720 1: decode HW_LDST_COND { 721 0: decode HW_LDST_QUAD { 722 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 723 {{ Mem.ul = Ra<31:0>; }}, L); 724 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 725 {{ Mem.uq = Ra.uq; }}, Q); 726 } 727 728 1: FailUnimpl::hw_st_cond(); 729 } 730 } 731 } 732 733 0x19: decode PALMODE { 734 0: OpcdecFault::hw_mfpr(); 735 format HwMoveIPR { 736 1: hw_mfpr({{ 737 Ra = xc->readMiscRegWithEffect(ipr_index, fault); 738 }}); 739 } 740 } 741 742 0x1d: decode PALMODE { 743 0: OpcdecFault::hw_mtpr(); 744 format HwMoveIPR { 745 1: hw_mtpr({{ 746 xc->setMiscRegWithEffect(ipr_index, Ra); 747 if (traceData) { traceData->setData(Ra); } 748 }}); 749 } 750 } 751 752 format BasicOperate { 753 0x1e: decode PALMODE { 754 0: OpcdecFault::hw_rei(); 755 1:hw_rei({{ xc->hwrei(); }}, IsSerializing); 756 } 757 758 // M5 special opcodes use the reserved 0x01 opcode space 759 0x01: decode M5FUNC { 760 0x00: arm({{ 761 AlphaPseudo::arm(xc->xcBase()); 762 }}, IsNonSpeculative); 763 0x01: quiesce({{ 764 AlphaPseudo::quiesce(xc->xcBase()); 765 }}, IsNonSpeculative); 766 0x02: quiesceNs({{ 767 AlphaPseudo::quiesceNs(xc->xcBase(), R16); 768 }}, IsNonSpeculative); 769 0x03: quiesceCycles({{ 770 AlphaPseudo::quiesceCycles(xc->xcBase(), R16); 771 }}, IsNonSpeculative); 772 0x04: quiesceTime({{ 773 R0 = AlphaPseudo::quiesceTime(xc->xcBase()); 774 }}, IsNonSpeculative); 775 0x10: ivlb({{ 776 AlphaPseudo::ivlb(xc->xcBase()); 777 }}, No_OpClass, IsNonSpeculative); 778 0x11: ivle({{ 779 AlphaPseudo::ivle(xc->xcBase()); 780 }}, No_OpClass, IsNonSpeculative); 781 0x20: m5exit_old({{ 782 AlphaPseudo::m5exit_old(xc->xcBase()); 783 }}, No_OpClass, IsNonSpeculative); 784 0x21: m5exit({{ 785 AlphaPseudo::m5exit(xc->xcBase(), R16); 786 }}, No_OpClass, IsNonSpeculative); 787 0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }}); 788 0x40: resetstats({{ 789 AlphaPseudo::resetstats(xc->xcBase(), R16, R17); 790 }}, IsNonSpeculative); 791 0x41: dumpstats({{ 792 AlphaPseudo::dumpstats(xc->xcBase(), R16, R17); 793 }}, IsNonSpeculative); 794 0x42: dumpresetstats({{ 795 AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17); 796 }}, IsNonSpeculative); 797 0x43: m5checkpoint({{ 798 AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17); 799 }}, IsNonSpeculative); 800 0x50: m5readfile({{ 801 R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18); 802 }}, IsNonSpeculative); 803 0x51: m5break({{ 804 AlphaPseudo::debugbreak(xc->xcBase()); 805 }}, IsNonSpeculative); 806 0x52: m5switchcpu({{ 807 AlphaPseudo::switchcpu(xc->xcBase()); 808 }}, IsNonSpeculative); 809 0x53: m5addsymbol({{ 810 AlphaPseudo::addsymbol(xc->xcBase(), R16, R17); 811 }}, IsNonSpeculative); 812 0x54: m5panic({{ 813 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 814 }}, IsNonSpeculative); 815 816 } 817 } 818#endif 819} 820