13457Sgblack@eecs.umich.edu/* 23457Sgblack@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 33457Sgblack@eecs.umich.edu * All rights reserved. 43457Sgblack@eecs.umich.edu * 53457Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63457Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73457Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83457Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93457Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103457Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113457Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123457Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133457Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143457Sgblack@eecs.umich.edu * this software without specific prior written permission. 153457Sgblack@eecs.umich.edu * 163457Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173457Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183457Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193457Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203457Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213457Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223457Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233457Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243457Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253457Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263457Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273457Sgblack@eecs.umich.edu * 283457Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 293457Sgblack@eecs.umich.edu * Gabe Black 303457Sgblack@eecs.umich.edu */ 313457Sgblack@eecs.umich.edu 323457Sgblack@eecs.umich.edu#ifndef __ARCH_ALPHA_IPR_HH__ 333457Sgblack@eecs.umich.edu#define __ARCH_ALPHA_IPR_HH__ 343457Sgblack@eecs.umich.edu 355569Snate@binkert.orgnamespace AlphaISA { 365569Snate@binkert.org 375569Snate@binkert.org//////////////////////////////////////////////////////////////////////// 385569Snate@binkert.org// 395569Snate@binkert.org// Internal Processor Reigsters 405569Snate@binkert.org// 415569Snate@binkert.orgenum md_ipr_names { 425569Snate@binkert.org RAW_IPR_ISR = 0x100, // interrupt summary 435569Snate@binkert.org RAW_IPR_ITB_TAG = 0x101, // ITLB tag 445569Snate@binkert.org RAW_IPR_ITB_PTE = 0x102, // ITLB page table entry 455569Snate@binkert.org RAW_IPR_ITB_ASN = 0x103, // ITLB address space 465569Snate@binkert.org RAW_IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp 475569Snate@binkert.org RAW_IPR_ITB_IA = 0x105, // ITLB invalidate all 485569Snate@binkert.org RAW_IPR_ITB_IAP = 0x106, // ITLB invalidate all process 495569Snate@binkert.org RAW_IPR_ITB_IS = 0x107, // ITLB invalidate select 505569Snate@binkert.org RAW_IPR_SIRR = 0x108, // software interrupt request 515569Snate@binkert.org RAW_IPR_ASTRR = 0x109, // asynchronous system trap request 525569Snate@binkert.org RAW_IPR_ASTER = 0x10a, // asynchronous system trap enable 535569Snate@binkert.org RAW_IPR_EXC_ADDR = 0x10b, // exception address 545569Snate@binkert.org RAW_IPR_EXC_SUM = 0x10c, // exception summary 555569Snate@binkert.org RAW_IPR_EXC_MASK = 0x10d, // exception mask 565569Snate@binkert.org RAW_IPR_PAL_BASE = 0x10e, // PAL base address 575569Snate@binkert.org RAW_IPR_ICM = 0x10f, // instruction current mode 585569Snate@binkert.org RAW_IPR_IPLR = 0x110, // interrupt priority level 595569Snate@binkert.org RAW_IPR_INTID = 0x111, // interrupt ID 605569Snate@binkert.org RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr 615569Snate@binkert.org RAW_IPR_IVPTBR = 0x113, // virtual page table base 625569Snate@binkert.org RAW_IPR_HWINT_CLR = 0x115, // H/W interrupt clear 635569Snate@binkert.org RAW_IPR_SL_XMIT = 0x116, // serial line transmit 645569Snate@binkert.org RAW_IPR_SL_RCV = 0x117, // serial line receive 655569Snate@binkert.org RAW_IPR_ICSR = 0x118, // instruction control and status 665569Snate@binkert.org RAW_IPR_IC_FLUSH = 0x119, // instruction cache flush control 675569Snate@binkert.org RAW_IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status 685569Snate@binkert.org RAW_IPR_PMCTR = 0x11c, // performance counter 695569Snate@binkert.org 705569Snate@binkert.org // PAL temporary registers... 715569Snate@binkert.org // register meanings gleaned from osfpal.s source code 725569Snate@binkert.org RAW_IPR_PALtemp0 = 0x140, // local scratch 735569Snate@binkert.org RAW_IPR_PALtemp1 = 0x141, // local scratch 745569Snate@binkert.org RAW_IPR_PALtemp2 = 0x142, // entUna 755569Snate@binkert.org RAW_IPR_PALtemp3 = 0x143, // CPU specific impure area pointer 765569Snate@binkert.org RAW_IPR_PALtemp4 = 0x144, // memory management temp 775569Snate@binkert.org RAW_IPR_PALtemp5 = 0x145, // memory management temp 785569Snate@binkert.org RAW_IPR_PALtemp6 = 0x146, // memory management temp 795569Snate@binkert.org RAW_IPR_PALtemp7 = 0x147, // entIF 805569Snate@binkert.org RAW_IPR_PALtemp8 = 0x148, // intmask 815569Snate@binkert.org RAW_IPR_PALtemp9 = 0x149, // entSys 825569Snate@binkert.org RAW_IPR_PALtemp10 = 0x14a, // ?? 835569Snate@binkert.org RAW_IPR_PALtemp11 = 0x14b, // entInt 845569Snate@binkert.org RAW_IPR_PALtemp12 = 0x14c, // entArith 855569Snate@binkert.org RAW_IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL 865569Snate@binkert.org RAW_IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL 875569Snate@binkert.org RAW_IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL 885569Snate@binkert.org RAW_IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> 895569Snate@binkert.org RAW_IPR_PALtemp17 = 0x151, // sysval 905569Snate@binkert.org RAW_IPR_PALtemp18 = 0x152, // usp 915569Snate@binkert.org RAW_IPR_PALtemp19 = 0x153, // ksp 925569Snate@binkert.org RAW_IPR_PALtemp20 = 0x154, // PTBR 935569Snate@binkert.org RAW_IPR_PALtemp21 = 0x155, // entMM 945569Snate@binkert.org RAW_IPR_PALtemp22 = 0x156, // kgp 955569Snate@binkert.org RAW_IPR_PALtemp23 = 0x157, // PCBB 965569Snate@binkert.org 975569Snate@binkert.org RAW_IPR_DTB_ASN = 0x200, // DTLB address space number 985569Snate@binkert.org RAW_IPR_DTB_CM = 0x201, // DTLB current mode 995569Snate@binkert.org RAW_IPR_DTB_TAG = 0x202, // DTLB tag 1005569Snate@binkert.org RAW_IPR_DTB_PTE = 0x203, // DTLB page table entry 1015569Snate@binkert.org RAW_IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary 1025569Snate@binkert.org 1035569Snate@binkert.org RAW_IPR_MM_STAT = 0x205, // data MMU fault status 1045569Snate@binkert.org RAW_IPR_VA = 0x206, // fault virtual address 1055569Snate@binkert.org RAW_IPR_VA_FORM = 0x207, // formatted virtual address 1065569Snate@binkert.org RAW_IPR_MVPTBR = 0x208, // MTU virtual page table base 1075569Snate@binkert.org RAW_IPR_DTB_IAP = 0x209, // DTLB invalidate all process 1085569Snate@binkert.org RAW_IPR_DTB_IA = 0x20a, // DTLB invalidate all 1095569Snate@binkert.org RAW_IPR_DTB_IS = 0x20b, // DTLB invalidate single 1105569Snate@binkert.org RAW_IPR_ALT_MODE = 0x20c, // alternate mode 1115569Snate@binkert.org RAW_IPR_CC = 0x20d, // cycle counter 1125569Snate@binkert.org RAW_IPR_CC_CTL = 0x20e, // cycle counter control 1135569Snate@binkert.org RAW_IPR_MCSR = 0x20f, // MTU control 1145569Snate@binkert.org 1155569Snate@binkert.org RAW_IPR_DC_FLUSH = 0x210, 1165569Snate@binkert.org RAW_IPR_DC_PERR_STAT = 0x212, // Dcache parity error status 1175569Snate@binkert.org RAW_IPR_DC_TEST_CTL = 0x213, // Dcache test tag control 1185569Snate@binkert.org RAW_IPR_DC_TEST_TAG = 0x214, // Dcache test tag 1195569Snate@binkert.org RAW_IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary 1205569Snate@binkert.org RAW_IPR_DC_MODE = 0x216, // Dcache mode 1215569Snate@binkert.org RAW_IPR_MAF_MODE = 0x217, // miss address file mode 1225569Snate@binkert.org 1235569Snate@binkert.org MaxInternalProcRegs // number of IPRs 1245569Snate@binkert.org}; 1255569Snate@binkert.org 1265569Snate@binkert.orgenum MiscRegIpr 1273457Sgblack@eecs.umich.edu{ 1285569Snate@binkert.org //Write only 1295569Snate@binkert.org MinWriteOnlyIpr, 1305569Snate@binkert.org IPR_HWINT_CLR = MinWriteOnlyIpr, 1315569Snate@binkert.org IPR_SL_XMIT, 1325569Snate@binkert.org IPR_DC_FLUSH, 1335569Snate@binkert.org IPR_IC_FLUSH, 1345569Snate@binkert.org IPR_ALT_MODE, 1355569Snate@binkert.org IPR_DTB_IA, 1365569Snate@binkert.org IPR_DTB_IAP, 1375569Snate@binkert.org IPR_ITB_IA, 1385569Snate@binkert.org MaxWriteOnlyIpr, 1395569Snate@binkert.org IPR_ITB_IAP = MaxWriteOnlyIpr, 1403457Sgblack@eecs.umich.edu 1415569Snate@binkert.org //Read only 1425569Snate@binkert.org MinReadOnlyIpr, 1435569Snate@binkert.org IPR_INTID = MinReadOnlyIpr, 1445569Snate@binkert.org IPR_SL_RCV, 1455569Snate@binkert.org IPR_MM_STAT, 1465569Snate@binkert.org IPR_ITB_PTE_TEMP, 1475569Snate@binkert.org MaxReadOnlyIpr, 1485569Snate@binkert.org IPR_DTB_PTE_TEMP = MaxReadOnlyIpr, 1493457Sgblack@eecs.umich.edu 1505569Snate@binkert.org IPR_ISR, 1515569Snate@binkert.org IPR_ITB_TAG, 1525569Snate@binkert.org IPR_ITB_PTE, 1535569Snate@binkert.org IPR_ITB_ASN, 1545569Snate@binkert.org IPR_ITB_IS, 1555569Snate@binkert.org IPR_SIRR, 1565569Snate@binkert.org IPR_ASTRR, 1575569Snate@binkert.org IPR_ASTER, 1585569Snate@binkert.org IPR_EXC_ADDR, 1595569Snate@binkert.org IPR_EXC_SUM, 1605569Snate@binkert.org IPR_EXC_MASK, 1615569Snate@binkert.org IPR_PAL_BASE, 1625569Snate@binkert.org IPR_ICM, 1635569Snate@binkert.org IPR_IPLR, 1645569Snate@binkert.org IPR_IFAULT_VA_FORM, 1655569Snate@binkert.org IPR_IVPTBR, 1665569Snate@binkert.org IPR_ICSR, 1675569Snate@binkert.org IPR_IC_PERR_STAT, 1685569Snate@binkert.org IPR_PMCTR, 1693457Sgblack@eecs.umich.edu 1705569Snate@binkert.org // PAL temporary registers... 1715569Snate@binkert.org // register meanings gleaned from osfpal.s source code 1725569Snate@binkert.org IPR_PALtemp0, 1735569Snate@binkert.org IPR_PALtemp1, 1745569Snate@binkert.org IPR_PALtemp2, 1755569Snate@binkert.org IPR_PALtemp3, 1765569Snate@binkert.org IPR_PALtemp4, 1775569Snate@binkert.org IPR_PALtemp5, 1785569Snate@binkert.org IPR_PALtemp6, 1795569Snate@binkert.org IPR_PALtemp7, 1805569Snate@binkert.org IPR_PALtemp8, 1815569Snate@binkert.org IPR_PALtemp9, 1825569Snate@binkert.org IPR_PALtemp10, 1835569Snate@binkert.org IPR_PALtemp11, 1845569Snate@binkert.org IPR_PALtemp12, 1855569Snate@binkert.org IPR_PALtemp13, 1865569Snate@binkert.org IPR_PALtemp14, 1875569Snate@binkert.org IPR_PALtemp15, 1885569Snate@binkert.org IPR_PALtemp16, 1895569Snate@binkert.org IPR_PALtemp17, 1905569Snate@binkert.org IPR_PALtemp18, 1915569Snate@binkert.org IPR_PALtemp19, 1925569Snate@binkert.org IPR_PALtemp20, 1935569Snate@binkert.org IPR_PALtemp21, 1945569Snate@binkert.org IPR_PALtemp22, 1955569Snate@binkert.org IPR_PALtemp23, 1963457Sgblack@eecs.umich.edu 1975569Snate@binkert.org IPR_DTB_ASN, 1985569Snate@binkert.org IPR_DTB_CM, 1995569Snate@binkert.org IPR_DTB_TAG, 2005569Snate@binkert.org IPR_DTB_PTE, 2013457Sgblack@eecs.umich.edu 2025569Snate@binkert.org IPR_VA, 2035569Snate@binkert.org IPR_VA_FORM, 2045569Snate@binkert.org IPR_MVPTBR, 2055569Snate@binkert.org IPR_DTB_IS, 2065569Snate@binkert.org IPR_CC, 2075569Snate@binkert.org IPR_CC_CTL, 2085569Snate@binkert.org IPR_MCSR, 2093457Sgblack@eecs.umich.edu 2105569Snate@binkert.org IPR_DC_PERR_STAT, 2115569Snate@binkert.org IPR_DC_TEST_CTL, 2125569Snate@binkert.org IPR_DC_TEST_TAG, 2135569Snate@binkert.org IPR_DC_TEST_TAG_TEMP, 2145569Snate@binkert.org IPR_DC_MODE, 2155569Snate@binkert.org IPR_MAF_MODE, 2163457Sgblack@eecs.umich.edu 2175569Snate@binkert.org NumInternalProcRegs // number of IPR registers 2185569Snate@binkert.org}; 2193457Sgblack@eecs.umich.edu 2205569Snate@binkert.orginline bool 2215569Snate@binkert.orgIprIsWritable(int index) 2225569Snate@binkert.org{ 2235569Snate@binkert.org return index < MinReadOnlyIpr || index > MaxReadOnlyIpr; 2243457Sgblack@eecs.umich.edu} 2253457Sgblack@eecs.umich.edu 2265569Snate@binkert.orginline bool 2275569Snate@binkert.orgIprIsReadable(int index) 2285569Snate@binkert.org{ 2295569Snate@binkert.org return index < MinWriteOnlyIpr || index > MaxWriteOnlyIpr; 2305569Snate@binkert.org} 2315569Snate@binkert.org 2325569Snate@binkert.orgextern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs]; 2335569Snate@binkert.orgextern int IprToMiscRegIndex[MaxInternalProcRegs]; 2345569Snate@binkert.org 2355569Snate@binkert.orgvoid initializeIprTable(); 2365569Snate@binkert.org 2375569Snate@binkert.org} // namespace AlphaISA 2385569Snate@binkert.org 2395569Snate@binkert.org#endif // __ARCH_ALPHA_IPR_HH__ 240