1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Gabe Black
30 */
31
32#ifndef __ARCH_ALPHA_IPR_HH__
33#define __ARCH_ALPHA_IPR_HH__
34
35namespace AlphaISA {
36
37////////////////////////////////////////////////////////////////////////
38//
39//  Internal Processor Reigsters
40//
41enum md_ipr_names {
42    RAW_IPR_ISR = 0x100,            // interrupt summary
43    RAW_IPR_ITB_TAG = 0x101,        // ITLB tag
44    RAW_IPR_ITB_PTE = 0x102,        // ITLB page table entry
45    RAW_IPR_ITB_ASN = 0x103,        // ITLB address space
46    RAW_IPR_ITB_PTE_TEMP = 0x104,   // ITLB page table entry temp
47    RAW_IPR_ITB_IA = 0x105,         // ITLB invalidate all
48    RAW_IPR_ITB_IAP = 0x106,        // ITLB invalidate all process
49    RAW_IPR_ITB_IS = 0x107,         // ITLB invalidate select
50    RAW_IPR_SIRR = 0x108,           // software interrupt request
51    RAW_IPR_ASTRR = 0x109,          // asynchronous system trap request
52    RAW_IPR_ASTER = 0x10a,          // asynchronous system trap enable
53    RAW_IPR_EXC_ADDR = 0x10b,       // exception address
54    RAW_IPR_EXC_SUM = 0x10c,        // exception summary
55    RAW_IPR_EXC_MASK = 0x10d,       // exception mask
56    RAW_IPR_PAL_BASE = 0x10e,       // PAL base address
57    RAW_IPR_ICM = 0x10f,            // instruction current mode
58    RAW_IPR_IPLR = 0x110,           // interrupt priority level
59    RAW_IPR_INTID = 0x111,          // interrupt ID
60    RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr
61    RAW_IPR_IVPTBR = 0x113,         // virtual page table base
62    RAW_IPR_HWINT_CLR = 0x115,      // H/W interrupt clear
63    RAW_IPR_SL_XMIT = 0x116,        // serial line transmit
64    RAW_IPR_SL_RCV = 0x117,         // serial line receive
65    RAW_IPR_ICSR = 0x118,           // instruction control and status
66    RAW_IPR_IC_FLUSH = 0x119,       // instruction cache flush control
67    RAW_IPR_IC_PERR_STAT = 0x11a,   // inst cache parity error status
68    RAW_IPR_PMCTR = 0x11c,          // performance counter
69
70    // PAL temporary registers...
71    // register meanings gleaned from osfpal.s source code
72    RAW_IPR_PALtemp0 = 0x140,       // local scratch
73    RAW_IPR_PALtemp1 = 0x141,       // local scratch
74    RAW_IPR_PALtemp2 = 0x142,       // entUna
75    RAW_IPR_PALtemp3 = 0x143,       // CPU specific impure area pointer
76    RAW_IPR_PALtemp4 = 0x144,       // memory management temp
77    RAW_IPR_PALtemp5 = 0x145,       // memory management temp
78    RAW_IPR_PALtemp6 = 0x146,       // memory management temp
79    RAW_IPR_PALtemp7 = 0x147,       // entIF
80    RAW_IPR_PALtemp8 = 0x148,       // intmask
81    RAW_IPR_PALtemp9 = 0x149,       // entSys
82    RAW_IPR_PALtemp10 = 0x14a,      // ??
83    RAW_IPR_PALtemp11 = 0x14b,      // entInt
84    RAW_IPR_PALtemp12 = 0x14c,      // entArith
85    RAW_IPR_PALtemp13 = 0x14d,      // reserved for platform specific PAL
86    RAW_IPR_PALtemp14 = 0x14e,      // reserved for platform specific PAL
87    RAW_IPR_PALtemp15 = 0x14f,      // reserved for platform specific PAL
88    RAW_IPR_PALtemp16 = 0x150,      // scratch / whami<7:0> / mces<4:0>
89    RAW_IPR_PALtemp17 = 0x151,      // sysval
90    RAW_IPR_PALtemp18 = 0x152,      // usp
91    RAW_IPR_PALtemp19 = 0x153,      // ksp
92    RAW_IPR_PALtemp20 = 0x154,      // PTBR
93    RAW_IPR_PALtemp21 = 0x155,      // entMM
94    RAW_IPR_PALtemp22 = 0x156,      // kgp
95    RAW_IPR_PALtemp23 = 0x157,      // PCBB
96
97    RAW_IPR_DTB_ASN = 0x200,        // DTLB address space number
98    RAW_IPR_DTB_CM = 0x201,         // DTLB current mode
99    RAW_IPR_DTB_TAG = 0x202,        // DTLB tag
100    RAW_IPR_DTB_PTE = 0x203,        // DTLB page table entry
101    RAW_IPR_DTB_PTE_TEMP = 0x204,   // DTLB page table entry temporary
102
103    RAW_IPR_MM_STAT = 0x205,        // data MMU fault status
104    RAW_IPR_VA = 0x206,             // fault virtual address
105    RAW_IPR_VA_FORM = 0x207,        // formatted virtual address
106    RAW_IPR_MVPTBR = 0x208,         // MTU virtual page table base
107    RAW_IPR_DTB_IAP = 0x209,        // DTLB invalidate all process
108    RAW_IPR_DTB_IA = 0x20a,         // DTLB invalidate all
109    RAW_IPR_DTB_IS = 0x20b,         // DTLB invalidate single
110    RAW_IPR_ALT_MODE = 0x20c,       // alternate mode
111    RAW_IPR_CC = 0x20d,             // cycle counter
112    RAW_IPR_CC_CTL = 0x20e,         // cycle counter control
113    RAW_IPR_MCSR = 0x20f,           // MTU control
114
115    RAW_IPR_DC_FLUSH = 0x210,
116    RAW_IPR_DC_PERR_STAT = 0x212,   // Dcache parity error status
117    RAW_IPR_DC_TEST_CTL = 0x213,    // Dcache test tag control
118    RAW_IPR_DC_TEST_TAG = 0x214,    // Dcache test tag
119    RAW_IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary
120    RAW_IPR_DC_MODE = 0x216,        // Dcache mode
121    RAW_IPR_MAF_MODE = 0x217,       // miss address file mode
122
123    MaxInternalProcRegs             // number of IPRs
124};
125
126enum MiscRegIpr
127{
128    //Write only
129    MinWriteOnlyIpr,
130    IPR_HWINT_CLR = MinWriteOnlyIpr,
131    IPR_SL_XMIT,
132    IPR_DC_FLUSH,
133    IPR_IC_FLUSH,
134    IPR_ALT_MODE,
135    IPR_DTB_IA,
136    IPR_DTB_IAP,
137    IPR_ITB_IA,
138    MaxWriteOnlyIpr,
139    IPR_ITB_IAP = MaxWriteOnlyIpr,
140
141    //Read only
142    MinReadOnlyIpr,
143    IPR_INTID = MinReadOnlyIpr,
144    IPR_SL_RCV,
145    IPR_MM_STAT,
146    IPR_ITB_PTE_TEMP,
147    MaxReadOnlyIpr,
148    IPR_DTB_PTE_TEMP = MaxReadOnlyIpr,
149
150    IPR_ISR,
151    IPR_ITB_TAG,
152    IPR_ITB_PTE,
153    IPR_ITB_ASN,
154    IPR_ITB_IS,
155    IPR_SIRR,
156    IPR_ASTRR,
157    IPR_ASTER,
158    IPR_EXC_ADDR,
159    IPR_EXC_SUM,
160    IPR_EXC_MASK,
161    IPR_PAL_BASE,
162    IPR_ICM,
163    IPR_IPLR,
164    IPR_IFAULT_VA_FORM,
165    IPR_IVPTBR,
166    IPR_ICSR,
167    IPR_IC_PERR_STAT,
168    IPR_PMCTR,
169
170    // PAL temporary registers...
171    // register meanings gleaned from osfpal.s source code
172    IPR_PALtemp0,
173    IPR_PALtemp1,
174    IPR_PALtemp2,
175    IPR_PALtemp3,
176    IPR_PALtemp4,
177    IPR_PALtemp5,
178    IPR_PALtemp6,
179    IPR_PALtemp7,
180    IPR_PALtemp8,
181    IPR_PALtemp9,
182    IPR_PALtemp10,
183    IPR_PALtemp11,
184    IPR_PALtemp12,
185    IPR_PALtemp13,
186    IPR_PALtemp14,
187    IPR_PALtemp15,
188    IPR_PALtemp16,
189    IPR_PALtemp17,
190    IPR_PALtemp18,
191    IPR_PALtemp19,
192    IPR_PALtemp20,
193    IPR_PALtemp21,
194    IPR_PALtemp22,
195    IPR_PALtemp23,
196
197    IPR_DTB_ASN,
198    IPR_DTB_CM,
199    IPR_DTB_TAG,
200    IPR_DTB_PTE,
201
202    IPR_VA,
203    IPR_VA_FORM,
204    IPR_MVPTBR,
205    IPR_DTB_IS,
206    IPR_CC,
207    IPR_CC_CTL,
208    IPR_MCSR,
209
210    IPR_DC_PERR_STAT,
211    IPR_DC_TEST_CTL,
212    IPR_DC_TEST_TAG,
213    IPR_DC_TEST_TAG_TEMP,
214    IPR_DC_MODE,
215    IPR_MAF_MODE,
216
217    NumInternalProcRegs             // number of IPR registers
218};
219
220inline bool
221IprIsWritable(int index)
222{
223    return index < MinReadOnlyIpr || index > MaxReadOnlyIpr;
224}
225
226inline bool
227IprIsReadable(int index)
228{
229    return index < MinWriteOnlyIpr || index > MaxWriteOnlyIpr;
230}
231
232extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs];
233extern int IprToMiscRegIndex[MaxInternalProcRegs];
234
235void initializeIprTable();
236
237} // namespace AlphaISA
238
239#endif // __ARCH_ALPHA_IPR_HH__
240