ev5.hh revision 5566
12686Sksewell@umich.edu/* 22686Sksewell@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 35268Sksewell@umich.edu * All rights reserved. 45268Sksewell@umich.edu * 55268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65268Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115268Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145268Sksewell@umich.edu * this software without specific prior written permission. 155268Sksewell@umich.edu * 165268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195268Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205268Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215268Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225268Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235268Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245268Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255268Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265268Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275268Sksewell@umich.edu * 285268Sksewell@umich.edu * Authors: Steve Reinhardt 295268Sksewell@umich.edu * Nathan Binkert 302706Sksewell@umich.edu * Ali Saidi 312686Sksewell@umich.edu */ 322686Sksewell@umich.edu 332686Sksewell@umich.edu#ifndef __ARCH_ALPHA_EV5_HH__ 342686Sksewell@umich.edu#define __ARCH_ALPHA_EV5_HH__ 352686Sksewell@umich.edu 362686Sksewell@umich.edu#include "config/alpha_tlaser.hh" 372686Sksewell@umich.edu#include "arch/alpha/isa_traits.hh" 382741Sksewell@umich.edu 392686Sksewell@umich.edunamespace AlphaISA { 404661Sksewell@umich.edu 412686Sksewell@umich.edu#if ALPHA_TLASER 422686Sksewell@umich.educonst uint64_t AsnMask = ULL(0x7f); 432686Sksewell@umich.edu#else 442686Sksewell@umich.educonst uint64_t AsnMask = ULL(0xff); 454661Sksewell@umich.edu#endif 464661Sksewell@umich.edu 472686Sksewell@umich.educonst int VAddrImplBits = 43; 482686Sksewell@umich.educonst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 492686Sksewell@umich.educonst Addr VAddrUnImplMask = ~VAddrImplMask; 504661Sksewell@umich.eduinline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 514661Sksewell@umich.eduinline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 524661Sksewell@umich.eduinline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 534661Sksewell@umich.eduinline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 544661Sksewell@umich.eduinline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 554661Sksewell@umich.edu 564661Sksewell@umich.edu#if ALPHA_TLASER 574661Sksewell@umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 584661Sksewell@umich.educonst int PAddrImplBits = 40; 594661Sksewell@umich.edu#else 604661Sksewell@umich.eduinline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 614661Sksewell@umich.educonst int PAddrImplBits = 44; // for Tsunami 624661Sksewell@umich.edu#endif 634661Sksewell@umich.educonst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 644661Sksewell@umich.educonst Addr PAddrUncachedBit39 = ULL(0x8000000000); 654661Sksewell@umich.educonst Addr PAddrUncachedBit40 = ULL(0x10000000000); 664661Sksewell@umich.educonst Addr PAddrUncachedBit43 = ULL(0x80000000000); 672686Sksewell@umich.educonst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 682686Sksewell@umich.eduinline Addr Phys2K0Seg(Addr addr) 692686Sksewell@umich.edu{ 702686Sksewell@umich.edu#if !ALPHA_TLASER 714661Sksewell@umich.edu if (addr & PAddrUncachedBit43) { 724661Sksewell@umich.edu addr &= PAddrUncachedMask; 734661Sksewell@umich.edu addr |= PAddrUncachedBit40; 744661Sksewell@umich.edu } 755269Sksewell@umich.edu#endif 764661Sksewell@umich.edu return addr | AlphaISA::K0SegBase; 775269Sksewell@umich.edu} 784661Sksewell@umich.edu 794661Sksewell@umich.eduinline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 804661Sksewell@umich.eduinline Addr DTB_PTE_PPN(uint64_t reg) 814661Sksewell@umich.edu{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 824661Sksewell@umich.eduinline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 834661Sksewell@umich.eduinline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 844661Sksewell@umich.eduinline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 854661Sksewell@umich.eduinline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 864661Sksewell@umich.eduinline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 879554Sandreas.hansson@arm.cominline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 889554Sandreas.hansson@arm.com 899554Sandreas.hansson@arm.cominline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 909554Sandreas.hansson@arm.cominline Addr ITB_PTE_PPN(uint64_t reg) 919554Sandreas.hansson@arm.com{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 929554Sandreas.hansson@arm.cominline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 939554Sandreas.hansson@arm.cominline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 949554Sandreas.hansson@arm.cominline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 959554Sandreas.hansson@arm.cominline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 969554Sandreas.hansson@arm.cominline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 979554Sandreas.hansson@arm.com 984661Sksewell@umich.eduinline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 9910196SCurtis.Dunham@arm.com 1006376Sgblack@eecs.umich.eduinline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 1016376Sgblack@eecs.umich.eduinline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 1026376Sgblack@eecs.umich.eduinline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 1034661Sksewell@umich.edu 1046383Sgblack@eecs.umich.eduinline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 1059918Ssteve.reinhardt@amd.cominline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1066383Sgblack@eecs.umich.eduinline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1076383Sgblack@eecs.umich.edu 1086383Sgblack@eecs.umich.educonst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 1094661Sksewell@umich.educonst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 1104661Sksewell@umich.educonst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 11110196SCurtis.Dunham@arm.comconst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 1124661Sksewell@umich.educonst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 1136383Sgblack@eecs.umich.educonst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 1144661Sksewell@umich.eduinline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 1154661Sksewell@umich.eduinline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 1164661Sksewell@umich.edu 1174661Sksewell@umich.educonst Addr PalBase = 0x4000; 11810196SCurtis.Dunham@arm.comconst Addr PalMax = 0x10000; 1192686Sksewell@umich.edu 1204661Sksewell@umich.edu} // namespace AlphaISA 1218607Sgblack@eecs.umich.edu 1224661Sksewell@umich.edu#endif // __ARCH_ALPHA_EV5_HH__ 1234661Sksewell@umich.edu