ev5.hh revision 5566
12440SN/A/* 22440SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32440SN/A * All rights reserved. 42440SN/A * 52440SN/A * Redistribution and use in source and binary forms, with or without 62440SN/A * modification, are permitted provided that the following conditions are 72440SN/A * met: redistributions of source code must retain the above copyright 82440SN/A * notice, this list of conditions and the following disclaimer; 92440SN/A * redistributions in binary form must reproduce the above copyright 102440SN/A * notice, this list of conditions and the following disclaimer in the 112440SN/A * documentation and/or other materials provided with the distribution; 122440SN/A * neither the name of the copyright holders nor the names of its 132440SN/A * contributors may be used to endorse or promote products derived from 142440SN/A * this software without specific prior written permission. 152440SN/A * 162440SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172440SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182440SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192440SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202440SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212440SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222440SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232440SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242440SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252440SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262440SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302440SN/A * Ali Saidi 312440SN/A */ 322440SN/A 332440SN/A#ifndef __ARCH_ALPHA_EV5_HH__ 342440SN/A#define __ARCH_ALPHA_EV5_HH__ 352440SN/A 362440SN/A#include "config/alpha_tlaser.hh" 372972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 382460SN/A 392440SN/Anamespace AlphaISA { 403120Sgblack@eecs.umich.edu 412440SN/A#if ALPHA_TLASER 422440SN/Aconst uint64_t AsnMask = ULL(0x7f); 432440SN/A#else 442440SN/Aconst uint64_t AsnMask = ULL(0xff); 453577Sgblack@eecs.umich.edu#endif 463577Sgblack@eecs.umich.edu 473577Sgblack@eecs.umich.educonst int VAddrImplBits = 43; 483577Sgblack@eecs.umich.educonst Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; 493577Sgblack@eecs.umich.educonst Addr VAddrUnImplMask = ~VAddrImplMask; 503577Sgblack@eecs.umich.eduinline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 512440SN/Ainline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; } 523484Sktlim@umich.eduinline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; } 532440SN/Ainline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } 542440SN/Ainline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } 553484Sktlim@umich.edu 563484Sktlim@umich.edu#if ALPHA_TLASER 572440SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); } 582440SN/Aconst int PAddrImplBits = 40; 592440SN/A#else 602440SN/Ainline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } 612440SN/Aconst int PAddrImplBits = 44; // for Tsunami 622440SN/A#endif 632440SN/Aconst Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; 642467SN/Aconst Addr PAddrUncachedBit39 = ULL(0x8000000000); 652440SN/Aconst Addr PAddrUncachedBit40 = ULL(0x10000000000); 662440SN/Aconst Addr PAddrUncachedBit43 = ULL(0x80000000000); 672440SN/Aconst Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> 682440SN/Ainline Addr Phys2K0Seg(Addr addr) 692467SN/A{ 702440SN/A#if !ALPHA_TLASER 712440SN/A if (addr & PAddrUncachedBit43) { 722440SN/A addr &= PAddrUncachedMask; 732440SN/A addr |= PAddrUncachedBit40; 742467SN/A } 752440SN/A#endif 762440SN/A return addr | AlphaISA::K0SegBase; 772440SN/A} 782440SN/A 792467SN/Ainline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } 802440SN/Ainline Addr DTB_PTE_PPN(uint64_t reg) 812440SN/A{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 822440SN/Ainline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 832440SN/Ainline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } 842467SN/Ainline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 852440SN/Ainline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 862440SN/Ainline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 872440SN/Ainline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 882440SN/A 892440SN/Ainline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } 902467SN/Ainline Addr ITB_PTE_PPN(uint64_t reg) 912440SN/A{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; } 922440SN/Ainline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } 932440SN/Ainline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } 942467SN/Ainline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } 952440SN/Ainline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } 962440SN/Ainline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } 972440SN/A 982440SN/Ainline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } 992440SN/A 1002467SN/Ainline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } 1012440SN/Ainline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } 1022440SN/Ainline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } 1032440SN/A 1042467SN/Ainline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } 1052440SN/Ainline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1062440SN/Ainline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } 1072440SN/A 1082440SN/Aconst uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); 1092440SN/Aconst uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); 1102440SN/Aconst uint64_t MM_STAT_FONW_MASK = ULL(0x0008); 1112440SN/Aconst uint64_t MM_STAT_FONR_MASK = ULL(0x0004); 1122440SN/Aconst uint64_t MM_STAT_ACV_MASK = ULL(0x0002); 1132440SN/Aconst uint64_t MM_STAT_WR_MASK = ULL(0x0001); 1142440SN/Ainline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; } 1152440SN/Ainline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; } 1162440SN/A 1172440SN/Aconst Addr PalBase = 0x4000; 1182440SN/Aconst Addr PalMax = 0x10000; 1192680Sktlim@umich.edu 1202440SN/A} // namespace AlphaISA 1212680Sktlim@umich.edu 1222680Sktlim@umich.edu#endif // __ARCH_ALPHA_EV5_HH__ 1232440SN/A