ev5.cc revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/alpha/tlb.hh"
30#include "arch/alpha/isa_traits.hh"
31#include "arch/alpha/osfpal.hh"
32#include "base/kgdb.h"
33#include "base/remote_gdb.hh"
34#include "base/stats/events.hh"
35#include "config/full_system.hh"
36#include "cpu/base.hh"
37#include "cpu/cpu_exec_context.hh"
38#include "cpu/exec_context.hh"
39#include "kern/kernel_stats.hh"
40#include "sim/debug.hh"
41#include "sim/sim_events.hh"
42
43#if FULL_SYSTEM
44
45using namespace EV5;
46
47////////////////////////////////////////////////////////////////////////
48//
49//  Machine dependent functions
50//
51void
52AlphaISA::initCPU(ExecContext *xc, int cpuId)
53{
54    initIPRs(xc, cpuId);
55
56    xc->setIntReg(16, cpuId);
57    xc->setIntReg(0, cpuId);
58
59    xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
60    xc->setNextPC(xc->readPC() + sizeof(MachInst));
61}
62
63////////////////////////////////////////////////////////////////////////
64//
65//
66//
67void
68AlphaISA::initIPRs(ExecContext *xc, int cpuId)
69{
70    for (int i = 0; i < NumInternalProcRegs; ++i) {
71        xc->setMiscReg(i, 0);
72    }
73
74    xc->setMiscReg(IPR_PAL_BASE, PalBase);
75    xc->setMiscReg(IPR_MCSR, 0x6);
76    xc->setMiscReg(IPR_PALtemp16, cpuId);
77}
78
79
80template <class CPU>
81void
82AlphaISA::processInterrupts(CPU *cpu)
83{
84    //Check if there are any outstanding interrupts
85    //Handle the interrupts
86    int ipl = 0;
87    int summary = 0;
88
89    cpu->checkInterrupts = false;
90
91    if (cpu->readMiscReg(IPR_ASTRR))
92        panic("asynchronous traps not implemented\n");
93
94    if (cpu->readMiscReg(IPR_SIRR)) {
95        for (int i = INTLEVEL_SOFTWARE_MIN;
96             i < INTLEVEL_SOFTWARE_MAX; i++) {
97            if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
98                // See table 4-19 of the 21164 hardware reference
99                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
100                summary |= (ULL(1) << i);
101            }
102        }
103    }
104
105    uint64_t interrupts = cpu->intr_status();
106
107    if (interrupts) {
108        for (int i = INTLEVEL_EXTERNAL_MIN;
109             i < INTLEVEL_EXTERNAL_MAX; i++) {
110            if (interrupts & (ULL(1) << i)) {
111                // See table 4-19 of the 21164 hardware reference
112                ipl = i;
113                summary |= (ULL(1) << i);
114            }
115        }
116    }
117
118    if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
119        cpu->setMiscReg(IPR_ISR, summary);
120        cpu->setMiscReg(IPR_INTID, ipl);
121        cpu->trap(new InterruptFault);
122        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
123                cpu->readMiscReg(IPR_IPLR), ipl, summary);
124    }
125
126}
127
128template <class CPU>
129void
130AlphaISA::zeroRegisters(CPU *cpu)
131{
132    // Insure ISA semantics
133    // (no longer very clean due to the change in setIntReg() in the
134    // cpu model.  Consider changing later.)
135    cpu->cpuXC->setIntReg(ZeroReg, 0);
136    cpu->cpuXC->setFloatReg(ZeroReg, 0.0);
137}
138
139Fault
140CPUExecContext::hwrei()
141{
142    if (!inPalMode())
143        return new UnimplementedOpcodeFault;
144
145    setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
146
147    if (!misspeculating()) {
148        cpu->kernelStats->hwrei();
149
150        cpu->checkInterrupts = true;
151    }
152
153    // FIXME: XXX check for interrupts? XXX
154    return NoFault;
155}
156
157int
158AlphaISA::MiscRegFile::getInstAsid()
159{
160    return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
161}
162
163int
164AlphaISA::MiscRegFile::getDataAsid()
165{
166    return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
167}
168
169AlphaISA::MiscReg
170AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
171{
172    uint64_t retval = 0;	// return value, default 0
173
174    switch (idx) {
175      case AlphaISA::IPR_PALtemp0:
176      case AlphaISA::IPR_PALtemp1:
177      case AlphaISA::IPR_PALtemp2:
178      case AlphaISA::IPR_PALtemp3:
179      case AlphaISA::IPR_PALtemp4:
180      case AlphaISA::IPR_PALtemp5:
181      case AlphaISA::IPR_PALtemp6:
182      case AlphaISA::IPR_PALtemp7:
183      case AlphaISA::IPR_PALtemp8:
184      case AlphaISA::IPR_PALtemp9:
185      case AlphaISA::IPR_PALtemp10:
186      case AlphaISA::IPR_PALtemp11:
187      case AlphaISA::IPR_PALtemp12:
188      case AlphaISA::IPR_PALtemp13:
189      case AlphaISA::IPR_PALtemp14:
190      case AlphaISA::IPR_PALtemp15:
191      case AlphaISA::IPR_PALtemp16:
192      case AlphaISA::IPR_PALtemp17:
193      case AlphaISA::IPR_PALtemp18:
194      case AlphaISA::IPR_PALtemp19:
195      case AlphaISA::IPR_PALtemp20:
196      case AlphaISA::IPR_PALtemp21:
197      case AlphaISA::IPR_PALtemp22:
198      case AlphaISA::IPR_PALtemp23:
199      case AlphaISA::IPR_PAL_BASE:
200
201      case AlphaISA::IPR_IVPTBR:
202      case AlphaISA::IPR_DC_MODE:
203      case AlphaISA::IPR_MAF_MODE:
204      case AlphaISA::IPR_ISR:
205      case AlphaISA::IPR_EXC_ADDR:
206      case AlphaISA::IPR_IC_PERR_STAT:
207      case AlphaISA::IPR_DC_PERR_STAT:
208      case AlphaISA::IPR_MCSR:
209      case AlphaISA::IPR_ASTRR:
210      case AlphaISA::IPR_ASTER:
211      case AlphaISA::IPR_SIRR:
212      case AlphaISA::IPR_ICSR:
213      case AlphaISA::IPR_ICM:
214      case AlphaISA::IPR_DTB_CM:
215      case AlphaISA::IPR_IPLR:
216      case AlphaISA::IPR_INTID:
217      case AlphaISA::IPR_PMCTR:
218        // no side-effect
219        retval = ipr[idx];
220        break;
221
222      case AlphaISA::IPR_CC:
223        retval |= ipr[idx] & ULL(0xffffffff00000000);
224        retval |= xc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
225        break;
226
227      case AlphaISA::IPR_VA:
228        retval = ipr[idx];
229        break;
230
231      case AlphaISA::IPR_VA_FORM:
232      case AlphaISA::IPR_MM_STAT:
233      case AlphaISA::IPR_IFAULT_VA_FORM:
234      case AlphaISA::IPR_EXC_MASK:
235      case AlphaISA::IPR_EXC_SUM:
236        retval = ipr[idx];
237        break;
238
239      case AlphaISA::IPR_DTB_PTE:
240        {
241            AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating());
242
243            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
244            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
245            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
246            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
247            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
248            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
249            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
250        }
251        break;
252
253        // write only registers
254      case AlphaISA::IPR_HWINT_CLR:
255      case AlphaISA::IPR_SL_XMIT:
256      case AlphaISA::IPR_DC_FLUSH:
257      case AlphaISA::IPR_IC_FLUSH:
258      case AlphaISA::IPR_ALT_MODE:
259      case AlphaISA::IPR_DTB_IA:
260      case AlphaISA::IPR_DTB_IAP:
261      case AlphaISA::IPR_ITB_IA:
262      case AlphaISA::IPR_ITB_IAP:
263        fault = new UnimplementedOpcodeFault;
264        break;
265
266      default:
267        // invalid IPR
268        fault = new UnimplementedOpcodeFault;
269        break;
270    }
271
272    return retval;
273}
274
275#ifdef DEBUG
276// Cause the simulator to break when changing to the following IPL
277int break_ipl = -1;
278#endif
279
280Fault
281AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
282{
283    uint64_t old;
284
285    if (xc->misspeculating())
286        return NoFault;
287
288    switch (idx) {
289      case AlphaISA::IPR_PALtemp0:
290      case AlphaISA::IPR_PALtemp1:
291      case AlphaISA::IPR_PALtemp2:
292      case AlphaISA::IPR_PALtemp3:
293      case AlphaISA::IPR_PALtemp4:
294      case AlphaISA::IPR_PALtemp5:
295      case AlphaISA::IPR_PALtemp6:
296      case AlphaISA::IPR_PALtemp7:
297      case AlphaISA::IPR_PALtemp8:
298      case AlphaISA::IPR_PALtemp9:
299      case AlphaISA::IPR_PALtemp10:
300      case AlphaISA::IPR_PALtemp11:
301      case AlphaISA::IPR_PALtemp12:
302      case AlphaISA::IPR_PALtemp13:
303      case AlphaISA::IPR_PALtemp14:
304      case AlphaISA::IPR_PALtemp15:
305      case AlphaISA::IPR_PALtemp16:
306      case AlphaISA::IPR_PALtemp17:
307      case AlphaISA::IPR_PALtemp18:
308      case AlphaISA::IPR_PALtemp19:
309      case AlphaISA::IPR_PALtemp20:
310      case AlphaISA::IPR_PALtemp21:
311      case AlphaISA::IPR_PALtemp22:
312      case AlphaISA::IPR_PAL_BASE:
313      case AlphaISA::IPR_IC_PERR_STAT:
314      case AlphaISA::IPR_DC_PERR_STAT:
315      case AlphaISA::IPR_PMCTR:
316        // write entire quad w/ no side-effect
317        ipr[idx] = val;
318        break;
319
320      case AlphaISA::IPR_CC_CTL:
321        // This IPR resets the cycle counter.  We assume this only
322        // happens once... let's verify that.
323        assert(ipr[idx] == 0);
324        ipr[idx] = 1;
325        break;
326
327      case AlphaISA::IPR_CC:
328        // This IPR only writes the upper 64 bits.  It's ok to write
329        // all 64 here since we mask out the lower 32 in rpcc (see
330        // isa_desc).
331        ipr[idx] = val;
332        break;
333
334      case AlphaISA::IPR_PALtemp23:
335        // write entire quad w/ no side-effect
336        old = ipr[idx];
337        ipr[idx] = val;
338        xc->getCpuPtr()->kernelStats->context(old, val, xc);
339        break;
340
341      case AlphaISA::IPR_DTB_PTE:
342        // write entire quad w/ no side-effect, tag is forthcoming
343        ipr[idx] = val;
344        break;
345
346      case AlphaISA::IPR_EXC_ADDR:
347        // second least significant bit in PC is always zero
348        ipr[idx] = val & ~2;
349        break;
350
351      case AlphaISA::IPR_ASTRR:
352      case AlphaISA::IPR_ASTER:
353        // only write least significant four bits - privilege mask
354        ipr[idx] = val & 0xf;
355        break;
356
357      case AlphaISA::IPR_IPLR:
358#ifdef DEBUG
359        if (break_ipl != -1 && break_ipl == (val & 0x1f))
360            debug_break();
361#endif
362
363        // only write least significant five bits - interrupt level
364        ipr[idx] = val & 0x1f;
365        xc->getCpuPtr()->kernelStats->swpipl(ipr[idx]);
366        break;
367
368      case AlphaISA::IPR_DTB_CM:
369        if (val & 0x18)
370            xc->getCpuPtr()->kernelStats->mode(Kernel::user, xc);
371        else
372            xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
373
374      case AlphaISA::IPR_ICM:
375        // only write two mode bits - processor mode
376        ipr[idx] = val & 0x18;
377        break;
378
379      case AlphaISA::IPR_ALT_MODE:
380        // only write two mode bits - processor mode
381        ipr[idx] = val & 0x18;
382        break;
383
384      case AlphaISA::IPR_MCSR:
385        // more here after optimization...
386        ipr[idx] = val;
387        break;
388
389      case AlphaISA::IPR_SIRR:
390        // only write software interrupt mask
391        ipr[idx] = val & 0x7fff0;
392        break;
393
394      case AlphaISA::IPR_ICSR:
395        ipr[idx] = val & ULL(0xffffff0300);
396        break;
397
398      case AlphaISA::IPR_IVPTBR:
399      case AlphaISA::IPR_MVPTBR:
400        ipr[idx] = val & ULL(0xffffffffc0000000);
401        break;
402
403      case AlphaISA::IPR_DC_TEST_CTL:
404        ipr[idx] = val & 0x1ffb;
405        break;
406
407      case AlphaISA::IPR_DC_MODE:
408      case AlphaISA::IPR_MAF_MODE:
409        ipr[idx] = val & 0x3f;
410        break;
411
412      case AlphaISA::IPR_ITB_ASN:
413        ipr[idx] = val & 0x7f0;
414        break;
415
416      case AlphaISA::IPR_DTB_ASN:
417        ipr[idx] = val & ULL(0xfe00000000000000);
418        break;
419
420      case AlphaISA::IPR_EXC_SUM:
421      case AlphaISA::IPR_EXC_MASK:
422        // any write to this register clears it
423        ipr[idx] = 0;
424        break;
425
426      case AlphaISA::IPR_INTID:
427      case AlphaISA::IPR_SL_RCV:
428      case AlphaISA::IPR_MM_STAT:
429      case AlphaISA::IPR_ITB_PTE_TEMP:
430      case AlphaISA::IPR_DTB_PTE_TEMP:
431        // read-only registers
432        return new UnimplementedOpcodeFault;
433
434      case AlphaISA::IPR_HWINT_CLR:
435      case AlphaISA::IPR_SL_XMIT:
436      case AlphaISA::IPR_DC_FLUSH:
437      case AlphaISA::IPR_IC_FLUSH:
438        // the following are write only
439        ipr[idx] = val;
440        break;
441
442      case AlphaISA::IPR_DTB_IA:
443        // really a control write
444        ipr[idx] = 0;
445
446        xc->getDTBPtr()->flushAll();
447        break;
448
449      case AlphaISA::IPR_DTB_IAP:
450        // really a control write
451        ipr[idx] = 0;
452
453        xc->getDTBPtr()->flushProcesses();
454        break;
455
456      case AlphaISA::IPR_DTB_IS:
457        // really a control write
458        ipr[idx] = val;
459
460        xc->getDTBPtr()->flushAddr(val,
461                                   DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
462        break;
463
464      case AlphaISA::IPR_DTB_TAG: {
465          struct AlphaISA::PTE pte;
466
467          // FIXME: granularity hints NYI...
468          if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
469              panic("PTE GH field != 0");
470
471          // write entire quad
472          ipr[idx] = val;
473
474          // construct PTE for new entry
475          pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
476          pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
477          pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
478          pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
479          pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
480          pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
481          pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
482
483          // insert new TAG/PTE value into data TLB
484          xc->getDTBPtr()->insert(val, pte);
485      }
486        break;
487
488      case AlphaISA::IPR_ITB_PTE: {
489          struct AlphaISA::PTE pte;
490
491          // FIXME: granularity hints NYI...
492          if (ITB_PTE_GH(val) != 0)
493              panic("PTE GH field != 0");
494
495          // write entire quad
496          ipr[idx] = val;
497
498          // construct PTE for new entry
499          pte.ppn = ITB_PTE_PPN(val);
500          pte.xre = ITB_PTE_XRE(val);
501          pte.xwe = 0;
502          pte.fonr = ITB_PTE_FONR(val);
503          pte.fonw = ITB_PTE_FONW(val);
504          pte.asma = ITB_PTE_ASMA(val);
505          pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
506
507          // insert new TAG/PTE value into data TLB
508          xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
509      }
510        break;
511
512      case AlphaISA::IPR_ITB_IA:
513        // really a control write
514        ipr[idx] = 0;
515
516        xc->getITBPtr()->flushAll();
517        break;
518
519      case AlphaISA::IPR_ITB_IAP:
520        // really a control write
521        ipr[idx] = 0;
522
523        xc->getITBPtr()->flushProcesses();
524        break;
525
526      case AlphaISA::IPR_ITB_IS:
527        // really a control write
528        ipr[idx] = val;
529
530        xc->getITBPtr()->flushAddr(val,
531                                   ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
532        break;
533
534      default:
535        // invalid IPR
536        return new UnimplementedOpcodeFault;
537    }
538
539    // no error...
540    return NoFault;
541}
542
543void
544AlphaISA::copyIprs(ExecContext *src, ExecContext *dest)
545{
546    for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
547        dest->setMiscReg(i, src->readMiscReg(i));
548    }
549}
550
551/**
552 * Check for special simulator handling of specific PAL calls.
553 * If return value is false, actual PAL call will be suppressed.
554 */
555bool
556CPUExecContext::simPalCheck(int palFunc)
557{
558    cpu->kernelStats->callpal(palFunc, proxy);
559
560    switch (palFunc) {
561      case PAL::halt:
562        halt();
563        if (--System::numSystemsRunning == 0)
564            new SimExitEvent("all cpus halted");
565        break;
566
567      case PAL::bpt:
568      case PAL::bugchk:
569        if (system->breakpoint())
570            return false;
571        break;
572    }
573
574    return true;
575}
576
577#endif // FULL_SYSTEM
578