ev5.cc revision 2632:1bb2f91485ea
12810SN/A/*
211870Snikos.nikoleris@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan
39347SAndreas.Sandberg@arm.com * All rights reserved.
49347SAndreas.Sandberg@arm.com *
59347SAndreas.Sandberg@arm.com * Redistribution and use in source and binary forms, with or without
69347SAndreas.Sandberg@arm.com * modification, are permitted provided that the following conditions are
79347SAndreas.Sandberg@arm.com * met: redistributions of source code must retain the above copyright
89347SAndreas.Sandberg@arm.com * notice, this list of conditions and the following disclaimer;
99347SAndreas.Sandberg@arm.com * redistributions in binary form must reproduce the above copyright
109347SAndreas.Sandberg@arm.com * notice, this list of conditions and the following disclaimer in the
119347SAndreas.Sandberg@arm.com * documentation and/or other materials provided with the distribution;
129347SAndreas.Sandberg@arm.com * neither the name of the copyright holders nor the names of its
139347SAndreas.Sandberg@arm.com * contributors may be used to endorse or promote products derived from
142810SN/A * this software without specific prior written permission.
152810SN/A *
162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272810SN/A */
282810SN/A
292810SN/A#include "arch/alpha/tlb.hh"
302810SN/A#include "arch/alpha/isa_traits.hh"
312810SN/A#include "arch/alpha/osfpal.hh"
322810SN/A#include "base/kgdb.h"
332810SN/A#include "base/remote_gdb.hh"
342810SN/A#include "base/stats/events.hh"
352810SN/A#include "config/full_system.hh"
362810SN/A#include "cpu/base.hh"
372810SN/A#include "cpu/cpu_exec_context.hh"
382810SN/A#include "cpu/exec_context.hh"
392810SN/A#include "kern/kernel_stats.hh"
402810SN/A#include "sim/debug.hh"
412810SN/A#include "sim/sim_events.hh"
422810SN/A
432810SN/A#if FULL_SYSTEM
442810SN/A
452810SN/Ausing namespace EV5;
462810SN/A
472810SN/A////////////////////////////////////////////////////////////////////////
482810SN/A//
4912492Sodanrc@yahoo.com.br//  Machine dependent functions
5012492Sodanrc@yahoo.com.br//
512810SN/Avoid
522810SN/AAlphaISA::initCPU(ExecContext *xc, int cpuId)
538229Snate@binkert.org{
548229Snate@binkert.org    initIPRs(xc, cpuId);
552810SN/A
5610815Sdavid.guillen@arm.com    xc->setIntReg(16, cpuId);
579796Sprakash.ramrakhyani@arm.com    xc->setIntReg(0, cpuId);
589796Sprakash.ramrakhyani@arm.com
592810SN/A    xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
602810SN/A    xc->setNextPC(xc->readPC() + sizeof(MachInst));
612810SN/A}
622810SN/A
632810SN/A////////////////////////////////////////////////////////////////////////
642810SN/A//
659796Sprakash.ramrakhyani@arm.com//
662810SN/A//
672810SN/Avoid
689796Sprakash.ramrakhyani@arm.comAlphaISA::initIPRs(ExecContext *xc, int cpuId)
699796Sprakash.ramrakhyani@arm.com{
7011893Snikos.nikoleris@arm.com    for (int i = 0; i < NumInternalProcRegs; ++i) {
7111893Snikos.nikoleris@arm.com        xc->setMiscReg(i, 0);
729796Sprakash.ramrakhyani@arm.com    }
739796Sprakash.ramrakhyani@arm.com
7411722Ssophiane.senni@gmail.com    xc->setMiscReg(IPR_PAL_BASE, PalBase);
7511722Ssophiane.senni@gmail.com    xc->setMiscReg(IPR_MCSR, 0x6);
7611722Ssophiane.senni@gmail.com    xc->setMiscReg(IPR_PALtemp16, cpuId);
7711722Ssophiane.senni@gmail.com}
7811722Ssophiane.senni@gmail.com
7911722Ssophiane.senni@gmail.com
8011722Ssophiane.senni@gmail.comtemplate <class CPU>
8110693SMarco.Balboni@ARM.comvoid
822810SN/AAlphaISA::processInterrupts(CPU *cpu)
832810SN/A{
842810SN/A    //Check if there are any outstanding interrupts
852810SN/A    //Handle the interrupts
862810SN/A    int ipl = 0;
872810SN/A    int summary = 0;
882810SN/A
8912513Sodanrc@yahoo.com.br    cpu->checkInterrupts = false;
902810SN/A
912810SN/A    if (cpu->readMiscReg(IPR_ASTRR))
922810SN/A        panic("asynchronous traps not implemented\n");
936978SLisa.Hsu@amd.com
9412553Snikos.nikoleris@arm.com    if (cpu->readMiscReg(IPR_SIRR)) {
956978SLisa.Hsu@amd.com        for (int i = INTLEVEL_SOFTWARE_MIN;
962810SN/A             i < INTLEVEL_SOFTWARE_MAX; i++) {
972810SN/A            if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
9812513Sodanrc@yahoo.com.br                // See table 4-19 of the 21164 hardware reference
992810SN/A                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
1002810SN/A                summary |= (ULL(1) << i);
1012810SN/A            }
1022810SN/A        }
1032810SN/A    }
1045999Snate@binkert.org
1052810SN/A    uint64_t interrupts = cpu->intr_status();
1065999Snate@binkert.org
1072810SN/A    if (interrupts) {
1082810SN/A        for (int i = INTLEVEL_EXTERNAL_MIN;
1095999Snate@binkert.org             i < INTLEVEL_EXTERNAL_MAX; i++) {
1102810SN/A            if (interrupts & (ULL(1) << i)) {
1112810SN/A                // See table 4-19 of the 21164 hardware reference
1122810SN/A                ipl = i;
1132810SN/A                summary |= (ULL(1) << i);
1142810SN/A            }
1152810SN/A        }
1165999Snate@binkert.org    }
1172810SN/A
1182810SN/A    if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
1192810SN/A        cpu->setMiscReg(IPR_ISR, summary);
1202810SN/A        cpu->setMiscReg(IPR_INTID, ipl);
1212810SN/A        cpu->trap(new InterruptFault);
1222810SN/A        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
1232810SN/A                cpu->readMiscReg(IPR_IPLR), ipl, summary);
12412513Sodanrc@yahoo.com.br    }
1255999Snate@binkert.org
1266978SLisa.Hsu@amd.com}
1278833Sdam.sunwoo@arm.com
1286978SLisa.Hsu@amd.comtemplate <class CPU>
1296978SLisa.Hsu@amd.comvoid
1308833Sdam.sunwoo@arm.comAlphaISA::zeroRegisters(CPU *cpu)
1316978SLisa.Hsu@amd.com{
1326978SLisa.Hsu@amd.com    // Insure ISA semantics
13310024Sdam.sunwoo@arm.com    // (no longer very clean due to the change in setIntReg() in the
13410024Sdam.sunwoo@arm.com    // cpu model.  Consider changing later.)
13510024Sdam.sunwoo@arm.com    cpu->cpuXC->setIntReg(ZeroReg, 0);
13610024Sdam.sunwoo@arm.com    cpu->cpuXC->setFloatReg(ZeroReg, 0.0);
13710024Sdam.sunwoo@arm.com}
13810024Sdam.sunwoo@arm.com
13910024Sdam.sunwoo@arm.comFault
14010024Sdam.sunwoo@arm.comCPUExecContext::hwrei()
14110024Sdam.sunwoo@arm.com{
14210025Stimothy.jones@arm.com    if (!inPalMode())
14310025Stimothy.jones@arm.com        return new UnimplementedOpcodeFault;
14410025Stimothy.jones@arm.com
14510025Stimothy.jones@arm.com    setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
14610025Stimothy.jones@arm.com
1472810SN/A    if (!misspeculating()) {
1482810SN/A        cpu->kernelStats->hwrei();
1492810SN/A
1502810SN/A        cpu->checkInterrupts = true;
1512810SN/A    }
1529796Sprakash.ramrakhyani@arm.com
1539796Sprakash.ramrakhyani@arm.com    // FIXME: XXX check for interrupts? XXX
1542810SN/A    return NoFault;
1552810SN/A}
1562810SN/A
1572810SN/Aint
1582810SN/AAlphaISA::MiscRegFile::getInstAsid()
1592810SN/A{
1602810SN/A    return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
1619796Sprakash.ramrakhyani@arm.com}
1622810SN/A
1632810SN/Aint
1642810SN/AAlphaISA::MiscRegFile::getDataAsid()
1652810SN/A{
1662810SN/A    return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
1679796Sprakash.ramrakhyani@arm.com}
1682810SN/A
1699796Sprakash.ramrakhyani@arm.comAlphaISA::MiscReg
1702810SN/AAlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
1712810SN/A{
1722810SN/A    uint64_t retval = 0;	// return value, default 0
1732810SN/A
1742810SN/A    switch (idx) {
1752810SN/A      case AlphaISA::IPR_PALtemp0:
1767612SGene.Wu@arm.com      case AlphaISA::IPR_PALtemp1:
1777612SGene.Wu@arm.com      case AlphaISA::IPR_PALtemp2:
17810024Sdam.sunwoo@arm.com      case AlphaISA::IPR_PALtemp3:
17910024Sdam.sunwoo@arm.com      case AlphaISA::IPR_PALtemp4:
18010024Sdam.sunwoo@arm.com      case AlphaISA::IPR_PALtemp5:
18110024Sdam.sunwoo@arm.com      case AlphaISA::IPR_PALtemp6:
18210024Sdam.sunwoo@arm.com      case AlphaISA::IPR_PALtemp7:
1839663Suri.wiener@arm.com      case AlphaISA::IPR_PALtemp8:
1849663Suri.wiener@arm.com      case AlphaISA::IPR_PALtemp9:
1859663Suri.wiener@arm.com      case AlphaISA::IPR_PALtemp10:
18610815Sdavid.guillen@arm.com      case AlphaISA::IPR_PALtemp11:
18710815Sdavid.guillen@arm.com      case AlphaISA::IPR_PALtemp12:
18810815Sdavid.guillen@arm.com      case AlphaISA::IPR_PALtemp13:
18910815Sdavid.guillen@arm.com      case AlphaISA::IPR_PALtemp14:
19010815Sdavid.guillen@arm.com      case AlphaISA::IPR_PALtemp15:
19110815Sdavid.guillen@arm.com      case AlphaISA::IPR_PALtemp16:
19210815Sdavid.guillen@arm.com      case AlphaISA::IPR_PALtemp17:
19311893Snikos.nikoleris@arm.com      case AlphaISA::IPR_PALtemp18:
19411893Snikos.nikoleris@arm.com      case AlphaISA::IPR_PALtemp19:
19511893Snikos.nikoleris@arm.com      case AlphaISA::IPR_PALtemp20:
19611893Snikos.nikoleris@arm.com      case AlphaISA::IPR_PALtemp21:
19711893Snikos.nikoleris@arm.com      case AlphaISA::IPR_PALtemp22:
19811893Snikos.nikoleris@arm.com      case AlphaISA::IPR_PALtemp23:
19911893Snikos.nikoleris@arm.com      case AlphaISA::IPR_PAL_BASE:
20011893Snikos.nikoleris@arm.com
20111893Snikos.nikoleris@arm.com      case AlphaISA::IPR_IVPTBR:
20211893Snikos.nikoleris@arm.com      case AlphaISA::IPR_DC_MODE:
20310815Sdavid.guillen@arm.com      case AlphaISA::IPR_MAF_MODE:
20410815Sdavid.guillen@arm.com      case AlphaISA::IPR_ISR:
20510815Sdavid.guillen@arm.com      case AlphaISA::IPR_EXC_ADDR:
20610815Sdavid.guillen@arm.com      case AlphaISA::IPR_IC_PERR_STAT:
20710815Sdavid.guillen@arm.com      case AlphaISA::IPR_DC_PERR_STAT:
20810815Sdavid.guillen@arm.com      case AlphaISA::IPR_MCSR:
20911893Snikos.nikoleris@arm.com      case AlphaISA::IPR_ASTRR:
21010815Sdavid.guillen@arm.com      case AlphaISA::IPR_ASTER:
21110815Sdavid.guillen@arm.com      case AlphaISA::IPR_SIRR:
21210941Sdavid.guillen@arm.com      case AlphaISA::IPR_ICSR:
21310941Sdavid.guillen@arm.com      case AlphaISA::IPR_ICM:
21410941Sdavid.guillen@arm.com      case AlphaISA::IPR_DTB_CM:
21510941Sdavid.guillen@arm.com      case AlphaISA::IPR_IPLR:
21610941Sdavid.guillen@arm.com      case AlphaISA::IPR_INTID:
21710941Sdavid.guillen@arm.com      case AlphaISA::IPR_PMCTR:
21810941Sdavid.guillen@arm.com        // no side-effect
21910941Sdavid.guillen@arm.com        retval = ipr[idx];
22010941Sdavid.guillen@arm.com        break;
22110941Sdavid.guillen@arm.com
22210941Sdavid.guillen@arm.com      case AlphaISA::IPR_CC:
22310941Sdavid.guillen@arm.com        retval |= ipr[idx] & ULL(0xffffffff00000000);
22410941Sdavid.guillen@arm.com        retval |= xc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
22510941Sdavid.guillen@arm.com        break;
22610941Sdavid.guillen@arm.com
22710941Sdavid.guillen@arm.com      case AlphaISA::IPR_VA:
22810941Sdavid.guillen@arm.com        retval = ipr[idx];
22910941Sdavid.guillen@arm.com        break;
23010941Sdavid.guillen@arm.com
23110941Sdavid.guillen@arm.com      case AlphaISA::IPR_VA_FORM:
23210941Sdavid.guillen@arm.com      case AlphaISA::IPR_MM_STAT:
23310941Sdavid.guillen@arm.com      case AlphaISA::IPR_IFAULT_VA_FORM:
23410941Sdavid.guillen@arm.com      case AlphaISA::IPR_EXC_MASK:
23510941Sdavid.guillen@arm.com      case AlphaISA::IPR_EXC_SUM:
23610941Sdavid.guillen@arm.com        retval = ipr[idx];
23710941Sdavid.guillen@arm.com        break;
23810941Sdavid.guillen@arm.com
23910815Sdavid.guillen@arm.com      case AlphaISA::IPR_DTB_PTE:
24010815Sdavid.guillen@arm.com        {
24111870Snikos.nikoleris@arm.com            AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating());
24210815Sdavid.guillen@arm.com
24310815Sdavid.guillen@arm.com            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
24410815Sdavid.guillen@arm.com            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
24510815Sdavid.guillen@arm.com            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
24610815Sdavid.guillen@arm.com            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
24710815Sdavid.guillen@arm.com            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
24810815Sdavid.guillen@arm.com            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
24910815Sdavid.guillen@arm.com            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
25010815Sdavid.guillen@arm.com        }
25110815Sdavid.guillen@arm.com        break;
25210815Sdavid.guillen@arm.com
25310815Sdavid.guillen@arm.com        // write only registers
2542810SN/A      case AlphaISA::IPR_HWINT_CLR:
2552810SN/A      case AlphaISA::IPR_SL_XMIT:
2562810SN/A      case AlphaISA::IPR_DC_FLUSH:
2572810SN/A      case AlphaISA::IPR_IC_FLUSH:
2582810SN/A      case AlphaISA::IPR_ALT_MODE:
2592810SN/A      case AlphaISA::IPR_DTB_IA:
2602810SN/A      case AlphaISA::IPR_DTB_IAP:
2612810SN/A      case AlphaISA::IPR_ITB_IA:
2622810SN/A      case AlphaISA::IPR_ITB_IAP:
2632810SN/A        fault = new UnimplementedOpcodeFault;
26410024Sdam.sunwoo@arm.com        break;
26510024Sdam.sunwoo@arm.com
26610024Sdam.sunwoo@arm.com      default:
26710024Sdam.sunwoo@arm.com        // invalid IPR
26810024Sdam.sunwoo@arm.com        fault = new UnimplementedOpcodeFault;
26910024Sdam.sunwoo@arm.com        break;
27010024Sdam.sunwoo@arm.com    }
27110024Sdam.sunwoo@arm.com
27212492Sodanrc@yahoo.com.br    return retval;
273}
274
275#ifdef DEBUG
276// Cause the simulator to break when changing to the following IPL
277int break_ipl = -1;
278#endif
279
280Fault
281AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
282{
283    uint64_t old;
284
285    if (xc->misspeculating())
286        return NoFault;
287
288    switch (idx) {
289      case AlphaISA::IPR_PALtemp0:
290      case AlphaISA::IPR_PALtemp1:
291      case AlphaISA::IPR_PALtemp2:
292      case AlphaISA::IPR_PALtemp3:
293      case AlphaISA::IPR_PALtemp4:
294      case AlphaISA::IPR_PALtemp5:
295      case AlphaISA::IPR_PALtemp6:
296      case AlphaISA::IPR_PALtemp7:
297      case AlphaISA::IPR_PALtemp8:
298      case AlphaISA::IPR_PALtemp9:
299      case AlphaISA::IPR_PALtemp10:
300      case AlphaISA::IPR_PALtemp11:
301      case AlphaISA::IPR_PALtemp12:
302      case AlphaISA::IPR_PALtemp13:
303      case AlphaISA::IPR_PALtemp14:
304      case AlphaISA::IPR_PALtemp15:
305      case AlphaISA::IPR_PALtemp16:
306      case AlphaISA::IPR_PALtemp17:
307      case AlphaISA::IPR_PALtemp18:
308      case AlphaISA::IPR_PALtemp19:
309      case AlphaISA::IPR_PALtemp20:
310      case AlphaISA::IPR_PALtemp21:
311      case AlphaISA::IPR_PALtemp22:
312      case AlphaISA::IPR_PAL_BASE:
313      case AlphaISA::IPR_IC_PERR_STAT:
314      case AlphaISA::IPR_DC_PERR_STAT:
315      case AlphaISA::IPR_PMCTR:
316        // write entire quad w/ no side-effect
317        ipr[idx] = val;
318        break;
319
320      case AlphaISA::IPR_CC_CTL:
321        // This IPR resets the cycle counter.  We assume this only
322        // happens once... let's verify that.
323        assert(ipr[idx] == 0);
324        ipr[idx] = 1;
325        break;
326
327      case AlphaISA::IPR_CC:
328        // This IPR only writes the upper 64 bits.  It's ok to write
329        // all 64 here since we mask out the lower 32 in rpcc (see
330        // isa_desc).
331        ipr[idx] = val;
332        break;
333
334      case AlphaISA::IPR_PALtemp23:
335        // write entire quad w/ no side-effect
336        old = ipr[idx];
337        ipr[idx] = val;
338        xc->getCpuPtr()->kernelStats->context(old, val, xc);
339        break;
340
341      case AlphaISA::IPR_DTB_PTE:
342        // write entire quad w/ no side-effect, tag is forthcoming
343        ipr[idx] = val;
344        break;
345
346      case AlphaISA::IPR_EXC_ADDR:
347        // second least significant bit in PC is always zero
348        ipr[idx] = val & ~2;
349        break;
350
351      case AlphaISA::IPR_ASTRR:
352      case AlphaISA::IPR_ASTER:
353        // only write least significant four bits - privilege mask
354        ipr[idx] = val & 0xf;
355        break;
356
357      case AlphaISA::IPR_IPLR:
358#ifdef DEBUG
359        if (break_ipl != -1 && break_ipl == (val & 0x1f))
360            debug_break();
361#endif
362
363        // only write least significant five bits - interrupt level
364        ipr[idx] = val & 0x1f;
365        xc->getCpuPtr()->kernelStats->swpipl(ipr[idx]);
366        break;
367
368      case AlphaISA::IPR_DTB_CM:
369        if (val & 0x18)
370            xc->getCpuPtr()->kernelStats->mode(Kernel::user, xc);
371        else
372            xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
373
374      case AlphaISA::IPR_ICM:
375        // only write two mode bits - processor mode
376        ipr[idx] = val & 0x18;
377        break;
378
379      case AlphaISA::IPR_ALT_MODE:
380        // only write two mode bits - processor mode
381        ipr[idx] = val & 0x18;
382        break;
383
384      case AlphaISA::IPR_MCSR:
385        // more here after optimization...
386        ipr[idx] = val;
387        break;
388
389      case AlphaISA::IPR_SIRR:
390        // only write software interrupt mask
391        ipr[idx] = val & 0x7fff0;
392        break;
393
394      case AlphaISA::IPR_ICSR:
395        ipr[idx] = val & ULL(0xffffff0300);
396        break;
397
398      case AlphaISA::IPR_IVPTBR:
399      case AlphaISA::IPR_MVPTBR:
400        ipr[idx] = val & ULL(0xffffffffc0000000);
401        break;
402
403      case AlphaISA::IPR_DC_TEST_CTL:
404        ipr[idx] = val & 0x1ffb;
405        break;
406
407      case AlphaISA::IPR_DC_MODE:
408      case AlphaISA::IPR_MAF_MODE:
409        ipr[idx] = val & 0x3f;
410        break;
411
412      case AlphaISA::IPR_ITB_ASN:
413        ipr[idx] = val & 0x7f0;
414        break;
415
416      case AlphaISA::IPR_DTB_ASN:
417        ipr[idx] = val & ULL(0xfe00000000000000);
418        break;
419
420      case AlphaISA::IPR_EXC_SUM:
421      case AlphaISA::IPR_EXC_MASK:
422        // any write to this register clears it
423        ipr[idx] = 0;
424        break;
425
426      case AlphaISA::IPR_INTID:
427      case AlphaISA::IPR_SL_RCV:
428      case AlphaISA::IPR_MM_STAT:
429      case AlphaISA::IPR_ITB_PTE_TEMP:
430      case AlphaISA::IPR_DTB_PTE_TEMP:
431        // read-only registers
432        return new UnimplementedOpcodeFault;
433
434      case AlphaISA::IPR_HWINT_CLR:
435      case AlphaISA::IPR_SL_XMIT:
436      case AlphaISA::IPR_DC_FLUSH:
437      case AlphaISA::IPR_IC_FLUSH:
438        // the following are write only
439        ipr[idx] = val;
440        break;
441
442      case AlphaISA::IPR_DTB_IA:
443        // really a control write
444        ipr[idx] = 0;
445
446        xc->getDTBPtr()->flushAll();
447        break;
448
449      case AlphaISA::IPR_DTB_IAP:
450        // really a control write
451        ipr[idx] = 0;
452
453        xc->getDTBPtr()->flushProcesses();
454        break;
455
456      case AlphaISA::IPR_DTB_IS:
457        // really a control write
458        ipr[idx] = val;
459
460        xc->getDTBPtr()->flushAddr(val,
461                                   DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
462        break;
463
464      case AlphaISA::IPR_DTB_TAG: {
465          struct AlphaISA::PTE pte;
466
467          // FIXME: granularity hints NYI...
468          if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
469              panic("PTE GH field != 0");
470
471          // write entire quad
472          ipr[idx] = val;
473
474          // construct PTE for new entry
475          pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
476          pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
477          pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
478          pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
479          pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
480          pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
481          pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
482
483          // insert new TAG/PTE value into data TLB
484          xc->getDTBPtr()->insert(val, pte);
485      }
486        break;
487
488      case AlphaISA::IPR_ITB_PTE: {
489          struct AlphaISA::PTE pte;
490
491          // FIXME: granularity hints NYI...
492          if (ITB_PTE_GH(val) != 0)
493              panic("PTE GH field != 0");
494
495          // write entire quad
496          ipr[idx] = val;
497
498          // construct PTE for new entry
499          pte.ppn = ITB_PTE_PPN(val);
500          pte.xre = ITB_PTE_XRE(val);
501          pte.xwe = 0;
502          pte.fonr = ITB_PTE_FONR(val);
503          pte.fonw = ITB_PTE_FONW(val);
504          pte.asma = ITB_PTE_ASMA(val);
505          pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
506
507          // insert new TAG/PTE value into data TLB
508          xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
509      }
510        break;
511
512      case AlphaISA::IPR_ITB_IA:
513        // really a control write
514        ipr[idx] = 0;
515
516        xc->getITBPtr()->flushAll();
517        break;
518
519      case AlphaISA::IPR_ITB_IAP:
520        // really a control write
521        ipr[idx] = 0;
522
523        xc->getITBPtr()->flushProcesses();
524        break;
525
526      case AlphaISA::IPR_ITB_IS:
527        // really a control write
528        ipr[idx] = val;
529
530        xc->getITBPtr()->flushAddr(val,
531                                   ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
532        break;
533
534      default:
535        // invalid IPR
536        return new UnimplementedOpcodeFault;
537    }
538
539    // no error...
540    return NoFault;
541}
542
543void
544AlphaISA::copyIprs(ExecContext *src, ExecContext *dest)
545{
546    for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
547        dest->setMiscReg(i, src->readMiscReg(i));
548    }
549}
550
551/**
552 * Check for special simulator handling of specific PAL calls.
553 * If return value is false, actual PAL call will be suppressed.
554 */
555bool
556CPUExecContext::simPalCheck(int palFunc)
557{
558    cpu->kernelStats->callpal(palFunc, proxy);
559
560    switch (palFunc) {
561      case PAL::halt:
562        halt();
563        if (--System::numSystemsRunning == 0)
564            new SimExitEvent("all cpus halted");
565        break;
566
567      case PAL::bpt:
568      case PAL::bugchk:
569        if (system->breakpoint())
570            return false;
571        break;
572    }
573
574    return true;
575}
576
577#endif // FULL_SYSTEM
578