ev5.cc revision 716 
1/* $Id$ */
2
3#include "targetarch/alpha_memory.hh"
4#include "sim/annotation.hh"
5#ifdef DEBUG
6#include "sim/debug.hh"
7#endif
8#include "cpu/exec_context.hh"
9#include "cpu/fast_cpu/fast_cpu.hh"
10#include "sim/sim_events.hh"
11#include "targetarch/isa_traits.hh"
12#include "base/remote_gdb.hh"
13#include "base/kgdb.h"	// for ALPHA_KENTRY_IF
14#include "targetarch/osfpal.hh"
15
16#ifdef FULL_SYSTEM
17
18#ifndef SYSTEM_EV5
19#error This code is only valid for EV5 systems
20#endif
21
22////////////////////////////////////////////////////////////////////////
23//
24//
25//
26void
27AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
28{
29    if (regs->pal_shadow == use_shadow)
30        panic("swap_palshadow: wrong PAL shadow state");
31
32    regs->pal_shadow = use_shadow;
33
34    for (int i = 0; i < NumIntRegs; i++) {
35        if (reg_redir[i]) {
36            IntReg temp = regs->intRegFile[i];
37            regs->intRegFile[i] = regs->palregs[i];
38            regs->palregs[i] = temp;
39        }
40    }
41}
42
43////////////////////////////////////////////////////////////////////////
44//
45//  Machine dependent functions
46//
47void
48AlphaISA::initCPU(RegFile *regs)
49{
50    initIPRs(regs);
51    // CPU comes up with PAL regs enabled
52    swap_palshadow(regs, true);
53
54    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
55    regs->npc = regs->pc + sizeof(MachInst);
56}
57
58////////////////////////////////////////////////////////////////////////
59//
60// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
61//
62Addr
63AlphaISA::fault_addr[Num_Faults] = {
64    0x0000,	/* No_Fault */
65    0x0001,	/* Reset_Fault */
66    0x0401,	/* Machine_Check_Fault */
67    0x0501,	/* Arithmetic_Fault */
68    0x0101,	/* Interrupt_Fault */
69    0x0201,	/* Ndtb_Miss_Fault */
70    0x0281,	/* Pdtb_Miss_Fault */
71    0x0301,	/* Alignment_Fault */
72    0x0381,	/* DTB_Fault_Fault */
73    0x0381,	/* DTB_Acv_Fault */
74    0x0181,	/* ITB_Miss_Fault */
75    0x0181,	/* ITB_Fault_Fault */
76    0x0081,	/* ITB_Acv_Fault */
77    0x0481,	/* Unimplemented_Opcode_Fault */
78    0x0581,	/* Fen_Fault */
79    0x2001,	/* Pal_Fault */
80    0x0501,	/* Integer_Overflow_Fault: maps to Arithmetic_Fault */
81};
82
83const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
84    /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
85    /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
86    /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
87    /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
88
89////////////////////////////////////////////////////////////////////////
90//
91//
92//
93void
94AlphaISA::initIPRs(RegFile *regs)
95{
96    uint64_t *ipr = regs->ipr;
97
98    bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
99    ipr[IPR_PAL_BASE] = PAL_BASE;
100    ipr[IPR_MCSR] = 0x6;
101}
102
103
104template <class XC>
105void
106AlphaISA::processInterrupts(XC *xc)
107{
108    //Check if there are any outstanding interrupts
109    //Handle the interrupts
110    int ipl = 0;
111    int summary = 0;
112    IntReg *ipr = xc->getIprPtr();
113
114    check_interrupts = 0;
115
116    if (ipr[IPR_ASTRR])
117        panic("asynchronous traps not implemented\n");
118
119    if (ipr[IPR_SIRR]) {
120        for (int i = INTLEVEL_SOFTWARE_MIN;
121             i < INTLEVEL_SOFTWARE_MAX; i++) {
122            if (ipr[IPR_SIRR] & (ULL(1) << i)) {
123                // See table 4-19 of the 21164 hardware reference
124                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
125                summary |= (ULL(1) << i);
126            }
127        }
128    }
129
130    uint64_t interrupts = xc->intr_status();
131
132    if (interrupts) {
133        for (int i = INTLEVEL_EXTERNAL_MIN;
134             i < INTLEVEL_EXTERNAL_MAX; i++) {
135            if (interrupts & (ULL(1) << i)) {
136                // See table 4-19 of the 21164 hardware reference
137                ipl = i;
138                summary |= (ULL(1) << i);
139            }
140        }
141    }
142
143    if (ipl && ipl > ipr[IPR_IPLR]) {
144        ipr[IPR_ISR] = summary;
145        ipr[IPR_INTID] = ipl;
146        xc->trap(Interrupt_Fault);
147        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
148                ipr[IPR_IPLR], ipl, summary);
149    }
150
151}
152
153template <class XC>
154void
155AlphaISA::zeroRegisters(XC *xc)
156{
157    // Insure ISA semantics
158    xc->setIntReg(ZeroReg, 0);
159    xc->setFloatRegDouble(ZeroReg, 0.0);
160}
161
162void
163ExecContext::ev5_trap(Fault fault)
164{
165    assert(!misspeculating());
166    kernelStats.fault(fault);
167
168    if (fault == Arithmetic_Fault)
169        panic("Arithmetic traps are unimplemented!");
170
171    AlphaISA::InternalProcReg *ipr = regs.ipr;
172
173    // exception restart address
174    if (fault != Interrupt_Fault || !PC_PAL(regs.pc))
175        ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
176
177    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
178        fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
179        // traps...  skip faulting instruction
180        ipr[AlphaISA::IPR_EXC_ADDR] += 4;
181    }
182
183    if (!PC_PAL(regs.pc))
184        AlphaISA::swap_palshadow(&regs, true);
185
186    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
187    regs.npc = regs.pc + sizeof(MachInst);
188
189    Annotate::Ev5Trap(this, fault);
190}
191
192
193void
194AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
195{
196    InternalProcReg *ipr = regs->ipr;
197    bool use_pc = (fault == No_Fault);
198
199    if (fault == Arithmetic_Fault)
200        panic("arithmetic faults NYI...");
201
202    // compute exception restart address
203    if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
204        // traps...  skip faulting instruction
205        ipr[IPR_EXC_ADDR] = regs->pc + 4;
206    } else {
207        // fault, post fault at excepting instruction
208        ipr[IPR_EXC_ADDR] = regs->pc;
209    }
210
211    // jump to expection address (PAL PC bit set here as well...)
212    if (!use_pc)
213        regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
214    else
215        regs->npc = ipr[IPR_PAL_BASE] + pc;
216
217    // that's it! (orders of magnitude less painful than x86)
218}
219
220bool AlphaISA::check_interrupts = false;
221
222Fault
223ExecContext::hwrei()
224{
225    uint64_t *ipr = regs.ipr;
226
227    if (!PC_PAL(regs.pc))
228        return Unimplemented_Opcode_Fault;
229
230    setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
231
232    if (!misspeculating()) {
233        kernelStats.hwrei();
234
235        if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
236            AlphaISA::swap_palshadow(&regs, false);
237
238        AlphaISA::check_interrupts = true;
239    }
240
241    // FIXME: XXX check for interrupts? XXX
242    return No_Fault;
243}
244
245uint64_t
246ExecContext::readIpr(int idx, Fault &fault)
247{
248    uint64_t *ipr = regs.ipr;
249    uint64_t retval = 0;	// return value, default 0
250
251    switch (idx) {
252      case AlphaISA::IPR_PALtemp0:
253      case AlphaISA::IPR_PALtemp1:
254      case AlphaISA::IPR_PALtemp2:
255      case AlphaISA::IPR_PALtemp3:
256      case AlphaISA::IPR_PALtemp4:
257      case AlphaISA::IPR_PALtemp5:
258      case AlphaISA::IPR_PALtemp6:
259      case AlphaISA::IPR_PALtemp7:
260      case AlphaISA::IPR_PALtemp8:
261      case AlphaISA::IPR_PALtemp9:
262      case AlphaISA::IPR_PALtemp10:
263      case AlphaISA::IPR_PALtemp11:
264      case AlphaISA::IPR_PALtemp12:
265      case AlphaISA::IPR_PALtemp13:
266      case AlphaISA::IPR_PALtemp14:
267      case AlphaISA::IPR_PALtemp15:
268      case AlphaISA::IPR_PALtemp16:
269      case AlphaISA::IPR_PALtemp17:
270      case AlphaISA::IPR_PALtemp18:
271      case AlphaISA::IPR_PALtemp19:
272      case AlphaISA::IPR_PALtemp20:
273      case AlphaISA::IPR_PALtemp21:
274      case AlphaISA::IPR_PALtemp22:
275      case AlphaISA::IPR_PALtemp23:
276      case AlphaISA::IPR_PAL_BASE:
277
278      case AlphaISA::IPR_IVPTBR:
279      case AlphaISA::IPR_DC_MODE:
280      case AlphaISA::IPR_MAF_MODE:
281      case AlphaISA::IPR_ISR:
282      case AlphaISA::IPR_EXC_ADDR:
283      case AlphaISA::IPR_IC_PERR_STAT:
284      case AlphaISA::IPR_DC_PERR_STAT:
285      case AlphaISA::IPR_MCSR:
286      case AlphaISA::IPR_ASTRR:
287      case AlphaISA::IPR_ASTER:
288      case AlphaISA::IPR_SIRR:
289      case AlphaISA::IPR_ICSR:
290      case AlphaISA::IPR_ICM:
291      case AlphaISA::IPR_DTB_CM:
292      case AlphaISA::IPR_IPLR:
293      case AlphaISA::IPR_INTID:
294      case AlphaISA::IPR_PMCTR:
295        // no side-effect
296        retval = ipr[idx];
297        break;
298
299      case AlphaISA::IPR_CC:
300        retval |= ipr[idx] & ULL(0xffffffff00000000);
301        retval |= curTick  & ULL(0x00000000ffffffff);
302        break;
303
304      case AlphaISA::IPR_VA:
305        // SFX: unlocks interrupt status registers
306        retval = ipr[idx];
307
308        if (!misspeculating())
309            regs.intrlock = false;
310        break;
311
312      case AlphaISA::IPR_VA_FORM:
313      case AlphaISA::IPR_MM_STAT:
314      case AlphaISA::IPR_IFAULT_VA_FORM:
315      case AlphaISA::IPR_EXC_MASK:
316      case AlphaISA::IPR_EXC_SUM:
317        retval = ipr[idx];
318        break;
319
320      case AlphaISA::IPR_DTB_PTE:
321        {
322            AlphaISA::PTE &pte = dtb->index(!misspeculating());
323
324            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
325            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
326            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
327            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
328            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
329            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
330            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
331        }
332        break;
333
334        // write only registers
335      case AlphaISA::IPR_HWINT_CLR:
336      case AlphaISA::IPR_SL_XMIT:
337      case AlphaISA::IPR_DC_FLUSH:
338      case AlphaISA::IPR_IC_FLUSH:
339      case AlphaISA::IPR_ALT_MODE:
340      case AlphaISA::IPR_DTB_IA:
341      case AlphaISA::IPR_DTB_IAP:
342      case AlphaISA::IPR_ITB_IA:
343      case AlphaISA::IPR_ITB_IAP:
344        fault = Unimplemented_Opcode_Fault;
345        break;
346
347      default:
348        // invalid IPR
349        fault = Unimplemented_Opcode_Fault;
350        break;
351    }
352
353    return retval;
354}
355
356#ifdef DEBUG
357// Cause the simulator to break when changing to the following IPL
358int break_ipl = -1;
359#endif
360
361Fault
362ExecContext::setIpr(int idx, uint64_t val)
363{
364    uint64_t *ipr = regs.ipr;
365
366    if (misspeculating())
367        return No_Fault;
368
369    switch (idx) {
370      case AlphaISA::IPR_PALtemp0:
371      case AlphaISA::IPR_PALtemp1:
372      case AlphaISA::IPR_PALtemp2:
373      case AlphaISA::IPR_PALtemp3:
374      case AlphaISA::IPR_PALtemp4:
375      case AlphaISA::IPR_PALtemp5:
376      case AlphaISA::IPR_PALtemp6:
377      case AlphaISA::IPR_PALtemp7:
378      case AlphaISA::IPR_PALtemp8:
379      case AlphaISA::IPR_PALtemp9:
380      case AlphaISA::IPR_PALtemp10:
381      case AlphaISA::IPR_PALtemp11:
382      case AlphaISA::IPR_PALtemp12:
383      case AlphaISA::IPR_PALtemp13:
384      case AlphaISA::IPR_PALtemp14:
385      case AlphaISA::IPR_PALtemp15:
386      case AlphaISA::IPR_PALtemp16:
387      case AlphaISA::IPR_PALtemp17:
388      case AlphaISA::IPR_PALtemp18:
389      case AlphaISA::IPR_PALtemp19:
390      case AlphaISA::IPR_PALtemp20:
391      case AlphaISA::IPR_PALtemp21:
392      case AlphaISA::IPR_PALtemp22:
393      case AlphaISA::IPR_PAL_BASE:
394      case AlphaISA::IPR_IC_PERR_STAT:
395      case AlphaISA::IPR_DC_PERR_STAT:
396      case AlphaISA::IPR_PMCTR:
397        // write entire quad w/ no side-effect
398        ipr[idx] = val;
399        break;
400
401      case AlphaISA::IPR_CC_CTL:
402        // This IPR resets the cycle counter.  We assume this only
403        // happens once... let's verify that.
404        assert(ipr[idx] == 0);
405        ipr[idx] = 1;
406        break;
407
408      case AlphaISA::IPR_CC:
409        // This IPR only writes the upper 64 bits.  It's ok to write
410        // all 64 here since we mask out the lower 32 in rpcc (see
411        // isa_desc).
412        ipr[idx] = val;
413        break;
414
415      case AlphaISA::IPR_PALtemp23:
416        // write entire quad w/ no side-effect
417        ipr[idx] = val;
418        kernelStats.context(ipr[idx]);
419        Annotate::Context(this);
420        break;
421
422      case AlphaISA::IPR_DTB_PTE:
423        // write entire quad w/ no side-effect, tag is forthcoming
424        ipr[idx] = val;
425        break;
426
427      case AlphaISA::IPR_EXC_ADDR:
428        // second least significant bit in PC is always zero
429        ipr[idx] = val & ~2;
430        break;
431
432      case AlphaISA::IPR_ASTRR:
433      case AlphaISA::IPR_ASTER:
434        // only write least significant four bits - privilege mask
435        ipr[idx] = val & 0xf;
436        break;
437
438      case AlphaISA::IPR_IPLR:
439#ifdef DEBUG
440        if (break_ipl != -1 && break_ipl == (val & 0x1f))
441            debug_break();
442#endif
443
444        // only write least significant five bits - interrupt level
445        ipr[idx] = val & 0x1f;
446        kernelStats.swpipl(ipr[idx]);
447        Annotate::IPL(this, val & 0x1f);
448        break;
449
450      case AlphaISA::IPR_DTB_CM:
451        Annotate::ChangeMode(this, (val & 0x18) != 0);
452        kernelStats.mode((val & 0x18) != 0);
453
454      case AlphaISA::IPR_ICM:
455        // only write two mode bits - processor mode
456        ipr[idx] = val & 0x18;
457        break;
458
459      case AlphaISA::IPR_ALT_MODE:
460        // only write two mode bits - processor mode
461        ipr[idx] = val & 0x18;
462        break;
463
464      case AlphaISA::IPR_MCSR:
465        // more here after optimization...
466        ipr[idx] = val;
467        break;
468
469      case AlphaISA::IPR_SIRR:
470        // only write software interrupt mask
471        ipr[idx] = val & 0x7fff0;
472        break;
473
474      case AlphaISA::IPR_ICSR:
475        ipr[idx] = val & ULL(0xffffff0300);
476        break;
477
478      case AlphaISA::IPR_IVPTBR:
479      case AlphaISA::IPR_MVPTBR:
480        ipr[idx] = val & ULL(0xffffffffc0000000);
481        break;
482
483      case AlphaISA::IPR_DC_TEST_CTL:
484        ipr[idx] = val & 0x1ffb;
485        break;
486
487      case AlphaISA::IPR_DC_MODE:
488      case AlphaISA::IPR_MAF_MODE:
489        ipr[idx] = val & 0x3f;
490        break;
491
492      case AlphaISA::IPR_ITB_ASN:
493        ipr[idx] = val & 0x7f0;
494        break;
495
496      case AlphaISA::IPR_DTB_ASN:
497        ipr[idx] = val & ULL(0xfe00000000000000);
498        break;
499
500      case AlphaISA::IPR_EXC_SUM:
501      case AlphaISA::IPR_EXC_MASK:
502        // any write to this register clears it
503        ipr[idx] = 0;
504        break;
505
506      case AlphaISA::IPR_INTID:
507      case AlphaISA::IPR_SL_RCV:
508      case AlphaISA::IPR_MM_STAT:
509      case AlphaISA::IPR_ITB_PTE_TEMP:
510      case AlphaISA::IPR_DTB_PTE_TEMP:
511        // read-only registers
512        return Unimplemented_Opcode_Fault;
513
514      case AlphaISA::IPR_HWINT_CLR:
515      case AlphaISA::IPR_SL_XMIT:
516      case AlphaISA::IPR_DC_FLUSH:
517      case AlphaISA::IPR_IC_FLUSH:
518        // the following are write only
519        ipr[idx] = val;
520        break;
521
522      case AlphaISA::IPR_DTB_IA:
523        // really a control write
524        ipr[idx] = 0;
525
526        dtb->flushAll();
527        break;
528
529      case AlphaISA::IPR_DTB_IAP:
530        // really a control write
531        ipr[idx] = 0;
532
533        dtb->flushProcesses();
534        break;
535
536      case AlphaISA::IPR_DTB_IS:
537        // really a control write
538        ipr[idx] = val;
539
540        dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
541        break;
542
543      case AlphaISA::IPR_DTB_TAG: {
544          struct AlphaISA::PTE pte;
545
546          // FIXME: granularity hints NYI...
547          if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
548              panic("PTE GH field != 0");
549
550          // write entire quad
551          ipr[idx] = val;
552
553          // construct PTE for new entry
554          pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
555          pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
556          pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
557          pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
558          pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
559          pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
560          pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
561
562          // insert new TAG/PTE value into data TLB
563          dtb->insert(val, pte);
564      }
565        break;
566
567      case AlphaISA::IPR_ITB_PTE: {
568          struct AlphaISA::PTE pte;
569
570          // FIXME: granularity hints NYI...
571          if (ITB_PTE_GH(val) != 0)
572              panic("PTE GH field != 0");
573
574          // write entire quad
575          ipr[idx] = val;
576
577          // construct PTE for new entry
578          pte.ppn = ITB_PTE_PPN(val);
579          pte.xre = ITB_PTE_XRE(val);
580          pte.xwe = 0;
581          pte.fonr = ITB_PTE_FONR(val);
582          pte.fonw = ITB_PTE_FONW(val);
583          pte.asma = ITB_PTE_ASMA(val);
584          pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
585
586          // insert new TAG/PTE value into data TLB
587          itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
588      }
589        break;
590
591      case AlphaISA::IPR_ITB_IA:
592        // really a control write
593        ipr[idx] = 0;
594
595        itb->flushAll();
596        break;
597
598      case AlphaISA::IPR_ITB_IAP:
599        // really a control write
600        ipr[idx] = 0;
601
602        itb->flushProcesses();
603        break;
604
605      case AlphaISA::IPR_ITB_IS:
606        // really a control write
607        ipr[idx] = val;
608
609        itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
610        break;
611
612      default:
613        // invalid IPR
614        return Unimplemented_Opcode_Fault;
615    }
616
617    // no error...
618    return No_Fault;
619}
620
621/**
622 * Check for special simulator handling of specific PAL calls.
623 * If return value is false, actual PAL call will be suppressed.
624 */
625bool
626ExecContext::simPalCheck(int palFunc)
627{
628    kernelStats.callpal(palFunc);
629
630    switch (palFunc) {
631      case PAL::halt:
632        halt();
633        if (--System::numSystemsRunning == 0)
634            new SimExitEvent("all cpus halted");
635        break;
636
637      case PAL::bpt:
638      case PAL::bugchk:
639        if (system->breakpoint())
640            return false;
641        break;
642    }
643
644    return true;
645}
646
647//Forward instantiation for FastCPU object
648template
649void AlphaISA::processInterrupts(FastCPU *xc);
650
651//Forward instantiation for FastCPU object
652template
653void AlphaISA::zeroRegisters(FastCPU *xc);
654
655#endif // FULL_SYSTEM
656