ev5.cc revision 2261 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/alpha/tlb.hh"
30#include "arch/alpha/isa_traits.hh"
31#include "arch/alpha/osfpal.hh"
32#include "base/kgdb.h"
33#include "base/remote_gdb.hh"
34#include "base/stats/events.hh"
35#include "config/full_system.hh"
36#include "cpu/base.hh"
37#include "cpu/cpu_exec_context.hh"
38#include "cpu/exec_context.hh"
39#include "cpu/fast/cpu.hh"
40#include "kern/kernel_stats.hh"
41#include "sim/debug.hh"
42#include "sim/sim_events.hh"
43
44#if FULL_SYSTEM
45
46using namespace EV5;
47
48////////////////////////////////////////////////////////////////////////
49//
50//  Machine dependent functions
51//
52void
53AlphaISA::initCPU(ExecContext *xc, int cpuId)
54{
55    initIPRs(xc, cpuId);
56
57    xc->setIntReg(16, cpuId);
58    xc->setIntReg(0, cpuId);
59
60    xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
61    xc->setNextPC(xc->readPC() + sizeof(MachInst));
62}
63
64////////////////////////////////////////////////////////////////////////
65//
66//
67//
68void
69AlphaISA::initIPRs(ExecContext *xc, int cpuId)
70{
71    for (int i = 0; i < NumInternalProcRegs; ++i) {
72        xc->setMiscReg(i, 0);
73    }
74
75    xc->setMiscReg(IPR_PAL_BASE, PalBase);
76    xc->setMiscReg(IPR_MCSR, 0x6);
77    xc->setMiscReg(IPR_PALtemp16, cpuId);
78}
79
80
81template <class CPU>
82void
83AlphaISA::processInterrupts(CPU *cpu)
84{
85    //Check if there are any outstanding interrupts
86    //Handle the interrupts
87    int ipl = 0;
88    int summary = 0;
89
90    cpu->checkInterrupts = false;
91
92    if (cpu->readMiscReg(IPR_ASTRR))
93        panic("asynchronous traps not implemented\n");
94
95    if (cpu->readMiscReg(IPR_SIRR)) {
96        for (int i = INTLEVEL_SOFTWARE_MIN;
97             i < INTLEVEL_SOFTWARE_MAX; i++) {
98            if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
99                // See table 4-19 of the 21164 hardware reference
100                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
101                summary |= (ULL(1) << i);
102            }
103        }
104    }
105
106    uint64_t interrupts = cpu->intr_status();
107
108    if (interrupts) {
109        for (int i = INTLEVEL_EXTERNAL_MIN;
110             i < INTLEVEL_EXTERNAL_MAX; i++) {
111            if (interrupts & (ULL(1) << i)) {
112                // See table 4-19 of the 21164 hardware reference
113                ipl = i;
114                summary |= (ULL(1) << i);
115            }
116        }
117    }
118
119    if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
120        cpu->setMiscReg(IPR_ISR, summary);
121        cpu->setMiscReg(IPR_INTID, ipl);
122        cpu->trap(new InterruptFault);
123        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
124                cpu->readMiscReg(IPR_IPLR), ipl, summary);
125    }
126
127}
128
129template <class CPU>
130void
131AlphaISA::zeroRegisters(CPU *cpu)
132{
133    // Insure ISA semantics
134    // (no longer very clean due to the change in setIntReg() in the
135    // cpu model.  Consider changing later.)
136    cpu->cpuXC->setIntReg(ZeroReg, 0);
137    cpu->cpuXC->setFloatRegDouble(ZeroReg, 0.0);
138}
139
140Fault
141CPUExecContext::hwrei()
142{
143    if (!inPalMode())
144        return new UnimplementedOpcodeFault;
145
146    setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
147
148    if (!misspeculating()) {
149        cpu->kernelStats->hwrei();
150
151        cpu->checkInterrupts = true;
152    }
153
154    // FIXME: XXX check for interrupts? XXX
155    return NoFault;
156}
157
158int
159AlphaISA::MiscRegFile::getInstAsid()
160{
161    return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
162}
163
164int
165AlphaISA::MiscRegFile::getDataAsid()
166{
167    return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
168}
169
170AlphaISA::MiscReg
171AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
172{
173    uint64_t retval = 0;	// return value, default 0
174
175    switch (idx) {
176      case AlphaISA::IPR_PALtemp0:
177      case AlphaISA::IPR_PALtemp1:
178      case AlphaISA::IPR_PALtemp2:
179      case AlphaISA::IPR_PALtemp3:
180      case AlphaISA::IPR_PALtemp4:
181      case AlphaISA::IPR_PALtemp5:
182      case AlphaISA::IPR_PALtemp6:
183      case AlphaISA::IPR_PALtemp7:
184      case AlphaISA::IPR_PALtemp8:
185      case AlphaISA::IPR_PALtemp9:
186      case AlphaISA::IPR_PALtemp10:
187      case AlphaISA::IPR_PALtemp11:
188      case AlphaISA::IPR_PALtemp12:
189      case AlphaISA::IPR_PALtemp13:
190      case AlphaISA::IPR_PALtemp14:
191      case AlphaISA::IPR_PALtemp15:
192      case AlphaISA::IPR_PALtemp16:
193      case AlphaISA::IPR_PALtemp17:
194      case AlphaISA::IPR_PALtemp18:
195      case AlphaISA::IPR_PALtemp19:
196      case AlphaISA::IPR_PALtemp20:
197      case AlphaISA::IPR_PALtemp21:
198      case AlphaISA::IPR_PALtemp22:
199      case AlphaISA::IPR_PALtemp23:
200      case AlphaISA::IPR_PAL_BASE:
201
202      case AlphaISA::IPR_IVPTBR:
203      case AlphaISA::IPR_DC_MODE:
204      case AlphaISA::IPR_MAF_MODE:
205      case AlphaISA::IPR_ISR:
206      case AlphaISA::IPR_EXC_ADDR:
207      case AlphaISA::IPR_IC_PERR_STAT:
208      case AlphaISA::IPR_DC_PERR_STAT:
209      case AlphaISA::IPR_MCSR:
210      case AlphaISA::IPR_ASTRR:
211      case AlphaISA::IPR_ASTER:
212      case AlphaISA::IPR_SIRR:
213      case AlphaISA::IPR_ICSR:
214      case AlphaISA::IPR_ICM:
215      case AlphaISA::IPR_DTB_CM:
216      case AlphaISA::IPR_IPLR:
217      case AlphaISA::IPR_INTID:
218      case AlphaISA::IPR_PMCTR:
219        // no side-effect
220        retval = ipr[idx];
221        break;
222
223      case AlphaISA::IPR_CC:
224        retval |= ipr[idx] & ULL(0xffffffff00000000);
225        retval |= xc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
226        break;
227
228      case AlphaISA::IPR_VA:
229        retval = ipr[idx];
230        break;
231
232      case AlphaISA::IPR_VA_FORM:
233      case AlphaISA::IPR_MM_STAT:
234      case AlphaISA::IPR_IFAULT_VA_FORM:
235      case AlphaISA::IPR_EXC_MASK:
236      case AlphaISA::IPR_EXC_SUM:
237        retval = ipr[idx];
238        break;
239
240      case AlphaISA::IPR_DTB_PTE:
241        {
242            AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating());
243
244            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
245            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
246            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
247            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
248            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
249            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
250            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
251        }
252        break;
253
254        // write only registers
255      case AlphaISA::IPR_HWINT_CLR:
256      case AlphaISA::IPR_SL_XMIT:
257      case AlphaISA::IPR_DC_FLUSH:
258      case AlphaISA::IPR_IC_FLUSH:
259      case AlphaISA::IPR_ALT_MODE:
260      case AlphaISA::IPR_DTB_IA:
261      case AlphaISA::IPR_DTB_IAP:
262      case AlphaISA::IPR_ITB_IA:
263      case AlphaISA::IPR_ITB_IAP:
264        fault = new UnimplementedOpcodeFault;
265        break;
266
267      default:
268        // invalid IPR
269        fault = new UnimplementedOpcodeFault;
270        break;
271    }
272
273    return retval;
274}
275
276#ifdef DEBUG
277// Cause the simulator to break when changing to the following IPL
278int break_ipl = -1;
279#endif
280
281Fault
282AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
283{
284    uint64_t old;
285
286    if (xc->misspeculating())
287        return NoFault;
288
289    switch (idx) {
290      case AlphaISA::IPR_PALtemp0:
291      case AlphaISA::IPR_PALtemp1:
292      case AlphaISA::IPR_PALtemp2:
293      case AlphaISA::IPR_PALtemp3:
294      case AlphaISA::IPR_PALtemp4:
295      case AlphaISA::IPR_PALtemp5:
296      case AlphaISA::IPR_PALtemp6:
297      case AlphaISA::IPR_PALtemp7:
298      case AlphaISA::IPR_PALtemp8:
299      case AlphaISA::IPR_PALtemp9:
300      case AlphaISA::IPR_PALtemp10:
301      case AlphaISA::IPR_PALtemp11:
302      case AlphaISA::IPR_PALtemp12:
303      case AlphaISA::IPR_PALtemp13:
304      case AlphaISA::IPR_PALtemp14:
305      case AlphaISA::IPR_PALtemp15:
306      case AlphaISA::IPR_PALtemp16:
307      case AlphaISA::IPR_PALtemp17:
308      case AlphaISA::IPR_PALtemp18:
309      case AlphaISA::IPR_PALtemp19:
310      case AlphaISA::IPR_PALtemp20:
311      case AlphaISA::IPR_PALtemp21:
312      case AlphaISA::IPR_PALtemp22:
313      case AlphaISA::IPR_PAL_BASE:
314      case AlphaISA::IPR_IC_PERR_STAT:
315      case AlphaISA::IPR_DC_PERR_STAT:
316      case AlphaISA::IPR_PMCTR:
317        // write entire quad w/ no side-effect
318        ipr[idx] = val;
319        break;
320
321      case AlphaISA::IPR_CC_CTL:
322        // This IPR resets the cycle counter.  We assume this only
323        // happens once... let's verify that.
324        assert(ipr[idx] == 0);
325        ipr[idx] = 1;
326        break;
327
328      case AlphaISA::IPR_CC:
329        // This IPR only writes the upper 64 bits.  It's ok to write
330        // all 64 here since we mask out the lower 32 in rpcc (see
331        // isa_desc).
332        ipr[idx] = val;
333        break;
334
335      case AlphaISA::IPR_PALtemp23:
336        // write entire quad w/ no side-effect
337        old = ipr[idx];
338        ipr[idx] = val;
339        xc->getCpuPtr()->kernelStats->context(old, val, xc);
340        break;
341
342      case AlphaISA::IPR_DTB_PTE:
343        // write entire quad w/ no side-effect, tag is forthcoming
344        ipr[idx] = val;
345        break;
346
347      case AlphaISA::IPR_EXC_ADDR:
348        // second least significant bit in PC is always zero
349        ipr[idx] = val & ~2;
350        break;
351
352      case AlphaISA::IPR_ASTRR:
353      case AlphaISA::IPR_ASTER:
354        // only write least significant four bits - privilege mask
355        ipr[idx] = val & 0xf;
356        break;
357
358      case AlphaISA::IPR_IPLR:
359#ifdef DEBUG
360        if (break_ipl != -1 && break_ipl == (val & 0x1f))
361            debug_break();
362#endif
363
364        // only write least significant five bits - interrupt level
365        ipr[idx] = val & 0x1f;
366        xc->getCpuPtr()->kernelStats->swpipl(ipr[idx]);
367        break;
368
369      case AlphaISA::IPR_DTB_CM:
370        if (val & 0x18)
371            xc->getCpuPtr()->kernelStats->mode(Kernel::user, xc);
372        else
373            xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
374
375      case AlphaISA::IPR_ICM:
376        // only write two mode bits - processor mode
377        ipr[idx] = val & 0x18;
378        break;
379
380      case AlphaISA::IPR_ALT_MODE:
381        // only write two mode bits - processor mode
382        ipr[idx] = val & 0x18;
383        break;
384
385      case AlphaISA::IPR_MCSR:
386        // more here after optimization...
387        ipr[idx] = val;
388        break;
389
390      case AlphaISA::IPR_SIRR:
391        // only write software interrupt mask
392        ipr[idx] = val & 0x7fff0;
393        break;
394
395      case AlphaISA::IPR_ICSR:
396        ipr[idx] = val & ULL(0xffffff0300);
397        break;
398
399      case AlphaISA::IPR_IVPTBR:
400      case AlphaISA::IPR_MVPTBR:
401        ipr[idx] = val & ULL(0xffffffffc0000000);
402        break;
403
404      case AlphaISA::IPR_DC_TEST_CTL:
405        ipr[idx] = val & 0x1ffb;
406        break;
407
408      case AlphaISA::IPR_DC_MODE:
409      case AlphaISA::IPR_MAF_MODE:
410        ipr[idx] = val & 0x3f;
411        break;
412
413      case AlphaISA::IPR_ITB_ASN:
414        ipr[idx] = val & 0x7f0;
415        break;
416
417      case AlphaISA::IPR_DTB_ASN:
418        ipr[idx] = val & ULL(0xfe00000000000000);
419        break;
420
421      case AlphaISA::IPR_EXC_SUM:
422      case AlphaISA::IPR_EXC_MASK:
423        // any write to this register clears it
424        ipr[idx] = 0;
425        break;
426
427      case AlphaISA::IPR_INTID:
428      case AlphaISA::IPR_SL_RCV:
429      case AlphaISA::IPR_MM_STAT:
430      case AlphaISA::IPR_ITB_PTE_TEMP:
431      case AlphaISA::IPR_DTB_PTE_TEMP:
432        // read-only registers
433        return new UnimplementedOpcodeFault;
434
435      case AlphaISA::IPR_HWINT_CLR:
436      case AlphaISA::IPR_SL_XMIT:
437      case AlphaISA::IPR_DC_FLUSH:
438      case AlphaISA::IPR_IC_FLUSH:
439        // the following are write only
440        ipr[idx] = val;
441        break;
442
443      case AlphaISA::IPR_DTB_IA:
444        // really a control write
445        ipr[idx] = 0;
446
447        xc->getDTBPtr()->flushAll();
448        break;
449
450      case AlphaISA::IPR_DTB_IAP:
451        // really a control write
452        ipr[idx] = 0;
453
454        xc->getDTBPtr()->flushProcesses();
455        break;
456
457      case AlphaISA::IPR_DTB_IS:
458        // really a control write
459        ipr[idx] = val;
460
461        xc->getDTBPtr()->flushAddr(val,
462                                   DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
463        break;
464
465      case AlphaISA::IPR_DTB_TAG: {
466          struct AlphaISA::PTE pte;
467
468          // FIXME: granularity hints NYI...
469          if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
470              panic("PTE GH field != 0");
471
472          // write entire quad
473          ipr[idx] = val;
474
475          // construct PTE for new entry
476          pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
477          pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
478          pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
479          pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
480          pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
481          pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
482          pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
483
484          // insert new TAG/PTE value into data TLB
485          xc->getDTBPtr()->insert(val, pte);
486      }
487        break;
488
489      case AlphaISA::IPR_ITB_PTE: {
490          struct AlphaISA::PTE pte;
491
492          // FIXME: granularity hints NYI...
493          if (ITB_PTE_GH(val) != 0)
494              panic("PTE GH field != 0");
495
496          // write entire quad
497          ipr[idx] = val;
498
499          // construct PTE for new entry
500          pte.ppn = ITB_PTE_PPN(val);
501          pte.xre = ITB_PTE_XRE(val);
502          pte.xwe = 0;
503          pte.fonr = ITB_PTE_FONR(val);
504          pte.fonw = ITB_PTE_FONW(val);
505          pte.asma = ITB_PTE_ASMA(val);
506          pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
507
508          // insert new TAG/PTE value into data TLB
509          xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
510      }
511        break;
512
513      case AlphaISA::IPR_ITB_IA:
514        // really a control write
515        ipr[idx] = 0;
516
517        xc->getITBPtr()->flushAll();
518        break;
519
520      case AlphaISA::IPR_ITB_IAP:
521        // really a control write
522        ipr[idx] = 0;
523
524        xc->getITBPtr()->flushProcesses();
525        break;
526
527      case AlphaISA::IPR_ITB_IS:
528        // really a control write
529        ipr[idx] = val;
530
531        xc->getITBPtr()->flushAddr(val,
532                                   ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
533        break;
534
535      default:
536        // invalid IPR
537        return new UnimplementedOpcodeFault;
538    }
539
540    // no error...
541    return NoFault;
542}
543
544void
545AlphaISA::MiscRegFile::copyIprs(ExecContext *xc)
546{
547    for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
548        ipr[i] = xc->readMiscReg(i);
549    }
550}
551
552/**
553 * Check for special simulator handling of specific PAL calls.
554 * If return value is false, actual PAL call will be suppressed.
555 */
556bool
557CPUExecContext::simPalCheck(int palFunc)
558{
559    cpu->kernelStats->callpal(palFunc, proxy);
560
561    switch (palFunc) {
562      case PAL::halt:
563        halt();
564        if (--System::numSystemsRunning == 0)
565            new SimExitEvent("all cpus halted");
566        break;
567
568      case PAL::bpt:
569      case PAL::bugchk:
570        if (system->breakpoint())
571            return false;
572        break;
573    }
574
575    return true;
576}
577
578//Forward instantiation for FastCPU object
579template
580void AlphaISA::processInterrupts(FastCPU *xc);
581
582//Forward instantiation for FastCPU object
583template
584void AlphaISA::zeroRegisters(FastCPU *xc);
585
586#endif // FULL_SYSTEM
587