ev5.cc revision 2245 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/alpha/tlb.hh"
30#include "arch/alpha/isa_traits.hh"
31#include "arch/alpha/osfpal.hh"
32#include "base/kgdb.h"
33#include "base/remote_gdb.hh"
34#include "base/stats/events.hh"
35#include "config/full_system.hh"
36#include "cpu/base.hh"
37#include "cpu/exec_context.hh"
38#include "cpu/fast/cpu.hh"
39#include "kern/kernel_stats.hh"
40#include "sim/debug.hh"
41#include "sim/sim_events.hh"
42
43#if FULL_SYSTEM
44
45using namespace EV5;
46
47////////////////////////////////////////////////////////////////////////
48//
49//  Machine dependent functions
50//
51void
52AlphaISA::initCPU(RegFile *regs, int cpuId)
53{
54    initIPRs(&regs->miscRegs, cpuId);
55
56    regs->intRegFile[16] = cpuId;
57    regs->intRegFile[0] = cpuId;
58
59    regs->pc = regs->miscRegs.readReg(IPR_PAL_BASE) + (new ResetFault)->vect();
60    regs->npc = regs->pc + sizeof(MachInst);
61}
62
63////////////////////////////////////////////////////////////////////////
64//
65//
66//
67void
68AlphaISA::initIPRs(MiscRegFile *miscRegs, int cpuId)
69{
70    miscRegs->clearIprs();
71
72    miscRegs->setReg(IPR_PAL_BASE, PalBase);
73    miscRegs->setReg(IPR_MCSR, 0x6);
74    miscRegs->setReg(IPR_PALtemp16, cpuId);
75}
76
77
78template <class CPU>
79void
80AlphaISA::processInterrupts(CPU *cpu)
81{
82    //Check if there are any outstanding interrupts
83    //Handle the interrupts
84    int ipl = 0;
85    int summary = 0;
86
87    cpu->checkInterrupts = false;
88
89    if (cpu->readMiscReg(IPR_ASTRR))
90        panic("asynchronous traps not implemented\n");
91
92    if (cpu->readMiscReg(IPR_SIRR)) {
93        for (int i = INTLEVEL_SOFTWARE_MIN;
94             i < INTLEVEL_SOFTWARE_MAX; i++) {
95            if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
96                // See table 4-19 of the 21164 hardware reference
97                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
98                summary |= (ULL(1) << i);
99            }
100        }
101    }
102
103    uint64_t interrupts = cpu->intr_status();
104
105    if (interrupts) {
106        for (int i = INTLEVEL_EXTERNAL_MIN;
107             i < INTLEVEL_EXTERNAL_MAX; i++) {
108            if (interrupts & (ULL(1) << i)) {
109                // See table 4-19 of the 21164 hardware reference
110                ipl = i;
111                summary |= (ULL(1) << i);
112            }
113        }
114    }
115
116    if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
117        cpu->setMiscReg(IPR_ISR, summary);
118        cpu->setMiscReg(IPR_INTID, ipl);
119        cpu->trap(new InterruptFault);
120        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
121                cpu->readMiscReg(IPR_IPLR), ipl, summary);
122    }
123
124}
125
126template <class CPU>
127void
128AlphaISA::zeroRegisters(CPU *cpu)
129{
130    // Insure ISA semantics
131    // (no longer very clean due to the change in setIntReg() in the
132    // cpu model.  Consider changing later.)
133    cpu->xc->setIntReg(ZeroReg, 0);
134    cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
135}
136
137Fault
138ExecContext::hwrei()
139{
140    if (!inPalMode())
141        return new UnimplementedOpcodeFault;
142
143    setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
144
145    if (!misspeculating()) {
146        kernelStats->hwrei();
147
148        cpu->checkInterrupts = true;
149    }
150
151    // FIXME: XXX check for interrupts? XXX
152    return NoFault;
153}
154
155int
156AlphaISA::MiscRegFile::getInstAsid()
157{
158    return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
159}
160
161int
162AlphaISA::MiscRegFile::getDataAsid()
163{
164    return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
165}
166
167void
168AlphaISA::MiscRegFile::clearIprs()
169{
170    bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
171}
172
173AlphaISA::MiscReg
174AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
175{
176    uint64_t retval = 0;	// return value, default 0
177
178    switch (idx) {
179      case AlphaISA::IPR_PALtemp0:
180      case AlphaISA::IPR_PALtemp1:
181      case AlphaISA::IPR_PALtemp2:
182      case AlphaISA::IPR_PALtemp3:
183      case AlphaISA::IPR_PALtemp4:
184      case AlphaISA::IPR_PALtemp5:
185      case AlphaISA::IPR_PALtemp6:
186      case AlphaISA::IPR_PALtemp7:
187      case AlphaISA::IPR_PALtemp8:
188      case AlphaISA::IPR_PALtemp9:
189      case AlphaISA::IPR_PALtemp10:
190      case AlphaISA::IPR_PALtemp11:
191      case AlphaISA::IPR_PALtemp12:
192      case AlphaISA::IPR_PALtemp13:
193      case AlphaISA::IPR_PALtemp14:
194      case AlphaISA::IPR_PALtemp15:
195      case AlphaISA::IPR_PALtemp16:
196      case AlphaISA::IPR_PALtemp17:
197      case AlphaISA::IPR_PALtemp18:
198      case AlphaISA::IPR_PALtemp19:
199      case AlphaISA::IPR_PALtemp20:
200      case AlphaISA::IPR_PALtemp21:
201      case AlphaISA::IPR_PALtemp22:
202      case AlphaISA::IPR_PALtemp23:
203      case AlphaISA::IPR_PAL_BASE:
204
205      case AlphaISA::IPR_IVPTBR:
206      case AlphaISA::IPR_DC_MODE:
207      case AlphaISA::IPR_MAF_MODE:
208      case AlphaISA::IPR_ISR:
209      case AlphaISA::IPR_EXC_ADDR:
210      case AlphaISA::IPR_IC_PERR_STAT:
211      case AlphaISA::IPR_DC_PERR_STAT:
212      case AlphaISA::IPR_MCSR:
213      case AlphaISA::IPR_ASTRR:
214      case AlphaISA::IPR_ASTER:
215      case AlphaISA::IPR_SIRR:
216      case AlphaISA::IPR_ICSR:
217      case AlphaISA::IPR_ICM:
218      case AlphaISA::IPR_DTB_CM:
219      case AlphaISA::IPR_IPLR:
220      case AlphaISA::IPR_INTID:
221      case AlphaISA::IPR_PMCTR:
222        // no side-effect
223        retval = ipr[idx];
224        break;
225
226      case AlphaISA::IPR_CC:
227        retval |= ipr[idx] & ULL(0xffffffff00000000);
228        retval |= xc->cpu->curCycle()  & ULL(0x00000000ffffffff);
229        break;
230
231      case AlphaISA::IPR_VA:
232        retval = ipr[idx];
233        break;
234
235      case AlphaISA::IPR_VA_FORM:
236      case AlphaISA::IPR_MM_STAT:
237      case AlphaISA::IPR_IFAULT_VA_FORM:
238      case AlphaISA::IPR_EXC_MASK:
239      case AlphaISA::IPR_EXC_SUM:
240        retval = ipr[idx];
241        break;
242
243      case AlphaISA::IPR_DTB_PTE:
244        {
245            AlphaISA::PTE &pte = xc->dtb->index(!xc->misspeculating());
246
247            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
248            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
249            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
250            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
251            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
252            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
253            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
254        }
255        break;
256
257        // write only registers
258      case AlphaISA::IPR_HWINT_CLR:
259      case AlphaISA::IPR_SL_XMIT:
260      case AlphaISA::IPR_DC_FLUSH:
261      case AlphaISA::IPR_IC_FLUSH:
262      case AlphaISA::IPR_ALT_MODE:
263      case AlphaISA::IPR_DTB_IA:
264      case AlphaISA::IPR_DTB_IAP:
265      case AlphaISA::IPR_ITB_IA:
266      case AlphaISA::IPR_ITB_IAP:
267        fault = new UnimplementedOpcodeFault;
268        break;
269
270      default:
271        // invalid IPR
272        fault = new UnimplementedOpcodeFault;
273        break;
274    }
275
276    return retval;
277}
278
279#ifdef DEBUG
280// Cause the simulator to break when changing to the following IPL
281int break_ipl = -1;
282#endif
283
284Fault
285AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
286{
287    uint64_t old;
288
289    if (xc->misspeculating())
290        return NoFault;
291
292    switch (idx) {
293      case AlphaISA::IPR_PALtemp0:
294      case AlphaISA::IPR_PALtemp1:
295      case AlphaISA::IPR_PALtemp2:
296      case AlphaISA::IPR_PALtemp3:
297      case AlphaISA::IPR_PALtemp4:
298      case AlphaISA::IPR_PALtemp5:
299      case AlphaISA::IPR_PALtemp6:
300      case AlphaISA::IPR_PALtemp7:
301      case AlphaISA::IPR_PALtemp8:
302      case AlphaISA::IPR_PALtemp9:
303      case AlphaISA::IPR_PALtemp10:
304      case AlphaISA::IPR_PALtemp11:
305      case AlphaISA::IPR_PALtemp12:
306      case AlphaISA::IPR_PALtemp13:
307      case AlphaISA::IPR_PALtemp14:
308      case AlphaISA::IPR_PALtemp15:
309      case AlphaISA::IPR_PALtemp16:
310      case AlphaISA::IPR_PALtemp17:
311      case AlphaISA::IPR_PALtemp18:
312      case AlphaISA::IPR_PALtemp19:
313      case AlphaISA::IPR_PALtemp20:
314      case AlphaISA::IPR_PALtemp21:
315      case AlphaISA::IPR_PALtemp22:
316      case AlphaISA::IPR_PAL_BASE:
317      case AlphaISA::IPR_IC_PERR_STAT:
318      case AlphaISA::IPR_DC_PERR_STAT:
319      case AlphaISA::IPR_PMCTR:
320        // write entire quad w/ no side-effect
321        ipr[idx] = val;
322        break;
323
324      case AlphaISA::IPR_CC_CTL:
325        // This IPR resets the cycle counter.  We assume this only
326        // happens once... let's verify that.
327        assert(ipr[idx] == 0);
328        ipr[idx] = 1;
329        break;
330
331      case AlphaISA::IPR_CC:
332        // This IPR only writes the upper 64 bits.  It's ok to write
333        // all 64 here since we mask out the lower 32 in rpcc (see
334        // isa_desc).
335        ipr[idx] = val;
336        break;
337
338      case AlphaISA::IPR_PALtemp23:
339        // write entire quad w/ no side-effect
340        old = ipr[idx];
341        ipr[idx] = val;
342        xc->kernelStats->context(old, val);
343        break;
344
345      case AlphaISA::IPR_DTB_PTE:
346        // write entire quad w/ no side-effect, tag is forthcoming
347        ipr[idx] = val;
348        break;
349
350      case AlphaISA::IPR_EXC_ADDR:
351        // second least significant bit in PC is always zero
352        ipr[idx] = val & ~2;
353        break;
354
355      case AlphaISA::IPR_ASTRR:
356      case AlphaISA::IPR_ASTER:
357        // only write least significant four bits - privilege mask
358        ipr[idx] = val & 0xf;
359        break;
360
361      case AlphaISA::IPR_IPLR:
362#ifdef DEBUG
363        if (break_ipl != -1 && break_ipl == (val & 0x1f))
364            debug_break();
365#endif
366
367        // only write least significant five bits - interrupt level
368        ipr[idx] = val & 0x1f;
369        xc->kernelStats->swpipl(ipr[idx]);
370        break;
371
372      case AlphaISA::IPR_DTB_CM:
373        if (val & 0x18)
374            xc->kernelStats->mode(Kernel::user);
375        else
376            xc->kernelStats->mode(Kernel::kernel);
377
378      case AlphaISA::IPR_ICM:
379        // only write two mode bits - processor mode
380        ipr[idx] = val & 0x18;
381        break;
382
383      case AlphaISA::IPR_ALT_MODE:
384        // only write two mode bits - processor mode
385        ipr[idx] = val & 0x18;
386        break;
387
388      case AlphaISA::IPR_MCSR:
389        // more here after optimization...
390        ipr[idx] = val;
391        break;
392
393      case AlphaISA::IPR_SIRR:
394        // only write software interrupt mask
395        ipr[idx] = val & 0x7fff0;
396        break;
397
398      case AlphaISA::IPR_ICSR:
399        ipr[idx] = val & ULL(0xffffff0300);
400        break;
401
402      case AlphaISA::IPR_IVPTBR:
403      case AlphaISA::IPR_MVPTBR:
404        ipr[idx] = val & ULL(0xffffffffc0000000);
405        break;
406
407      case AlphaISA::IPR_DC_TEST_CTL:
408        ipr[idx] = val & 0x1ffb;
409        break;
410
411      case AlphaISA::IPR_DC_MODE:
412      case AlphaISA::IPR_MAF_MODE:
413        ipr[idx] = val & 0x3f;
414        break;
415
416      case AlphaISA::IPR_ITB_ASN:
417        ipr[idx] = val & 0x7f0;
418        break;
419
420      case AlphaISA::IPR_DTB_ASN:
421        ipr[idx] = val & ULL(0xfe00000000000000);
422        break;
423
424      case AlphaISA::IPR_EXC_SUM:
425      case AlphaISA::IPR_EXC_MASK:
426        // any write to this register clears it
427        ipr[idx] = 0;
428        break;
429
430      case AlphaISA::IPR_INTID:
431      case AlphaISA::IPR_SL_RCV:
432      case AlphaISA::IPR_MM_STAT:
433      case AlphaISA::IPR_ITB_PTE_TEMP:
434      case AlphaISA::IPR_DTB_PTE_TEMP:
435        // read-only registers
436        return new UnimplementedOpcodeFault;
437
438      case AlphaISA::IPR_HWINT_CLR:
439      case AlphaISA::IPR_SL_XMIT:
440      case AlphaISA::IPR_DC_FLUSH:
441      case AlphaISA::IPR_IC_FLUSH:
442        // the following are write only
443        ipr[idx] = val;
444        break;
445
446      case AlphaISA::IPR_DTB_IA:
447        // really a control write
448        ipr[idx] = 0;
449
450        xc->dtb->flushAll();
451        break;
452
453      case AlphaISA::IPR_DTB_IAP:
454        // really a control write
455        ipr[idx] = 0;
456
457        xc->dtb->flushProcesses();
458        break;
459
460      case AlphaISA::IPR_DTB_IS:
461        // really a control write
462        ipr[idx] = val;
463
464        xc->dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
465        break;
466
467      case AlphaISA::IPR_DTB_TAG: {
468          struct AlphaISA::PTE pte;
469
470          // FIXME: granularity hints NYI...
471          if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
472              panic("PTE GH field != 0");
473
474          // write entire quad
475          ipr[idx] = val;
476
477          // construct PTE for new entry
478          pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
479          pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
480          pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
481          pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
482          pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
483          pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
484          pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
485
486          // insert new TAG/PTE value into data TLB
487          xc->dtb->insert(val, pte);
488      }
489        break;
490
491      case AlphaISA::IPR_ITB_PTE: {
492          struct AlphaISA::PTE pte;
493
494          // FIXME: granularity hints NYI...
495          if (ITB_PTE_GH(val) != 0)
496              panic("PTE GH field != 0");
497
498          // write entire quad
499          ipr[idx] = val;
500
501          // construct PTE for new entry
502          pte.ppn = ITB_PTE_PPN(val);
503          pte.xre = ITB_PTE_XRE(val);
504          pte.xwe = 0;
505          pte.fonr = ITB_PTE_FONR(val);
506          pte.fonw = ITB_PTE_FONW(val);
507          pte.asma = ITB_PTE_ASMA(val);
508          pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
509
510          // insert new TAG/PTE value into data TLB
511          xc->itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
512      }
513        break;
514
515      case AlphaISA::IPR_ITB_IA:
516        // really a control write
517        ipr[idx] = 0;
518
519        xc->itb->flushAll();
520        break;
521
522      case AlphaISA::IPR_ITB_IAP:
523        // really a control write
524        ipr[idx] = 0;
525
526        xc->itb->flushProcesses();
527        break;
528
529      case AlphaISA::IPR_ITB_IS:
530        // really a control write
531        ipr[idx] = val;
532
533        xc->itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
534        break;
535
536      default:
537        // invalid IPR
538        return new UnimplementedOpcodeFault;
539    }
540
541    // no error...
542    return NoFault;
543}
544
545/**
546 * Check for special simulator handling of specific PAL calls.
547 * If return value is false, actual PAL call will be suppressed.
548 */
549bool
550ExecContext::simPalCheck(int palFunc)
551{
552    kernelStats->callpal(palFunc);
553
554    switch (palFunc) {
555      case PAL::halt:
556        halt();
557        if (--System::numSystemsRunning == 0)
558            new SimExitEvent("all cpus halted");
559        break;
560
561      case PAL::bpt:
562      case PAL::bugchk:
563        if (system->breakpoint())
564            return false;
565        break;
566    }
567
568    return true;
569}
570
571//Forward instantiation for FastCPU object
572template
573void AlphaISA::processInterrupts(FastCPU *xc);
574
575//Forward instantiation for FastCPU object
576template
577void AlphaISA::zeroRegisters(FastCPU *xc);
578
579#endif // FULL_SYSTEM
580