ev5.cc revision 2154 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/alpha/alpha_memory.hh"
30#include "arch/alpha/isa_traits.hh"
31#include "arch/alpha/osfpal.hh"
32#include "base/kgdb.h"
33#include "base/remote_gdb.hh"
34#include "base/stats/events.hh"
35#include "config/full_system.hh"
36#include "cpu/base.hh"
37#include "cpu/exec_context.hh"
38#include "cpu/fast/cpu.hh"
39#include "kern/kernel_stats.hh"
40#include "sim/debug.hh"
41#include "sim/sim_events.hh"
42
43#if FULL_SYSTEM
44
45using namespace EV5;
46
47////////////////////////////////////////////////////////////////////////
48//
49//
50//
51void
52AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
53{
54    if (regs->pal_shadow == use_shadow)
55        panic("swap_palshadow: wrong PAL shadow state");
56
57    regs->pal_shadow = use_shadow;
58
59    for (int i = 0; i < NumIntRegs; i++) {
60        if (reg_redir[i]) {
61            IntReg temp = regs->intRegFile[i];
62            regs->intRegFile[i] = regs->palregs[i];
63            regs->palregs[i] = temp;
64        }
65    }
66}
67
68////////////////////////////////////////////////////////////////////////
69//
70//  Machine dependent functions
71//
72void
73AlphaISA::initCPU(RegFile *regs, int cpuId)
74{
75    initIPRs(regs, cpuId);
76    // CPU comes up with PAL regs enabled
77    swap_palshadow(regs, true);
78
79    regs->intRegFile[16] = cpuId;
80    regs->intRegFile[0] = cpuId;
81
82    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
83    regs->npc = regs->pc + sizeof(MachInst);
84}
85
86////////////////////////////////////////////////////////////////////////
87//
88// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
89//
90const Addr
91AlphaISA::fault_addr(Fault fault)
92{
93        //Check for the system wide faults
94        if(fault == NoFault) return 0x0000;
95        else if(fault == MachineCheckFault) return 0x0401;
96        else if(fault == AlignmentFault) return 0x0301;
97        //Deal with the alpha specific faults
98        return ((AlphaFault*)fault)->vect;
99};
100
101const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
102    /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
103    /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
104    /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
105    /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
106
107////////////////////////////////////////////////////////////////////////
108//
109//
110//
111void
112AlphaISA::initIPRs(RegFile *regs, int cpuId)
113{
114    uint64_t *ipr = regs->ipr;
115
116    bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
117    ipr[IPR_PAL_BASE] = PalBase;
118    ipr[IPR_MCSR] = 0x6;
119    ipr[IPR_PALtemp16] = cpuId;
120}
121
122
123template <class CPU>
124void
125AlphaISA::processInterrupts(CPU *cpu)
126{
127    //Check if there are any outstanding interrupts
128    //Handle the interrupts
129    int ipl = 0;
130    int summary = 0;
131    IntReg *ipr = cpu->getIprPtr();
132
133    cpu->checkInterrupts = false;
134
135    if (ipr[IPR_ASTRR])
136        panic("asynchronous traps not implemented\n");
137
138    if (ipr[IPR_SIRR]) {
139        for (int i = INTLEVEL_SOFTWARE_MIN;
140             i < INTLEVEL_SOFTWARE_MAX; i++) {
141            if (ipr[IPR_SIRR] & (ULL(1) << i)) {
142                // See table 4-19 of the 21164 hardware reference
143                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
144                summary |= (ULL(1) << i);
145            }
146        }
147    }
148
149    uint64_t interrupts = cpu->intr_status();
150
151    if (interrupts) {
152        for (int i = INTLEVEL_EXTERNAL_MIN;
153             i < INTLEVEL_EXTERNAL_MAX; i++) {
154            if (interrupts & (ULL(1) << i)) {
155                // See table 4-19 of the 21164 hardware reference
156                ipl = i;
157                summary |= (ULL(1) << i);
158            }
159        }
160    }
161
162    if (ipl && ipl > ipr[IPR_IPLR]) {
163        ipr[IPR_ISR] = summary;
164        ipr[IPR_INTID] = ipl;
165        cpu->trap(InterruptFault);
166        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
167                ipr[IPR_IPLR], ipl, summary);
168    }
169
170}
171
172template <class CPU>
173void
174AlphaISA::zeroRegisters(CPU *cpu)
175{
176    // Insure ISA semantics
177    // (no longer very clean due to the change in setIntReg() in the
178    // cpu model.  Consider changing later.)
179    cpu->xc->setIntReg(ZeroReg, 0);
180    cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
181}
182
183void
184ExecContext::ev5_trap(Fault fault)
185{
186    DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
187    cpu->recordEvent(csprintf("Fault %s", fault->name));
188
189    assert(!misspeculating());
190    kernelStats->fault(fault);
191
192    if (fault == ArithmeticFault)
193        panic("Arithmetic traps are unimplemented!");
194
195    AlphaISA::InternalProcReg *ipr = regs.ipr;
196
197    // exception restart address
198    if (fault != InterruptFault || !inPalMode())
199        ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
200
201    if (fault == PalFault || fault == ArithmeticFault /* ||
202        fault == InterruptFault && !inPalMode() */) {
203        // traps...  skip faulting instruction
204        ipr[AlphaISA::IPR_EXC_ADDR] += 4;
205    }
206
207    if (!inPalMode())
208        AlphaISA::swap_palshadow(&regs, true);
209
210    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
211    regs.npc = regs.pc + sizeof(MachInst);
212}
213
214
215void
216AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
217{
218    InternalProcReg *ipr = regs->ipr;
219    bool use_pc = (fault == NoFault);
220
221    if (fault == ArithmeticFault)
222        panic("arithmetic faults NYI...");
223
224    // compute exception restart address
225    if (use_pc || fault == PalFault || fault == ArithmeticFault) {
226        // traps...  skip faulting instruction
227        ipr[IPR_EXC_ADDR] = regs->pc + 4;
228    } else {
229        // fault, post fault at excepting instruction
230        ipr[IPR_EXC_ADDR] = regs->pc;
231    }
232
233    // jump to expection address (PAL PC bit set here as well...)
234    if (!use_pc)
235        regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
236    else
237        regs->npc = ipr[IPR_PAL_BASE] + pc;
238
239    // that's it! (orders of magnitude less painful than x86)
240}
241
242Fault
243ExecContext::hwrei()
244{
245    uint64_t *ipr = regs.ipr;
246
247    if (!inPalMode())
248        return UnimplementedOpcodeFault;
249
250    setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
251
252    if (!misspeculating()) {
253        kernelStats->hwrei();
254
255        if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
256            AlphaISA::swap_palshadow(&regs, false);
257
258        cpu->checkInterrupts = true;
259    }
260
261    // FIXME: XXX check for interrupts? XXX
262    return NoFault;
263}
264
265uint64_t
266ExecContext::readIpr(int idx, Fault &fault)
267{
268    uint64_t *ipr = regs.ipr;
269    uint64_t retval = 0;	// return value, default 0
270
271    switch (idx) {
272      case AlphaISA::IPR_PALtemp0:
273      case AlphaISA::IPR_PALtemp1:
274      case AlphaISA::IPR_PALtemp2:
275      case AlphaISA::IPR_PALtemp3:
276      case AlphaISA::IPR_PALtemp4:
277      case AlphaISA::IPR_PALtemp5:
278      case AlphaISA::IPR_PALtemp6:
279      case AlphaISA::IPR_PALtemp7:
280      case AlphaISA::IPR_PALtemp8:
281      case AlphaISA::IPR_PALtemp9:
282      case AlphaISA::IPR_PALtemp10:
283      case AlphaISA::IPR_PALtemp11:
284      case AlphaISA::IPR_PALtemp12:
285      case AlphaISA::IPR_PALtemp13:
286      case AlphaISA::IPR_PALtemp14:
287      case AlphaISA::IPR_PALtemp15:
288      case AlphaISA::IPR_PALtemp16:
289      case AlphaISA::IPR_PALtemp17:
290      case AlphaISA::IPR_PALtemp18:
291      case AlphaISA::IPR_PALtemp19:
292      case AlphaISA::IPR_PALtemp20:
293      case AlphaISA::IPR_PALtemp21:
294      case AlphaISA::IPR_PALtemp22:
295      case AlphaISA::IPR_PALtemp23:
296      case AlphaISA::IPR_PAL_BASE:
297
298      case AlphaISA::IPR_IVPTBR:
299      case AlphaISA::IPR_DC_MODE:
300      case AlphaISA::IPR_MAF_MODE:
301      case AlphaISA::IPR_ISR:
302      case AlphaISA::IPR_EXC_ADDR:
303      case AlphaISA::IPR_IC_PERR_STAT:
304      case AlphaISA::IPR_DC_PERR_STAT:
305      case AlphaISA::IPR_MCSR:
306      case AlphaISA::IPR_ASTRR:
307      case AlphaISA::IPR_ASTER:
308      case AlphaISA::IPR_SIRR:
309      case AlphaISA::IPR_ICSR:
310      case AlphaISA::IPR_ICM:
311      case AlphaISA::IPR_DTB_CM:
312      case AlphaISA::IPR_IPLR:
313      case AlphaISA::IPR_INTID:
314      case AlphaISA::IPR_PMCTR:
315        // no side-effect
316        retval = ipr[idx];
317        break;
318
319      case AlphaISA::IPR_CC:
320        retval |= ipr[idx] & ULL(0xffffffff00000000);
321        retval |= cpu->curCycle()  & ULL(0x00000000ffffffff);
322        break;
323
324      case AlphaISA::IPR_VA:
325        retval = ipr[idx];
326        break;
327
328      case AlphaISA::IPR_VA_FORM:
329      case AlphaISA::IPR_MM_STAT:
330      case AlphaISA::IPR_IFAULT_VA_FORM:
331      case AlphaISA::IPR_EXC_MASK:
332      case AlphaISA::IPR_EXC_SUM:
333        retval = ipr[idx];
334        break;
335
336      case AlphaISA::IPR_DTB_PTE:
337        {
338            AlphaISA::PTE &pte = dtb->index(!misspeculating());
339
340            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
341            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
342            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
343            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
344            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
345            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
346            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
347        }
348        break;
349
350        // write only registers
351      case AlphaISA::IPR_HWINT_CLR:
352      case AlphaISA::IPR_SL_XMIT:
353      case AlphaISA::IPR_DC_FLUSH:
354      case AlphaISA::IPR_IC_FLUSH:
355      case AlphaISA::IPR_ALT_MODE:
356      case AlphaISA::IPR_DTB_IA:
357      case AlphaISA::IPR_DTB_IAP:
358      case AlphaISA::IPR_ITB_IA:
359      case AlphaISA::IPR_ITB_IAP:
360        fault = UnimplementedOpcodeFault;
361        break;
362
363      default:
364        // invalid IPR
365        fault = UnimplementedOpcodeFault;
366        break;
367    }
368
369    return retval;
370}
371
372#ifdef DEBUG
373// Cause the simulator to break when changing to the following IPL
374int break_ipl = -1;
375#endif
376
377Fault
378ExecContext::setIpr(int idx, uint64_t val)
379{
380    uint64_t *ipr = regs.ipr;
381    uint64_t old;
382
383    if (misspeculating())
384        return NoFault;
385
386    switch (idx) {
387      case AlphaISA::IPR_PALtemp0:
388      case AlphaISA::IPR_PALtemp1:
389      case AlphaISA::IPR_PALtemp2:
390      case AlphaISA::IPR_PALtemp3:
391      case AlphaISA::IPR_PALtemp4:
392      case AlphaISA::IPR_PALtemp5:
393      case AlphaISA::IPR_PALtemp6:
394      case AlphaISA::IPR_PALtemp7:
395      case AlphaISA::IPR_PALtemp8:
396      case AlphaISA::IPR_PALtemp9:
397      case AlphaISA::IPR_PALtemp10:
398      case AlphaISA::IPR_PALtemp11:
399      case AlphaISA::IPR_PALtemp12:
400      case AlphaISA::IPR_PALtemp13:
401      case AlphaISA::IPR_PALtemp14:
402      case AlphaISA::IPR_PALtemp15:
403      case AlphaISA::IPR_PALtemp16:
404      case AlphaISA::IPR_PALtemp17:
405      case AlphaISA::IPR_PALtemp18:
406      case AlphaISA::IPR_PALtemp19:
407      case AlphaISA::IPR_PALtemp20:
408      case AlphaISA::IPR_PALtemp21:
409      case AlphaISA::IPR_PALtemp22:
410      case AlphaISA::IPR_PAL_BASE:
411      case AlphaISA::IPR_IC_PERR_STAT:
412      case AlphaISA::IPR_DC_PERR_STAT:
413      case AlphaISA::IPR_PMCTR:
414        // write entire quad w/ no side-effect
415        ipr[idx] = val;
416        break;
417
418      case AlphaISA::IPR_CC_CTL:
419        // This IPR resets the cycle counter.  We assume this only
420        // happens once... let's verify that.
421        assert(ipr[idx] == 0);
422        ipr[idx] = 1;
423        break;
424
425      case AlphaISA::IPR_CC:
426        // This IPR only writes the upper 64 bits.  It's ok to write
427        // all 64 here since we mask out the lower 32 in rpcc (see
428        // isa_desc).
429        ipr[idx] = val;
430        break;
431
432      case AlphaISA::IPR_PALtemp23:
433        // write entire quad w/ no side-effect
434        old = ipr[idx];
435        ipr[idx] = val;
436        kernelStats->context(old, val);
437        break;
438
439      case AlphaISA::IPR_DTB_PTE:
440        // write entire quad w/ no side-effect, tag is forthcoming
441        ipr[idx] = val;
442        break;
443
444      case AlphaISA::IPR_EXC_ADDR:
445        // second least significant bit in PC is always zero
446        ipr[idx] = val & ~2;
447        break;
448
449      case AlphaISA::IPR_ASTRR:
450      case AlphaISA::IPR_ASTER:
451        // only write least significant four bits - privilege mask
452        ipr[idx] = val & 0xf;
453        break;
454
455      case AlphaISA::IPR_IPLR:
456#ifdef DEBUG
457        if (break_ipl != -1 && break_ipl == (val & 0x1f))
458            debug_break();
459#endif
460
461        // only write least significant five bits - interrupt level
462        ipr[idx] = val & 0x1f;
463        kernelStats->swpipl(ipr[idx]);
464        break;
465
466      case AlphaISA::IPR_DTB_CM:
467        if (val & 0x18)
468            kernelStats->mode(Kernel::user);
469        else
470            kernelStats->mode(Kernel::kernel);
471
472      case AlphaISA::IPR_ICM:
473        // only write two mode bits - processor mode
474        ipr[idx] = val & 0x18;
475        break;
476
477      case AlphaISA::IPR_ALT_MODE:
478        // only write two mode bits - processor mode
479        ipr[idx] = val & 0x18;
480        break;
481
482      case AlphaISA::IPR_MCSR:
483        // more here after optimization...
484        ipr[idx] = val;
485        break;
486
487      case AlphaISA::IPR_SIRR:
488        // only write software interrupt mask
489        ipr[idx] = val & 0x7fff0;
490        break;
491
492      case AlphaISA::IPR_ICSR:
493        ipr[idx] = val & ULL(0xffffff0300);
494        break;
495
496      case AlphaISA::IPR_IVPTBR:
497      case AlphaISA::IPR_MVPTBR:
498        ipr[idx] = val & ULL(0xffffffffc0000000);
499        break;
500
501      case AlphaISA::IPR_DC_TEST_CTL:
502        ipr[idx] = val & 0x1ffb;
503        break;
504
505      case AlphaISA::IPR_DC_MODE:
506      case AlphaISA::IPR_MAF_MODE:
507        ipr[idx] = val & 0x3f;
508        break;
509
510      case AlphaISA::IPR_ITB_ASN:
511        ipr[idx] = val & 0x7f0;
512        break;
513
514      case AlphaISA::IPR_DTB_ASN:
515        ipr[idx] = val & ULL(0xfe00000000000000);
516        break;
517
518      case AlphaISA::IPR_EXC_SUM:
519      case AlphaISA::IPR_EXC_MASK:
520        // any write to this register clears it
521        ipr[idx] = 0;
522        break;
523
524      case AlphaISA::IPR_INTID:
525      case AlphaISA::IPR_SL_RCV:
526      case AlphaISA::IPR_MM_STAT:
527      case AlphaISA::IPR_ITB_PTE_TEMP:
528      case AlphaISA::IPR_DTB_PTE_TEMP:
529        // read-only registers
530        return UnimplementedOpcodeFault;
531
532      case AlphaISA::IPR_HWINT_CLR:
533      case AlphaISA::IPR_SL_XMIT:
534      case AlphaISA::IPR_DC_FLUSH:
535      case AlphaISA::IPR_IC_FLUSH:
536        // the following are write only
537        ipr[idx] = val;
538        break;
539
540      case AlphaISA::IPR_DTB_IA:
541        // really a control write
542        ipr[idx] = 0;
543
544        dtb->flushAll();
545        break;
546
547      case AlphaISA::IPR_DTB_IAP:
548        // really a control write
549        ipr[idx] = 0;
550
551        dtb->flushProcesses();
552        break;
553
554      case AlphaISA::IPR_DTB_IS:
555        // really a control write
556        ipr[idx] = val;
557
558        dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
559        break;
560
561      case AlphaISA::IPR_DTB_TAG: {
562          struct AlphaISA::PTE pte;
563
564          // FIXME: granularity hints NYI...
565          if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
566              panic("PTE GH field != 0");
567
568          // write entire quad
569          ipr[idx] = val;
570
571          // construct PTE for new entry
572          pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
573          pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
574          pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
575          pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
576          pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
577          pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
578          pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
579
580          // insert new TAG/PTE value into data TLB
581          dtb->insert(val, pte);
582      }
583        break;
584
585      case AlphaISA::IPR_ITB_PTE: {
586          struct AlphaISA::PTE pte;
587
588          // FIXME: granularity hints NYI...
589          if (ITB_PTE_GH(val) != 0)
590              panic("PTE GH field != 0");
591
592          // write entire quad
593          ipr[idx] = val;
594
595          // construct PTE for new entry
596          pte.ppn = ITB_PTE_PPN(val);
597          pte.xre = ITB_PTE_XRE(val);
598          pte.xwe = 0;
599          pte.fonr = ITB_PTE_FONR(val);
600          pte.fonw = ITB_PTE_FONW(val);
601          pte.asma = ITB_PTE_ASMA(val);
602          pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
603
604          // insert new TAG/PTE value into data TLB
605          itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
606      }
607        break;
608
609      case AlphaISA::IPR_ITB_IA:
610        // really a control write
611        ipr[idx] = 0;
612
613        itb->flushAll();
614        break;
615
616      case AlphaISA::IPR_ITB_IAP:
617        // really a control write
618        ipr[idx] = 0;
619
620        itb->flushProcesses();
621        break;
622
623      case AlphaISA::IPR_ITB_IS:
624        // really a control write
625        ipr[idx] = val;
626
627        itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
628        break;
629
630      default:
631        // invalid IPR
632        return UnimplementedOpcodeFault;
633    }
634
635    // no error...
636    return NoFault;
637}
638
639/**
640 * Check for special simulator handling of specific PAL calls.
641 * If return value is false, actual PAL call will be suppressed.
642 */
643bool
644ExecContext::simPalCheck(int palFunc)
645{
646    kernelStats->callpal(palFunc);
647
648    switch (palFunc) {
649      case PAL::halt:
650        halt();
651        if (--System::numSystemsRunning == 0)
652            new SimExitEvent("all cpus halted");
653        break;
654
655      case PAL::bpt:
656      case PAL::bugchk:
657        if (system->breakpoint())
658            return false;
659        break;
660    }
661
662    return true;
663}
664
665//Forward instantiation for FastCPU object
666template
667void AlphaISA::processInterrupts(FastCPU *xc);
668
669//Forward instantiation for FastCPU object
670template
671void AlphaISA::zeroRegisters(FastCPU *xc);
672
673#endif // FULL_SYSTEM
674