ev5.cc revision 2114 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/alpha/alpha_memory.hh"
30#include "arch/alpha/isa_traits.hh"
31#include "arch/alpha/osfpal.hh"
32#include "base/kgdb.h"
33#include "base/remote_gdb.hh"
34#include "base/stats/events.hh"
35#include "config/full_system.hh"
36#include "cpu/base.hh"
37#include "cpu/exec_context.hh"
38#include "cpu/fast/cpu.hh"
39#include "kern/kernel_stats.hh"
40#include "sim/debug.hh"
41#include "sim/sim_events.hh"
42
43#if FULL_SYSTEM
44
45using namespace EV5;
46
47////////////////////////////////////////////////////////////////////////
48//
49//
50//
51void
52AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
53{
54    if (regs->pal_shadow == use_shadow)
55        panic("swap_palshadow: wrong PAL shadow state");
56
57    regs->pal_shadow = use_shadow;
58
59    for (int i = 0; i < NumIntRegs; i++) {
60        if (reg_redir[i]) {
61            IntReg temp = regs->intRegFile[i];
62            regs->intRegFile[i] = regs->palregs[i];
63            regs->palregs[i] = temp;
64        }
65    }
66}
67
68////////////////////////////////////////////////////////////////////////
69//
70//  Machine dependent functions
71//
72void
73AlphaISA::initCPU(RegFile *regs, int cpuId)
74{
75    initIPRs(regs, cpuId);
76    // CPU comes up with PAL regs enabled
77    swap_palshadow(regs, true);
78
79    regs->intRegFile[16] = cpuId;
80    regs->intRegFile[0] = cpuId;
81
82    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
83    regs->npc = regs->pc + sizeof(MachInst);
84}
85
86////////////////////////////////////////////////////////////////////////
87//
88// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
89//
90Addr
91AlphaISA::fault_addr[Num_Faults] = {
92    0x0000,	/* No_Fault */
93    0x0001,	/* Reset_Fault */
94    0x0401,	/* Machine_Check_Fault */
95    0x0501,	/* Arithmetic_Fault */
96    0x0101,	/* Interrupt_Fault */
97    0x0201,	/* Ndtb_Miss_Fault */
98    0x0281,	/* Pdtb_Miss_Fault */
99    0x0301,	/* Alignment_Fault */
100    0x0381,	/* DTB_Fault_Fault */
101    0x0381,	/* DTB_Acv_Fault */
102    0x0181,	/* ITB_Miss_Fault */
103    0x0181,	/* ITB_Fault_Fault */
104    0x0081,	/* ITB_Acv_Fault */
105    0x0481,	/* Unimplemented_Opcode_Fault */
106    0x0581,	/* Fen_Fault */
107    0x2001,	/* Pal_Fault */
108    0x0501,	/* Integer_Overflow_Fault: maps to Arithmetic_Fault */
109};
110
111const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
112    /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
113    /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
114    /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
115    /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
116
117////////////////////////////////////////////////////////////////////////
118//
119//
120//
121void
122AlphaISA::initIPRs(RegFile *regs, int cpuId)
123{
124    uint64_t *ipr = regs->ipr;
125
126    bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
127    ipr[IPR_PAL_BASE] = PalBase;
128    ipr[IPR_MCSR] = 0x6;
129    ipr[IPR_PALtemp16] = cpuId;
130}
131
132
133template <class CPU>
134void
135AlphaISA::processInterrupts(CPU *cpu)
136{
137    //Check if there are any outstanding interrupts
138    //Handle the interrupts
139    int ipl = 0;
140    int summary = 0;
141    IntReg *ipr = cpu->getIprPtr();
142
143    cpu->checkInterrupts = false;
144
145    if (ipr[IPR_ASTRR])
146        panic("asynchronous traps not implemented\n");
147
148    if (ipr[IPR_SIRR]) {
149        for (int i = INTLEVEL_SOFTWARE_MIN;
150             i < INTLEVEL_SOFTWARE_MAX; i++) {
151            if (ipr[IPR_SIRR] & (ULL(1) << i)) {
152                // See table 4-19 of the 21164 hardware reference
153                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
154                summary |= (ULL(1) << i);
155            }
156        }
157    }
158
159    uint64_t interrupts = cpu->intr_status();
160
161    if (interrupts) {
162        for (int i = INTLEVEL_EXTERNAL_MIN;
163             i < INTLEVEL_EXTERNAL_MAX; i++) {
164            if (interrupts & (ULL(1) << i)) {
165                // See table 4-19 of the 21164 hardware reference
166                ipl = i;
167                summary |= (ULL(1) << i);
168            }
169        }
170    }
171
172    if (ipl && ipl > ipr[IPR_IPLR]) {
173        ipr[IPR_ISR] = summary;
174        ipr[IPR_INTID] = ipl;
175        cpu->trap(Interrupt_Fault);
176        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
177                ipr[IPR_IPLR], ipl, summary);
178    }
179
180}
181
182template <class CPU>
183void
184AlphaISA::zeroRegisters(CPU *cpu)
185{
186    // Insure ISA semantics
187    // (no longer very clean due to the change in setIntReg() in the
188    // cpu model.  Consider changing later.)
189    cpu->xc->setIntReg(ZeroReg, 0);
190    cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
191}
192
193void
194ExecContext::ev5_trap(Fault fault)
195{
196    DPRINTF(Fault, "Fault %s at PC: %#x\n", FaultName(fault), regs.pc);
197    cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
198
199    assert(!misspeculating());
200    kernelStats->fault(fault);
201
202    if (fault == Arithmetic_Fault)
203        panic("Arithmetic traps are unimplemented!");
204
205    AlphaISA::InternalProcReg *ipr = regs.ipr;
206
207    // exception restart address
208    if (fault != Interrupt_Fault || !inPalMode())
209        ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
210
211    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
212        fault == Interrupt_Fault && !inPalMode() */) {
213        // traps...  skip faulting instruction
214        ipr[AlphaISA::IPR_EXC_ADDR] += 4;
215    }
216
217    if (!inPalMode())
218        AlphaISA::swap_palshadow(&regs, true);
219
220    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
221    regs.npc = regs.pc + sizeof(MachInst);
222}
223
224
225void
226AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
227{
228    InternalProcReg *ipr = regs->ipr;
229    bool use_pc = (fault == No_Fault);
230
231    if (fault == Arithmetic_Fault)
232        panic("arithmetic faults NYI...");
233
234    // compute exception restart address
235    if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
236        // traps...  skip faulting instruction
237        ipr[IPR_EXC_ADDR] = regs->pc + 4;
238    } else {
239        // fault, post fault at excepting instruction
240        ipr[IPR_EXC_ADDR] = regs->pc;
241    }
242
243    // jump to expection address (PAL PC bit set here as well...)
244    if (!use_pc)
245        regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
246    else
247        regs->npc = ipr[IPR_PAL_BASE] + pc;
248
249    // that's it! (orders of magnitude less painful than x86)
250}
251
252Fault
253ExecContext::hwrei()
254{
255    uint64_t *ipr = regs.ipr;
256
257    if (!inPalMode())
258        return Unimplemented_Opcode_Fault;
259
260    setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
261
262    if (!misspeculating()) {
263        kernelStats->hwrei();
264
265        if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
266            AlphaISA::swap_palshadow(&regs, false);
267
268        cpu->checkInterrupts = true;
269    }
270
271    // FIXME: XXX check for interrupts? XXX
272    return No_Fault;
273}
274
275uint64_t
276ExecContext::readIpr(int idx, Fault &fault)
277{
278    uint64_t *ipr = regs.ipr;
279    uint64_t retval = 0;	// return value, default 0
280
281    switch (idx) {
282      case AlphaISA::IPR_PALtemp0:
283      case AlphaISA::IPR_PALtemp1:
284      case AlphaISA::IPR_PALtemp2:
285      case AlphaISA::IPR_PALtemp3:
286      case AlphaISA::IPR_PALtemp4:
287      case AlphaISA::IPR_PALtemp5:
288      case AlphaISA::IPR_PALtemp6:
289      case AlphaISA::IPR_PALtemp7:
290      case AlphaISA::IPR_PALtemp8:
291      case AlphaISA::IPR_PALtemp9:
292      case AlphaISA::IPR_PALtemp10:
293      case AlphaISA::IPR_PALtemp11:
294      case AlphaISA::IPR_PALtemp12:
295      case AlphaISA::IPR_PALtemp13:
296      case AlphaISA::IPR_PALtemp14:
297      case AlphaISA::IPR_PALtemp15:
298      case AlphaISA::IPR_PALtemp16:
299      case AlphaISA::IPR_PALtemp17:
300      case AlphaISA::IPR_PALtemp18:
301      case AlphaISA::IPR_PALtemp19:
302      case AlphaISA::IPR_PALtemp20:
303      case AlphaISA::IPR_PALtemp21:
304      case AlphaISA::IPR_PALtemp22:
305      case AlphaISA::IPR_PALtemp23:
306      case AlphaISA::IPR_PAL_BASE:
307
308      case AlphaISA::IPR_IVPTBR:
309      case AlphaISA::IPR_DC_MODE:
310      case AlphaISA::IPR_MAF_MODE:
311      case AlphaISA::IPR_ISR:
312      case AlphaISA::IPR_EXC_ADDR:
313      case AlphaISA::IPR_IC_PERR_STAT:
314      case AlphaISA::IPR_DC_PERR_STAT:
315      case AlphaISA::IPR_MCSR:
316      case AlphaISA::IPR_ASTRR:
317      case AlphaISA::IPR_ASTER:
318      case AlphaISA::IPR_SIRR:
319      case AlphaISA::IPR_ICSR:
320      case AlphaISA::IPR_ICM:
321      case AlphaISA::IPR_DTB_CM:
322      case AlphaISA::IPR_IPLR:
323      case AlphaISA::IPR_INTID:
324      case AlphaISA::IPR_PMCTR:
325        // no side-effect
326        retval = ipr[idx];
327        break;
328
329      case AlphaISA::IPR_CC:
330        retval |= ipr[idx] & ULL(0xffffffff00000000);
331        retval |= cpu->curCycle()  & ULL(0x00000000ffffffff);
332        break;
333
334      case AlphaISA::IPR_VA:
335        retval = ipr[idx];
336        break;
337
338      case AlphaISA::IPR_VA_FORM:
339      case AlphaISA::IPR_MM_STAT:
340      case AlphaISA::IPR_IFAULT_VA_FORM:
341      case AlphaISA::IPR_EXC_MASK:
342      case AlphaISA::IPR_EXC_SUM:
343        retval = ipr[idx];
344        break;
345
346      case AlphaISA::IPR_DTB_PTE:
347        {
348            AlphaISA::PTE &pte = dtb->index(!misspeculating());
349
350            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
351            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
352            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
353            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
354            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
355            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
356            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
357        }
358        break;
359
360        // write only registers
361      case AlphaISA::IPR_HWINT_CLR:
362      case AlphaISA::IPR_SL_XMIT:
363      case AlphaISA::IPR_DC_FLUSH:
364      case AlphaISA::IPR_IC_FLUSH:
365      case AlphaISA::IPR_ALT_MODE:
366      case AlphaISA::IPR_DTB_IA:
367      case AlphaISA::IPR_DTB_IAP:
368      case AlphaISA::IPR_ITB_IA:
369      case AlphaISA::IPR_ITB_IAP:
370        fault = Unimplemented_Opcode_Fault;
371        break;
372
373      default:
374        // invalid IPR
375        fault = Unimplemented_Opcode_Fault;
376        break;
377    }
378
379    return retval;
380}
381
382#ifdef DEBUG
383// Cause the simulator to break when changing to the following IPL
384int break_ipl = -1;
385#endif
386
387Fault
388ExecContext::setIpr(int idx, uint64_t val)
389{
390    uint64_t *ipr = regs.ipr;
391    uint64_t old;
392
393    if (misspeculating())
394        return No_Fault;
395
396    switch (idx) {
397      case AlphaISA::IPR_PALtemp0:
398      case AlphaISA::IPR_PALtemp1:
399      case AlphaISA::IPR_PALtemp2:
400      case AlphaISA::IPR_PALtemp3:
401      case AlphaISA::IPR_PALtemp4:
402      case AlphaISA::IPR_PALtemp5:
403      case AlphaISA::IPR_PALtemp6:
404      case AlphaISA::IPR_PALtemp7:
405      case AlphaISA::IPR_PALtemp8:
406      case AlphaISA::IPR_PALtemp9:
407      case AlphaISA::IPR_PALtemp10:
408      case AlphaISA::IPR_PALtemp11:
409      case AlphaISA::IPR_PALtemp12:
410      case AlphaISA::IPR_PALtemp13:
411      case AlphaISA::IPR_PALtemp14:
412      case AlphaISA::IPR_PALtemp15:
413      case AlphaISA::IPR_PALtemp16:
414      case AlphaISA::IPR_PALtemp17:
415      case AlphaISA::IPR_PALtemp18:
416      case AlphaISA::IPR_PALtemp19:
417      case AlphaISA::IPR_PALtemp20:
418      case AlphaISA::IPR_PALtemp21:
419      case AlphaISA::IPR_PALtemp22:
420      case AlphaISA::IPR_PAL_BASE:
421      case AlphaISA::IPR_IC_PERR_STAT:
422      case AlphaISA::IPR_DC_PERR_STAT:
423      case AlphaISA::IPR_PMCTR:
424        // write entire quad w/ no side-effect
425        ipr[idx] = val;
426        break;
427
428      case AlphaISA::IPR_CC_CTL:
429        // This IPR resets the cycle counter.  We assume this only
430        // happens once... let's verify that.
431        assert(ipr[idx] == 0);
432        ipr[idx] = 1;
433        break;
434
435      case AlphaISA::IPR_CC:
436        // This IPR only writes the upper 64 bits.  It's ok to write
437        // all 64 here since we mask out the lower 32 in rpcc (see
438        // isa_desc).
439        ipr[idx] = val;
440        break;
441
442      case AlphaISA::IPR_PALtemp23:
443        // write entire quad w/ no side-effect
444        old = ipr[idx];
445        ipr[idx] = val;
446        kernelStats->context(old, val);
447        break;
448
449      case AlphaISA::IPR_DTB_PTE:
450        // write entire quad w/ no side-effect, tag is forthcoming
451        ipr[idx] = val;
452        break;
453
454      case AlphaISA::IPR_EXC_ADDR:
455        // second least significant bit in PC is always zero
456        ipr[idx] = val & ~2;
457        break;
458
459      case AlphaISA::IPR_ASTRR:
460      case AlphaISA::IPR_ASTER:
461        // only write least significant four bits - privilege mask
462        ipr[idx] = val & 0xf;
463        break;
464
465      case AlphaISA::IPR_IPLR:
466#ifdef DEBUG
467        if (break_ipl != -1 && break_ipl == (val & 0x1f))
468            debug_break();
469#endif
470
471        // only write least significant five bits - interrupt level
472        ipr[idx] = val & 0x1f;
473        kernelStats->swpipl(ipr[idx]);
474        break;
475
476      case AlphaISA::IPR_DTB_CM:
477        if (val & 0x18)
478            kernelStats->mode(Kernel::user);
479        else
480            kernelStats->mode(Kernel::kernel);
481
482      case AlphaISA::IPR_ICM:
483        // only write two mode bits - processor mode
484        ipr[idx] = val & 0x18;
485        break;
486
487      case AlphaISA::IPR_ALT_MODE:
488        // only write two mode bits - processor mode
489        ipr[idx] = val & 0x18;
490        break;
491
492      case AlphaISA::IPR_MCSR:
493        // more here after optimization...
494        ipr[idx] = val;
495        break;
496
497      case AlphaISA::IPR_SIRR:
498        // only write software interrupt mask
499        ipr[idx] = val & 0x7fff0;
500        break;
501
502      case AlphaISA::IPR_ICSR:
503        ipr[idx] = val & ULL(0xffffff0300);
504        break;
505
506      case AlphaISA::IPR_IVPTBR:
507      case AlphaISA::IPR_MVPTBR:
508        ipr[idx] = val & ULL(0xffffffffc0000000);
509        break;
510
511      case AlphaISA::IPR_DC_TEST_CTL:
512        ipr[idx] = val & 0x1ffb;
513        break;
514
515      case AlphaISA::IPR_DC_MODE:
516      case AlphaISA::IPR_MAF_MODE:
517        ipr[idx] = val & 0x3f;
518        break;
519
520      case AlphaISA::IPR_ITB_ASN:
521        ipr[idx] = val & 0x7f0;
522        break;
523
524      case AlphaISA::IPR_DTB_ASN:
525        ipr[idx] = val & ULL(0xfe00000000000000);
526        break;
527
528      case AlphaISA::IPR_EXC_SUM:
529      case AlphaISA::IPR_EXC_MASK:
530        // any write to this register clears it
531        ipr[idx] = 0;
532        break;
533
534      case AlphaISA::IPR_INTID:
535      case AlphaISA::IPR_SL_RCV:
536      case AlphaISA::IPR_MM_STAT:
537      case AlphaISA::IPR_ITB_PTE_TEMP:
538      case AlphaISA::IPR_DTB_PTE_TEMP:
539        // read-only registers
540        return Unimplemented_Opcode_Fault;
541
542      case AlphaISA::IPR_HWINT_CLR:
543      case AlphaISA::IPR_SL_XMIT:
544      case AlphaISA::IPR_DC_FLUSH:
545      case AlphaISA::IPR_IC_FLUSH:
546        // the following are write only
547        ipr[idx] = val;
548        break;
549
550      case AlphaISA::IPR_DTB_IA:
551        // really a control write
552        ipr[idx] = 0;
553
554        dtb->flushAll();
555        break;
556
557      case AlphaISA::IPR_DTB_IAP:
558        // really a control write
559        ipr[idx] = 0;
560
561        dtb->flushProcesses();
562        break;
563
564      case AlphaISA::IPR_DTB_IS:
565        // really a control write
566        ipr[idx] = val;
567
568        dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
569        break;
570
571      case AlphaISA::IPR_DTB_TAG: {
572          struct AlphaISA::PTE pte;
573
574          // FIXME: granularity hints NYI...
575          if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
576              panic("PTE GH field != 0");
577
578          // write entire quad
579          ipr[idx] = val;
580
581          // construct PTE for new entry
582          pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
583          pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
584          pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
585          pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
586          pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
587          pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
588          pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
589
590          // insert new TAG/PTE value into data TLB
591          dtb->insert(val, pte);
592      }
593        break;
594
595      case AlphaISA::IPR_ITB_PTE: {
596          struct AlphaISA::PTE pte;
597
598          // FIXME: granularity hints NYI...
599          if (ITB_PTE_GH(val) != 0)
600              panic("PTE GH field != 0");
601
602          // write entire quad
603          ipr[idx] = val;
604
605          // construct PTE for new entry
606          pte.ppn = ITB_PTE_PPN(val);
607          pte.xre = ITB_PTE_XRE(val);
608          pte.xwe = 0;
609          pte.fonr = ITB_PTE_FONR(val);
610          pte.fonw = ITB_PTE_FONW(val);
611          pte.asma = ITB_PTE_ASMA(val);
612          pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
613
614          // insert new TAG/PTE value into data TLB
615          itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
616      }
617        break;
618
619      case AlphaISA::IPR_ITB_IA:
620        // really a control write
621        ipr[idx] = 0;
622
623        itb->flushAll();
624        break;
625
626      case AlphaISA::IPR_ITB_IAP:
627        // really a control write
628        ipr[idx] = 0;
629
630        itb->flushProcesses();
631        break;
632
633      case AlphaISA::IPR_ITB_IS:
634        // really a control write
635        ipr[idx] = val;
636
637        itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
638        break;
639
640      default:
641        // invalid IPR
642        return Unimplemented_Opcode_Fault;
643    }
644
645    // no error...
646    return No_Fault;
647}
648
649/**
650 * Check for special simulator handling of specific PAL calls.
651 * If return value is false, actual PAL call will be suppressed.
652 */
653bool
654ExecContext::simPalCheck(int palFunc)
655{
656    kernelStats->callpal(palFunc);
657
658    switch (palFunc) {
659      case PAL::halt:
660        halt();
661        if (--System::numSystemsRunning == 0)
662            new SimExitEvent("all cpus halted");
663        break;
664
665      case PAL::bpt:
666      case PAL::bugchk:
667        if (system->breakpoint())
668            return false;
669        break;
670    }
671
672    return true;
673}
674
675//Forward instantiation for FastCPU object
676template
677void AlphaISA::processInterrupts(FastCPU *xc);
678
679//Forward instantiation for FastCPU object
680template
681void AlphaISA::zeroRegisters(FastCPU *xc);
682
683#endif // FULL_SYSTEM
684