ev5.cc revision 2 
1/* $Id$ */
2
3#include "alpha_memory.hh"
4#include "annotation.hh"
5#ifdef DEBUG
6#include "debug.hh"
7#endif
8#include "exec_context.hh"
9#include "sim_events.hh"
10#include "isa_traits.hh"
11#include "remote_gdb.hh"
12#include "kgdb.h"	// for ALPHA_KENTRY_IF
13#include "osfpal.hh"
14
15#ifdef FULL_SYSTEM
16
17#ifndef SYSTEM_EV5
18#error This code is only valid for EV5 systems
19#endif
20
21////////////////////////////////////////////////////////////////////////
22//
23//
24//
25void
26AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
27{
28    if (regs->pal_shadow == use_shadow)
29        panic("swap_palshadow: wrong PAL shadow state");
30
31    regs->pal_shadow = use_shadow;
32
33    for (int i = 0; i < NumIntRegs; i++) {
34        if (reg_redir[i]) {
35            IntReg temp = regs->intRegFile[i];
36            regs->intRegFile[i] = regs->palregs[i];
37            regs->palregs[i] = temp;
38        }
39    }
40}
41
42////////////////////////////////////////////////////////////////////////
43//
44//  Machine dependent functions
45//
46void
47AlphaISA::init(void *mem, RegFile *regs)
48{
49    ipr_init(mem, regs);
50}
51
52void
53m5_exit()
54{
55    static SimExitEvent event("m5_exit instruction encountered");
56}
57
58////////////////////////////////////////////////////////////////////////
59//
60// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
61//
62Addr
63AlphaISA::fault_addr[Num_Faults] = {
64    0x0000,	/* No_Fault */
65    0x0001,	/* Reset_Fault */
66    0x0401,	/* Machine_Check_Fault */
67    0x0501,	/* Arithmetic_Fault */
68    0x0101,	/* Interrupt_Fault */
69    0x0201,	/* Ndtb_Miss_Fault */
70    0x0281,	/* Pdtb_Miss_Fault */
71    0x0301,	/* Alignment_Fault */
72    0x0381,	/* Dtb_Fault_Fault */
73    0x0381,	/* Dtb_Acv_Fault */
74    0x0181,	/* Itb_Miss_Fault */
75    0x0181,	/* Itb_Fault_Fault */
76    0x0081,	/* Itb_Acv_Fault */
77    0x0481,	/* Unimplemented_Opcode_Fault */
78    0x0581,	/* Fen_Fault */
79    0x2001,	/* Pal_Fault */
80    0x0501,	/* Integer_Overflow_Fault: maps to Arithmetic_Fault */
81};
82
83const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
84    /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
85    /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
86    /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
87    /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
88
89////////////////////////////////////////////////////////////////////////
90//
91//
92//
93void
94AlphaISA::ipr_init(void *mem, RegFile *regs)
95{
96    uint64_t *ipr = regs->ipr;
97
98    bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
99    ipr[IPR_PAL_BASE] = PAL_BASE;
100}
101
102
103void
104ExecContext::ev5_trap(Fault fault)
105{
106    assert(!misspeculating());
107    kernelStats.fault(fault);
108
109    if (fault == Arithmetic_Fault)
110        panic("Arithmetic traps are unimplemented!");
111
112    AlphaISA::InternalProcReg *ipr = regs.ipr;
113
114    // exception restart address
115    if (fault != Interrupt_Fault || !PC_PAL(regs.pc))
116        ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
117
118    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
119        fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
120        // traps...  skip faulting instruction
121        ipr[AlphaISA::IPR_EXC_ADDR] += 4;
122    }
123
124    if (!PC_PAL(regs.pc))
125        AlphaISA::swap_palshadow(&regs, true);
126
127    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
128    regs.npc = regs.pc + sizeof(MachInst);
129
130    Annotate::Ev5Trap(this, fault);
131}
132
133
134void
135AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
136{
137    InternalProcReg *ipr = regs->ipr;
138    bool use_pc = (fault == No_Fault);
139
140    if (fault == Arithmetic_Fault)
141        panic("arithmetic faults NYI...");
142
143    // compute exception restart address
144    if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
145        // traps...  skip faulting instruction
146        ipr[IPR_EXC_ADDR] = regs->pc + 4;
147    } else {
148        // fault, post fault at excepting instruction
149        ipr[IPR_EXC_ADDR] = regs->pc;
150    }
151
152    // jump to expection address (PAL PC bit set here as well...)
153    if (!use_pc)
154        regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
155    else
156        regs->npc = ipr[IPR_PAL_BASE] + pc;
157
158    // that's it! (orders of magnitude less painful than x86)
159}
160
161bool AlphaISA::check_interrupts = false;
162
163Fault
164ExecContext::hwrei()
165{
166    uint64_t *ipr = regs.ipr;
167
168    if (!PC_PAL(regs.pc))
169        return Unimplemented_Opcode_Fault;
170
171    kernelStats.hwrei();
172
173    regs.npc = ipr[AlphaISA::IPR_EXC_ADDR];
174
175    if (!misspeculating()) {
176        if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
177            AlphaISA::swap_palshadow(&regs, false);
178
179        AlphaISA::check_interrupts = true;
180    }
181
182    // FIXME: XXX check for interrupts? XXX
183    return No_Fault;
184}
185
186uint64_t
187ExecContext::readIpr(int idx, Fault &fault)
188{
189    uint64_t *ipr = regs.ipr;
190    uint64_t retval = 0;	// return value, default 0
191
192    switch (idx) {
193      case AlphaISA::IPR_PALtemp0:
194      case AlphaISA::IPR_PALtemp1:
195      case AlphaISA::IPR_PALtemp2:
196      case AlphaISA::IPR_PALtemp3:
197      case AlphaISA::IPR_PALtemp4:
198      case AlphaISA::IPR_PALtemp5:
199      case AlphaISA::IPR_PALtemp6:
200      case AlphaISA::IPR_PALtemp7:
201      case AlphaISA::IPR_PALtemp8:
202      case AlphaISA::IPR_PALtemp9:
203      case AlphaISA::IPR_PALtemp10:
204      case AlphaISA::IPR_PALtemp11:
205      case AlphaISA::IPR_PALtemp12:
206      case AlphaISA::IPR_PALtemp13:
207      case AlphaISA::IPR_PALtemp14:
208      case AlphaISA::IPR_PALtemp15:
209      case AlphaISA::IPR_PALtemp16:
210      case AlphaISA::IPR_PALtemp17:
211      case AlphaISA::IPR_PALtemp18:
212      case AlphaISA::IPR_PALtemp19:
213      case AlphaISA::IPR_PALtemp20:
214      case AlphaISA::IPR_PALtemp21:
215      case AlphaISA::IPR_PALtemp22:
216      case AlphaISA::IPR_PALtemp23:
217      case AlphaISA::IPR_PAL_BASE:
218
219      case AlphaISA::IPR_IVPTBR:
220      case AlphaISA::IPR_DC_MODE:
221      case AlphaISA::IPR_MAF_MODE:
222      case AlphaISA::IPR_ISR:
223      case AlphaISA::IPR_EXC_ADDR:
224      case AlphaISA::IPR_IC_PERR_STAT:
225      case AlphaISA::IPR_DC_PERR_STAT:
226      case AlphaISA::IPR_MCSR:
227      case AlphaISA::IPR_ASTRR:
228      case AlphaISA::IPR_ASTER:
229      case AlphaISA::IPR_SIRR:
230      case AlphaISA::IPR_ICSR:
231      case AlphaISA::IPR_ICM:
232      case AlphaISA::IPR_DTB_CM:
233      case AlphaISA::IPR_IPLR:
234      case AlphaISA::IPR_INTID:
235      case AlphaISA::IPR_PMCTR:
236        // no side-effect
237        retval = ipr[idx];
238        break;
239
240      case AlphaISA::IPR_VA:
241        // SFX: unlocks interrupt status registers
242        retval = ipr[idx];
243        regs.intrlock = false;
244        break;
245
246      case AlphaISA::IPR_VA_FORM:
247      case AlphaISA::IPR_MM_STAT:
248      case AlphaISA::IPR_IFAULT_VA_FORM:
249      case AlphaISA::IPR_EXC_MASK:
250      case AlphaISA::IPR_EXC_SUM:
251        retval = ipr[idx];
252        break;
253
254      case AlphaISA::IPR_DTB_PTE:
255        {
256            AlphaISA::PTE &pte = dtb->index();
257
258            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
259            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
260            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
261            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
262            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
263            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
264            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
265        }
266        break;
267
268        // write only registers
269      case AlphaISA::IPR_HWINT_CLR:
270      case AlphaISA::IPR_SL_XMIT:
271      case AlphaISA::IPR_DC_FLUSH:
272      case AlphaISA::IPR_IC_FLUSH:
273      case AlphaISA::IPR_ALT_MODE:
274      case AlphaISA::IPR_DTB_IA:
275      case AlphaISA::IPR_DTB_IAP:
276      case AlphaISA::IPR_ITB_IA:
277      case AlphaISA::IPR_ITB_IAP:
278        fault = Unimplemented_Opcode_Fault;
279        break;
280
281      default:
282        // invalid IPR
283        fault = Unimplemented_Opcode_Fault;
284        break;
285    }
286
287    return retval;
288}
289
290#ifdef DEBUG
291// Cause the simulator to break when changing to the following IPL
292int break_ipl = -1;
293#endif
294
295Fault
296ExecContext::setIpr(int idx, uint64_t val)
297{
298    uint64_t *ipr = regs.ipr;
299
300    if (misspeculating())
301        return No_Fault;
302
303    switch (idx) {
304      case AlphaISA::IPR_PALtemp0:
305      case AlphaISA::IPR_PALtemp1:
306      case AlphaISA::IPR_PALtemp2:
307      case AlphaISA::IPR_PALtemp3:
308      case AlphaISA::IPR_PALtemp4:
309      case AlphaISA::IPR_PALtemp5:
310      case AlphaISA::IPR_PALtemp6:
311      case AlphaISA::IPR_PALtemp7:
312      case AlphaISA::IPR_PALtemp8:
313      case AlphaISA::IPR_PALtemp9:
314      case AlphaISA::IPR_PALtemp10:
315      case AlphaISA::IPR_PALtemp11:
316      case AlphaISA::IPR_PALtemp12:
317      case AlphaISA::IPR_PALtemp13:
318      case AlphaISA::IPR_PALtemp14:
319      case AlphaISA::IPR_PALtemp15:
320      case AlphaISA::IPR_PALtemp16:
321      case AlphaISA::IPR_PALtemp17:
322      case AlphaISA::IPR_PALtemp18:
323      case AlphaISA::IPR_PALtemp19:
324      case AlphaISA::IPR_PALtemp20:
325      case AlphaISA::IPR_PALtemp21:
326      case AlphaISA::IPR_PALtemp22:
327      case AlphaISA::IPR_PAL_BASE:
328      case AlphaISA::IPR_IC_PERR_STAT:
329      case AlphaISA::IPR_DC_PERR_STAT:
330      case AlphaISA::IPR_CC_CTL:
331      case AlphaISA::IPR_CC:
332      case AlphaISA::IPR_PMCTR:
333        // write entire quad w/ no side-effect
334        ipr[idx] = val;
335        break;
336
337      case AlphaISA::IPR_PALtemp23:
338        // write entire quad w/ no side-effect
339        ipr[idx] = val;
340        kernelStats.context(ipr[idx]);
341        Annotate::Context(this);
342        break;
343
344      case AlphaISA::IPR_DTB_PTE:
345        // write entire quad w/ no side-effect, tag is forthcoming
346        ipr[idx] = val;
347        break;
348
349      case AlphaISA::IPR_EXC_ADDR:
350        // second least significant bit in PC is always zero
351        ipr[idx] = val & ~2;
352        break;
353
354      case AlphaISA::IPR_ASTRR:
355      case AlphaISA::IPR_ASTER:
356        // only write least significant four bits - privilege mask
357        ipr[idx] = val & 0xf;
358        break;
359
360      case AlphaISA::IPR_IPLR:
361#ifdef DEBUG
362        if (break_ipl != -1 && break_ipl == (val & 0x1f))
363            debug_break();
364#endif
365
366        // only write least significant five bits - interrupt level
367        ipr[idx] = val & 0x1f;
368        kernelStats.swpipl(ipr[idx]);
369        Annotate::IPL(this, val & 0x1f);
370        break;
371
372      case AlphaISA::IPR_DTB_CM:
373        Annotate::ChangeMode(this, (val & 0x18) != 0);
374        kernelStats.mode((val & 0x18) != 0);
375
376      case AlphaISA::IPR_ICM:
377        // only write two mode bits - processor mode
378        ipr[idx] = val & 0x18;
379        break;
380
381      case AlphaISA::IPR_ALT_MODE:
382        // only write two mode bits - processor mode
383        ipr[idx] = val & 0x18;
384        break;
385
386      case AlphaISA::IPR_MCSR:
387        // more here after optimization...
388        ipr[idx] = val;
389        break;
390
391      case AlphaISA::IPR_SIRR:
392        // only write software interrupt mask
393        ipr[idx] = val & 0x7fff0;
394        break;
395
396      case AlphaISA::IPR_ICSR:
397        ipr[idx] = val & ULL(0xffffff0300);
398        break;
399
400      case AlphaISA::IPR_IVPTBR:
401      case AlphaISA::IPR_MVPTBR:
402        ipr[idx] = val & ULL(0xffffffffc0000000);
403        break;
404
405      case AlphaISA::IPR_DC_TEST_CTL:
406        ipr[idx] = val & 0x1ffb;
407        break;
408
409      case AlphaISA::IPR_DC_MODE:
410      case AlphaISA::IPR_MAF_MODE:
411        ipr[idx] = val & 0x3f;
412        break;
413
414      case AlphaISA::IPR_ITB_ASN:
415        ipr[idx] = val & 0x7f0;
416        break;
417
418      case AlphaISA::IPR_DTB_ASN:
419        ipr[idx] = val & ULL(0xfe00000000000000);
420        break;
421
422      case AlphaISA::IPR_EXC_SUM:
423      case AlphaISA::IPR_EXC_MASK:
424        // any write to this register clears it
425        ipr[idx] = 0;
426        break;
427
428      case AlphaISA::IPR_INTID:
429      case AlphaISA::IPR_SL_RCV:
430      case AlphaISA::IPR_MM_STAT:
431      case AlphaISA::IPR_ITB_PTE_TEMP:
432      case AlphaISA::IPR_DTB_PTE_TEMP:
433        // read-only registers
434        return Unimplemented_Opcode_Fault;
435
436      case AlphaISA::IPR_HWINT_CLR:
437      case AlphaISA::IPR_SL_XMIT:
438      case AlphaISA::IPR_DC_FLUSH:
439      case AlphaISA::IPR_IC_FLUSH:
440        // the following are write only
441        ipr[idx] = val;
442        break;
443
444      case AlphaISA::IPR_DTB_IA:
445        // really a control write
446        ipr[idx] = 0;
447
448        dtb->flushAll();
449        break;
450
451      case AlphaISA::IPR_DTB_IAP:
452        // really a control write
453        ipr[idx] = 0;
454
455        dtb->flushProcesses();
456        break;
457
458      case AlphaISA::IPR_DTB_IS:
459        // really a control write
460        ipr[idx] = val;
461
462        dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
463        break;
464
465      case AlphaISA::IPR_DTB_TAG: {
466          struct AlphaISA::PTE pte;
467
468          // FIXME: granularity hints NYI...
469          if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
470              panic("PTE GH field != 0");
471
472          // write entire quad
473          ipr[idx] = val;
474
475          // construct PTE for new entry
476          pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
477          pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
478          pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
479          pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
480          pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
481          pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
482          pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
483
484          // insert new TAG/PTE value into data TLB
485          dtb->insert(val, pte);
486      }
487        break;
488
489      case AlphaISA::IPR_ITB_PTE: {
490          struct AlphaISA::PTE pte;
491
492          // FIXME: granularity hints NYI...
493          if (ITB_PTE_GH(val) != 0)
494              panic("PTE GH field != 0");
495
496          // write entire quad
497          ipr[idx] = val;
498
499          // construct PTE for new entry
500          pte.ppn = ITB_PTE_PPN(val);
501          pte.xre = ITB_PTE_XRE(val);
502          pte.xwe = 0;
503          pte.fonr = ITB_PTE_FONR(val);
504          pte.fonw = ITB_PTE_FONW(val);
505          pte.asma = ITB_PTE_ASMA(val);
506          pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
507
508          // insert new TAG/PTE value into data TLB
509          itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
510      }
511        break;
512
513      case AlphaISA::IPR_ITB_IA:
514        // really a control write
515        ipr[idx] = 0;
516
517        itb->flushAll();
518        break;
519
520      case AlphaISA::IPR_ITB_IAP:
521        // really a control write
522        ipr[idx] = 0;
523
524        itb->flushProcesses();
525        break;
526
527      case AlphaISA::IPR_ITB_IS:
528        // really a control write
529        ipr[idx] = val;
530
531        itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
532        break;
533
534      default:
535        // invalid IPR
536        return Unimplemented_Opcode_Fault;
537    }
538
539    // no error...
540    return No_Fault;
541}
542
543/**
544 * Check for special simulator handling of specific PAL calls.
545 * If return value is false, actual PAL call will be suppressed.
546 */
547bool
548ExecContext::simPalCheck(int palFunc)
549{
550    kernelStats.callpal(palFunc);
551
552    switch (palFunc) {
553      case PAL::halt:
554        if (!misspeculating()) {
555            setStatus(Halted);
556            if (--System::numSystemsRunning == 0)
557                new SimExitEvent("all cpus halted");
558        }
559        break;
560
561      case PAL::bpt:
562      case PAL::bugchk:
563        if (system->remoteGDB->trap(ALPHA_KENTRY_IF))
564            return false;
565        break;
566    }
567
568    return true;
569}
570
571#endif // FULL_SYSTEM
572