ev5.cc revision 1758 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/alpha/alpha_memory.hh"
30#include "arch/alpha/isa_traits.hh"
31#include "arch/alpha/osfpal.hh"
32#include "base/kgdb.h"
33#include "base/remote_gdb.hh"
34#include "base/stats/events.hh"
35#include "cpu/base.hh"
36#include "cpu/exec_context.hh"
37#include "cpu/fast/cpu.hh"
38#include "kern/kernel_stats.hh"
39#include "sim/debug.hh"
40#include "sim/sim_events.hh"
41
42#ifdef FULL_SYSTEM
43
44using namespace EV5;
45
46////////////////////////////////////////////////////////////////////////
47//
48//
49//
50void
51AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
52{
53    if (regs->pal_shadow == use_shadow)
54        panic("swap_palshadow: wrong PAL shadow state");
55
56    regs->pal_shadow = use_shadow;
57
58    for (int i = 0; i < NumIntRegs; i++) {
59        if (reg_redir[i]) {
60            IntReg temp = regs->intRegFile[i];
61            regs->intRegFile[i] = regs->palregs[i];
62            regs->palregs[i] = temp;
63        }
64    }
65}
66
67////////////////////////////////////////////////////////////////////////
68//
69//  Machine dependent functions
70//
71void
72AlphaISA::initCPU(RegFile *regs)
73{
74    initIPRs(regs);
75    // CPU comes up with PAL regs enabled
76    swap_palshadow(regs, true);
77
78    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
79    regs->npc = regs->pc + sizeof(MachInst);
80}
81
82////////////////////////////////////////////////////////////////////////
83//
84// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
85//
86Addr
87AlphaISA::fault_addr[Num_Faults] = {
88    0x0000,	/* No_Fault */
89    0x0001,	/* Reset_Fault */
90    0x0401,	/* Machine_Check_Fault */
91    0x0501,	/* Arithmetic_Fault */
92    0x0101,	/* Interrupt_Fault */
93    0x0201,	/* Ndtb_Miss_Fault */
94    0x0281,	/* Pdtb_Miss_Fault */
95    0x0301,	/* Alignment_Fault */
96    0x0381,	/* DTB_Fault_Fault */
97    0x0381,	/* DTB_Acv_Fault */
98    0x0181,	/* ITB_Miss_Fault */
99    0x0181,	/* ITB_Fault_Fault */
100    0x0081,	/* ITB_Acv_Fault */
101    0x0481,	/* Unimplemented_Opcode_Fault */
102    0x0581,	/* Fen_Fault */
103    0x2001,	/* Pal_Fault */
104    0x0501,	/* Integer_Overflow_Fault: maps to Arithmetic_Fault */
105};
106
107const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
108    /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
109    /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
110    /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
111    /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
112
113////////////////////////////////////////////////////////////////////////
114//
115//
116//
117void
118AlphaISA::initIPRs(RegFile *regs)
119{
120    uint64_t *ipr = regs->ipr;
121
122    bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
123    ipr[IPR_PAL_BASE] = PalBase;
124    ipr[IPR_MCSR] = 0x6;
125}
126
127
128template <class CPU>
129void
130AlphaISA::processInterrupts(CPU *cpu)
131{
132    //Check if there are any outstanding interrupts
133    //Handle the interrupts
134    int ipl = 0;
135    int summary = 0;
136    IntReg *ipr = cpu->getIprPtr();
137
138    cpu->checkInterrupts = false;
139
140    if (ipr[IPR_ASTRR])
141        panic("asynchronous traps not implemented\n");
142
143    if (ipr[IPR_SIRR]) {
144        for (int i = INTLEVEL_SOFTWARE_MIN;
145             i < INTLEVEL_SOFTWARE_MAX; i++) {
146            if (ipr[IPR_SIRR] & (ULL(1) << i)) {
147                // See table 4-19 of the 21164 hardware reference
148                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
149                summary |= (ULL(1) << i);
150            }
151        }
152    }
153
154    uint64_t interrupts = cpu->intr_status();
155
156    if (interrupts) {
157        for (int i = INTLEVEL_EXTERNAL_MIN;
158             i < INTLEVEL_EXTERNAL_MAX; i++) {
159            if (interrupts & (ULL(1) << i)) {
160                // See table 4-19 of the 21164 hardware reference
161                ipl = i;
162                summary |= (ULL(1) << i);
163            }
164        }
165    }
166
167    if (ipl && ipl > ipr[IPR_IPLR]) {
168        ipr[IPR_ISR] = summary;
169        ipr[IPR_INTID] = ipl;
170        cpu->trap(Interrupt_Fault);
171        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
172                ipr[IPR_IPLR], ipl, summary);
173    }
174
175}
176
177template <class CPU>
178void
179AlphaISA::zeroRegisters(CPU *cpu)
180{
181    // Insure ISA semantics
182    // (no longer very clean due to the change in setIntReg() in the
183    // cpu model.  Consider changing later.)
184    cpu->xc->setIntReg(ZeroReg, 0);
185    cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
186}
187
188void
189ExecContext::ev5_trap(Fault fault)
190{
191    DPRINTF(Fault, "Fault %s at PC: %#x\n", FaultName(fault), regs.pc);
192    cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
193
194    assert(!misspeculating());
195    kernelStats->fault(fault);
196
197    if (fault == Arithmetic_Fault)
198        panic("Arithmetic traps are unimplemented!");
199
200    AlphaISA::InternalProcReg *ipr = regs.ipr;
201
202    // exception restart address
203    if (fault != Interrupt_Fault || !inPalMode())
204        ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
205
206    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
207        fault == Interrupt_Fault && !inPalMode() */) {
208        // traps...  skip faulting instruction
209        ipr[AlphaISA::IPR_EXC_ADDR] += 4;
210    }
211
212    if (!inPalMode())
213        AlphaISA::swap_palshadow(&regs, true);
214
215    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
216    regs.npc = regs.pc + sizeof(MachInst);
217}
218
219
220void
221AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
222{
223    InternalProcReg *ipr = regs->ipr;
224    bool use_pc = (fault == No_Fault);
225
226    if (fault == Arithmetic_Fault)
227        panic("arithmetic faults NYI...");
228
229    // compute exception restart address
230    if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
231        // traps...  skip faulting instruction
232        ipr[IPR_EXC_ADDR] = regs->pc + 4;
233    } else {
234        // fault, post fault at excepting instruction
235        ipr[IPR_EXC_ADDR] = regs->pc;
236    }
237
238    // jump to expection address (PAL PC bit set here as well...)
239    if (!use_pc)
240        regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
241    else
242        regs->npc = ipr[IPR_PAL_BASE] + pc;
243
244    // that's it! (orders of magnitude less painful than x86)
245}
246
247Fault
248ExecContext::hwrei()
249{
250    uint64_t *ipr = regs.ipr;
251
252    if (!inPalMode())
253        return Unimplemented_Opcode_Fault;
254
255    setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
256
257    if (!misspeculating()) {
258        kernelStats->hwrei();
259
260        if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
261            AlphaISA::swap_palshadow(&regs, false);
262
263        cpu->checkInterrupts = true;
264    }
265
266    // FIXME: XXX check for interrupts? XXX
267    return No_Fault;
268}
269
270uint64_t
271ExecContext::readIpr(int idx, Fault &fault)
272{
273    uint64_t *ipr = regs.ipr;
274    uint64_t retval = 0;	// return value, default 0
275
276    switch (idx) {
277      case AlphaISA::IPR_PALtemp0:
278      case AlphaISA::IPR_PALtemp1:
279      case AlphaISA::IPR_PALtemp2:
280      case AlphaISA::IPR_PALtemp3:
281      case AlphaISA::IPR_PALtemp4:
282      case AlphaISA::IPR_PALtemp5:
283      case AlphaISA::IPR_PALtemp6:
284      case AlphaISA::IPR_PALtemp7:
285      case AlphaISA::IPR_PALtemp8:
286      case AlphaISA::IPR_PALtemp9:
287      case AlphaISA::IPR_PALtemp10:
288      case AlphaISA::IPR_PALtemp11:
289      case AlphaISA::IPR_PALtemp12:
290      case AlphaISA::IPR_PALtemp13:
291      case AlphaISA::IPR_PALtemp14:
292      case AlphaISA::IPR_PALtemp15:
293      case AlphaISA::IPR_PALtemp16:
294      case AlphaISA::IPR_PALtemp17:
295      case AlphaISA::IPR_PALtemp18:
296      case AlphaISA::IPR_PALtemp19:
297      case AlphaISA::IPR_PALtemp20:
298      case AlphaISA::IPR_PALtemp21:
299      case AlphaISA::IPR_PALtemp22:
300      case AlphaISA::IPR_PALtemp23:
301      case AlphaISA::IPR_PAL_BASE:
302
303      case AlphaISA::IPR_IVPTBR:
304      case AlphaISA::IPR_DC_MODE:
305      case AlphaISA::IPR_MAF_MODE:
306      case AlphaISA::IPR_ISR:
307      case AlphaISA::IPR_EXC_ADDR:
308      case AlphaISA::IPR_IC_PERR_STAT:
309      case AlphaISA::IPR_DC_PERR_STAT:
310      case AlphaISA::IPR_MCSR:
311      case AlphaISA::IPR_ASTRR:
312      case AlphaISA::IPR_ASTER:
313      case AlphaISA::IPR_SIRR:
314      case AlphaISA::IPR_ICSR:
315      case AlphaISA::IPR_ICM:
316      case AlphaISA::IPR_DTB_CM:
317      case AlphaISA::IPR_IPLR:
318      case AlphaISA::IPR_INTID:
319      case AlphaISA::IPR_PMCTR:
320        // no side-effect
321        retval = ipr[idx];
322        break;
323
324      case AlphaISA::IPR_CC:
325        retval |= ipr[idx] & ULL(0xffffffff00000000);
326        retval |= cpu->curCycle()  & ULL(0x00000000ffffffff);
327        break;
328
329      case AlphaISA::IPR_VA:
330        retval = ipr[idx];
331        break;
332
333      case AlphaISA::IPR_VA_FORM:
334      case AlphaISA::IPR_MM_STAT:
335      case AlphaISA::IPR_IFAULT_VA_FORM:
336      case AlphaISA::IPR_EXC_MASK:
337      case AlphaISA::IPR_EXC_SUM:
338        retval = ipr[idx];
339        break;
340
341      case AlphaISA::IPR_DTB_PTE:
342        {
343            AlphaISA::PTE &pte = dtb->index(!misspeculating());
344
345            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
346            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
347            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
348            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
349            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
350            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
351            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
352        }
353        break;
354
355        // write only registers
356      case AlphaISA::IPR_HWINT_CLR:
357      case AlphaISA::IPR_SL_XMIT:
358      case AlphaISA::IPR_DC_FLUSH:
359      case AlphaISA::IPR_IC_FLUSH:
360      case AlphaISA::IPR_ALT_MODE:
361      case AlphaISA::IPR_DTB_IA:
362      case AlphaISA::IPR_DTB_IAP:
363      case AlphaISA::IPR_ITB_IA:
364      case AlphaISA::IPR_ITB_IAP:
365        fault = Unimplemented_Opcode_Fault;
366        break;
367
368      default:
369        // invalid IPR
370        fault = Unimplemented_Opcode_Fault;
371        break;
372    }
373
374    return retval;
375}
376
377#ifdef DEBUG
378// Cause the simulator to break when changing to the following IPL
379int break_ipl = -1;
380#endif
381
382Fault
383ExecContext::setIpr(int idx, uint64_t val)
384{
385    uint64_t *ipr = regs.ipr;
386    uint64_t old;
387
388    if (misspeculating())
389        return No_Fault;
390
391    switch (idx) {
392      case AlphaISA::IPR_PALtemp0:
393      case AlphaISA::IPR_PALtemp1:
394      case AlphaISA::IPR_PALtemp2:
395      case AlphaISA::IPR_PALtemp3:
396      case AlphaISA::IPR_PALtemp4:
397      case AlphaISA::IPR_PALtemp5:
398      case AlphaISA::IPR_PALtemp6:
399      case AlphaISA::IPR_PALtemp7:
400      case AlphaISA::IPR_PALtemp8:
401      case AlphaISA::IPR_PALtemp9:
402      case AlphaISA::IPR_PALtemp10:
403      case AlphaISA::IPR_PALtemp11:
404      case AlphaISA::IPR_PALtemp12:
405      case AlphaISA::IPR_PALtemp13:
406      case AlphaISA::IPR_PALtemp14:
407      case AlphaISA::IPR_PALtemp15:
408      case AlphaISA::IPR_PALtemp16:
409      case AlphaISA::IPR_PALtemp17:
410      case AlphaISA::IPR_PALtemp18:
411      case AlphaISA::IPR_PALtemp19:
412      case AlphaISA::IPR_PALtemp20:
413      case AlphaISA::IPR_PALtemp21:
414      case AlphaISA::IPR_PALtemp22:
415      case AlphaISA::IPR_PAL_BASE:
416      case AlphaISA::IPR_IC_PERR_STAT:
417      case AlphaISA::IPR_DC_PERR_STAT:
418      case AlphaISA::IPR_PMCTR:
419        // write entire quad w/ no side-effect
420        ipr[idx] = val;
421        break;
422
423      case AlphaISA::IPR_CC_CTL:
424        // This IPR resets the cycle counter.  We assume this only
425        // happens once... let's verify that.
426        assert(ipr[idx] == 0);
427        ipr[idx] = 1;
428        break;
429
430      case AlphaISA::IPR_CC:
431        // This IPR only writes the upper 64 bits.  It's ok to write
432        // all 64 here since we mask out the lower 32 in rpcc (see
433        // isa_desc).
434        ipr[idx] = val;
435        break;
436
437      case AlphaISA::IPR_PALtemp23:
438        // write entire quad w/ no side-effect
439        old = ipr[idx];
440        ipr[idx] = val;
441        kernelStats->context(old, val);
442        break;
443
444      case AlphaISA::IPR_DTB_PTE:
445        // write entire quad w/ no side-effect, tag is forthcoming
446        ipr[idx] = val;
447        break;
448
449      case AlphaISA::IPR_EXC_ADDR:
450        // second least significant bit in PC is always zero
451        ipr[idx] = val & ~2;
452        break;
453
454      case AlphaISA::IPR_ASTRR:
455      case AlphaISA::IPR_ASTER:
456        // only write least significant four bits - privilege mask
457        ipr[idx] = val & 0xf;
458        break;
459
460      case AlphaISA::IPR_IPLR:
461#ifdef DEBUG
462        if (break_ipl != -1 && break_ipl == (val & 0x1f))
463            debug_break();
464#endif
465
466        // only write least significant five bits - interrupt level
467        ipr[idx] = val & 0x1f;
468        kernelStats->swpipl(ipr[idx]);
469        break;
470
471      case AlphaISA::IPR_DTB_CM:
472        if (val & 0x18)
473            kernelStats->mode(Kernel::user);
474        else
475            kernelStats->mode(Kernel::kernel);
476
477      case AlphaISA::IPR_ICM:
478        // only write two mode bits - processor mode
479        ipr[idx] = val & 0x18;
480        break;
481
482      case AlphaISA::IPR_ALT_MODE:
483        // only write two mode bits - processor mode
484        ipr[idx] = val & 0x18;
485        break;
486
487      case AlphaISA::IPR_MCSR:
488        // more here after optimization...
489        ipr[idx] = val;
490        break;
491
492      case AlphaISA::IPR_SIRR:
493        // only write software interrupt mask
494        ipr[idx] = val & 0x7fff0;
495        break;
496
497      case AlphaISA::IPR_ICSR:
498        ipr[idx] = val & ULL(0xffffff0300);
499        break;
500
501      case AlphaISA::IPR_IVPTBR:
502      case AlphaISA::IPR_MVPTBR:
503        ipr[idx] = val & ULL(0xffffffffc0000000);
504        break;
505
506      case AlphaISA::IPR_DC_TEST_CTL:
507        ipr[idx] = val & 0x1ffb;
508        break;
509
510      case AlphaISA::IPR_DC_MODE:
511      case AlphaISA::IPR_MAF_MODE:
512        ipr[idx] = val & 0x3f;
513        break;
514
515      case AlphaISA::IPR_ITB_ASN:
516        ipr[idx] = val & 0x7f0;
517        break;
518
519      case AlphaISA::IPR_DTB_ASN:
520        ipr[idx] = val & ULL(0xfe00000000000000);
521        break;
522
523      case AlphaISA::IPR_EXC_SUM:
524      case AlphaISA::IPR_EXC_MASK:
525        // any write to this register clears it
526        ipr[idx] = 0;
527        break;
528
529      case AlphaISA::IPR_INTID:
530      case AlphaISA::IPR_SL_RCV:
531      case AlphaISA::IPR_MM_STAT:
532      case AlphaISA::IPR_ITB_PTE_TEMP:
533      case AlphaISA::IPR_DTB_PTE_TEMP:
534        // read-only registers
535        return Unimplemented_Opcode_Fault;
536
537      case AlphaISA::IPR_HWINT_CLR:
538      case AlphaISA::IPR_SL_XMIT:
539      case AlphaISA::IPR_DC_FLUSH:
540      case AlphaISA::IPR_IC_FLUSH:
541        // the following are write only
542        ipr[idx] = val;
543        break;
544
545      case AlphaISA::IPR_DTB_IA:
546        // really a control write
547        ipr[idx] = 0;
548
549        dtb->flushAll();
550        break;
551
552      case AlphaISA::IPR_DTB_IAP:
553        // really a control write
554        ipr[idx] = 0;
555
556        dtb->flushProcesses();
557        break;
558
559      case AlphaISA::IPR_DTB_IS:
560        // really a control write
561        ipr[idx] = val;
562
563        dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
564        break;
565
566      case AlphaISA::IPR_DTB_TAG: {
567          struct AlphaISA::PTE pte;
568
569          // FIXME: granularity hints NYI...
570          if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
571              panic("PTE GH field != 0");
572
573          // write entire quad
574          ipr[idx] = val;
575
576          // construct PTE for new entry
577          pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
578          pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
579          pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
580          pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
581          pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
582          pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
583          pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
584
585          // insert new TAG/PTE value into data TLB
586          dtb->insert(val, pte);
587      }
588        break;
589
590      case AlphaISA::IPR_ITB_PTE: {
591          struct AlphaISA::PTE pte;
592
593          // FIXME: granularity hints NYI...
594          if (ITB_PTE_GH(val) != 0)
595              panic("PTE GH field != 0");
596
597          // write entire quad
598          ipr[idx] = val;
599
600          // construct PTE for new entry
601          pte.ppn = ITB_PTE_PPN(val);
602          pte.xre = ITB_PTE_XRE(val);
603          pte.xwe = 0;
604          pte.fonr = ITB_PTE_FONR(val);
605          pte.fonw = ITB_PTE_FONW(val);
606          pte.asma = ITB_PTE_ASMA(val);
607          pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
608
609          // insert new TAG/PTE value into data TLB
610          itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
611      }
612        break;
613
614      case AlphaISA::IPR_ITB_IA:
615        // really a control write
616        ipr[idx] = 0;
617
618        itb->flushAll();
619        break;
620
621      case AlphaISA::IPR_ITB_IAP:
622        // really a control write
623        ipr[idx] = 0;
624
625        itb->flushProcesses();
626        break;
627
628      case AlphaISA::IPR_ITB_IS:
629        // really a control write
630        ipr[idx] = val;
631
632        itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
633        break;
634
635      default:
636        // invalid IPR
637        return Unimplemented_Opcode_Fault;
638    }
639
640    // no error...
641    return No_Fault;
642}
643
644/**
645 * Check for special simulator handling of specific PAL calls.
646 * If return value is false, actual PAL call will be suppressed.
647 */
648bool
649ExecContext::simPalCheck(int palFunc)
650{
651    kernelStats->callpal(palFunc);
652
653    switch (palFunc) {
654      case PAL::halt:
655        halt();
656        if (--System::numSystemsRunning == 0)
657            new SimExitEvent("all cpus halted");
658        break;
659
660      case PAL::bpt:
661      case PAL::bugchk:
662        if (system->breakpoint())
663            return false;
664        break;
665    }
666
667    return true;
668}
669
670//Forward instantiation for FastCPU object
671template
672void AlphaISA::processInterrupts(FastCPU *xc);
673
674//Forward instantiation for FastCPU object
675template
676void AlphaISA::zeroRegisters(FastCPU *xc);
677
678#endif // FULL_SYSTEM
679