ev5.cc revision 1133 
1/* $Id$ */
2
3#include "arch/alpha/alpha_memory.hh"
4#include "arch/alpha/isa_traits.hh"
5#include "arch/alpha/osfpal.hh"
6#include "base/kgdb.h"
7#include "base/remote_gdb.hh"
8#include "base/stats/events.hh"
9#include "cpu/base_cpu.hh"
10#include "cpu/exec_context.hh"
11#include "cpu/fast_cpu/fast_cpu.hh"
12#include "kern/kernel_stats.hh"
13#include "sim/debug.hh"
14#include "sim/sim_events.hh"
15
16#ifdef FULL_SYSTEM
17
18#ifndef SYSTEM_EV5
19#error This code is only valid for EV5 systems
20#endif
21
22////////////////////////////////////////////////////////////////////////
23//
24//
25//
26void
27AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
28{
29    if (regs->pal_shadow == use_shadow)
30        panic("swap_palshadow: wrong PAL shadow state");
31
32    regs->pal_shadow = use_shadow;
33
34    for (int i = 0; i < NumIntRegs; i++) {
35        if (reg_redir[i]) {
36            IntReg temp = regs->intRegFile[i];
37            regs->intRegFile[i] = regs->palregs[i];
38            regs->palregs[i] = temp;
39        }
40    }
41}
42
43////////////////////////////////////////////////////////////////////////
44//
45//  Machine dependent functions
46//
47void
48AlphaISA::initCPU(RegFile *regs)
49{
50    initIPRs(regs);
51    // CPU comes up with PAL regs enabled
52    swap_palshadow(regs, true);
53
54    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
55    regs->npc = regs->pc + sizeof(MachInst);
56}
57
58////////////////////////////////////////////////////////////////////////
59//
60// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
61//
62Addr
63AlphaISA::fault_addr[Num_Faults] = {
64    0x0000,	/* No_Fault */
65    0x0001,	/* Reset_Fault */
66    0x0401,	/* Machine_Check_Fault */
67    0x0501,	/* Arithmetic_Fault */
68    0x0101,	/* Interrupt_Fault */
69    0x0201,	/* Ndtb_Miss_Fault */
70    0x0281,	/* Pdtb_Miss_Fault */
71    0x0301,	/* Alignment_Fault */
72    0x0381,	/* DTB_Fault_Fault */
73    0x0381,	/* DTB_Acv_Fault */
74    0x0181,	/* ITB_Miss_Fault */
75    0x0181,	/* ITB_Fault_Fault */
76    0x0081,	/* ITB_Acv_Fault */
77    0x0481,	/* Unimplemented_Opcode_Fault */
78    0x0581,	/* Fen_Fault */
79    0x2001,	/* Pal_Fault */
80    0x0501,	/* Integer_Overflow_Fault: maps to Arithmetic_Fault */
81};
82
83const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
84    /*  0 */ 0, 0, 0, 0, 0, 0, 0, 0,
85    /*  8 */ 1, 1, 1, 1, 1, 1, 1, 0,
86    /* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
87    /* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
88
89////////////////////////////////////////////////////////////////////////
90//
91//
92//
93void
94AlphaISA::initIPRs(RegFile *regs)
95{
96    uint64_t *ipr = regs->ipr;
97
98    bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
99    ipr[IPR_PAL_BASE] = PAL_BASE;
100    ipr[IPR_MCSR] = 0x6;
101}
102
103
104template <class CPU>
105void
106AlphaISA::processInterrupts(CPU *cpu)
107{
108    //Check if there are any outstanding interrupts
109    //Handle the interrupts
110    int ipl = 0;
111    int summary = 0;
112    IntReg *ipr = cpu->getIprPtr();
113
114    cpu->checkInterrupts = false;
115
116    if (ipr[IPR_ASTRR])
117        panic("asynchronous traps not implemented\n");
118
119    if (ipr[IPR_SIRR]) {
120        for (int i = INTLEVEL_SOFTWARE_MIN;
121             i < INTLEVEL_SOFTWARE_MAX; i++) {
122            if (ipr[IPR_SIRR] & (ULL(1) << i)) {
123                // See table 4-19 of the 21164 hardware reference
124                ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
125                summary |= (ULL(1) << i);
126            }
127        }
128    }
129
130    uint64_t interrupts = cpu->intr_status();
131
132    if (interrupts) {
133        for (int i = INTLEVEL_EXTERNAL_MIN;
134             i < INTLEVEL_EXTERNAL_MAX; i++) {
135            if (interrupts & (ULL(1) << i)) {
136                // See table 4-19 of the 21164 hardware reference
137                ipl = i;
138                summary |= (ULL(1) << i);
139            }
140        }
141    }
142
143    if (ipl && ipl > ipr[IPR_IPLR]) {
144        ipr[IPR_ISR] = summary;
145        ipr[IPR_INTID] = ipl;
146        cpu->trap(Interrupt_Fault);
147        DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
148                ipr[IPR_IPLR], ipl, summary);
149    }
150
151}
152
153template <class CPU>
154void
155AlphaISA::zeroRegisters(CPU *cpu)
156{
157    // Insure ISA semantics
158    // (no longer very clean due to the change in setIntReg() in the
159    // cpu model.  Consider changing later.)
160    cpu->xc->setIntReg(ZeroReg, 0);
161    cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
162}
163
164void
165ExecContext::ev5_trap(Fault fault)
166{
167    DPRINTF(Fault, "Fault %s at PC: %#x\n", FaultName(fault), regs.pc);
168    cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
169
170    assert(!misspeculating());
171    kernelStats->fault(fault);
172
173    if (fault == Arithmetic_Fault)
174        panic("Arithmetic traps are unimplemented!");
175
176    AlphaISA::InternalProcReg *ipr = regs.ipr;
177
178    // exception restart address
179    if (fault != Interrupt_Fault || !PC_PAL(regs.pc))
180        ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
181
182    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
183        fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
184        // traps...  skip faulting instruction
185        ipr[AlphaISA::IPR_EXC_ADDR] += 4;
186    }
187
188    if (!PC_PAL(regs.pc))
189        AlphaISA::swap_palshadow(&regs, true);
190
191    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
192    regs.npc = regs.pc + sizeof(MachInst);
193}
194
195
196void
197AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
198{
199    InternalProcReg *ipr = regs->ipr;
200    bool use_pc = (fault == No_Fault);
201
202    if (fault == Arithmetic_Fault)
203        panic("arithmetic faults NYI...");
204
205    // compute exception restart address
206    if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
207        // traps...  skip faulting instruction
208        ipr[IPR_EXC_ADDR] = regs->pc + 4;
209    } else {
210        // fault, post fault at excepting instruction
211        ipr[IPR_EXC_ADDR] = regs->pc;
212    }
213
214    // jump to expection address (PAL PC bit set here as well...)
215    if (!use_pc)
216        regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
217    else
218        regs->npc = ipr[IPR_PAL_BASE] + pc;
219
220    // that's it! (orders of magnitude less painful than x86)
221}
222
223Fault
224ExecContext::hwrei()
225{
226    uint64_t *ipr = regs.ipr;
227
228    if (!PC_PAL(regs.pc))
229        return Unimplemented_Opcode_Fault;
230
231    setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
232
233    if (!misspeculating()) {
234        kernelStats->hwrei();
235
236        if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
237            AlphaISA::swap_palshadow(&regs, false);
238
239        cpu->checkInterrupts = true;
240    }
241
242    // FIXME: XXX check for interrupts? XXX
243    return No_Fault;
244}
245
246uint64_t
247ExecContext::readIpr(int idx, Fault &fault)
248{
249    uint64_t *ipr = regs.ipr;
250    uint64_t retval = 0;	// return value, default 0
251
252    switch (idx) {
253      case AlphaISA::IPR_PALtemp0:
254      case AlphaISA::IPR_PALtemp1:
255      case AlphaISA::IPR_PALtemp2:
256      case AlphaISA::IPR_PALtemp3:
257      case AlphaISA::IPR_PALtemp4:
258      case AlphaISA::IPR_PALtemp5:
259      case AlphaISA::IPR_PALtemp6:
260      case AlphaISA::IPR_PALtemp7:
261      case AlphaISA::IPR_PALtemp8:
262      case AlphaISA::IPR_PALtemp9:
263      case AlphaISA::IPR_PALtemp10:
264      case AlphaISA::IPR_PALtemp11:
265      case AlphaISA::IPR_PALtemp12:
266      case AlphaISA::IPR_PALtemp13:
267      case AlphaISA::IPR_PALtemp14:
268      case AlphaISA::IPR_PALtemp15:
269      case AlphaISA::IPR_PALtemp16:
270      case AlphaISA::IPR_PALtemp17:
271      case AlphaISA::IPR_PALtemp18:
272      case AlphaISA::IPR_PALtemp19:
273      case AlphaISA::IPR_PALtemp20:
274      case AlphaISA::IPR_PALtemp21:
275      case AlphaISA::IPR_PALtemp22:
276      case AlphaISA::IPR_PALtemp23:
277      case AlphaISA::IPR_PAL_BASE:
278
279      case AlphaISA::IPR_IVPTBR:
280      case AlphaISA::IPR_DC_MODE:
281      case AlphaISA::IPR_MAF_MODE:
282      case AlphaISA::IPR_ISR:
283      case AlphaISA::IPR_EXC_ADDR:
284      case AlphaISA::IPR_IC_PERR_STAT:
285      case AlphaISA::IPR_DC_PERR_STAT:
286      case AlphaISA::IPR_MCSR:
287      case AlphaISA::IPR_ASTRR:
288      case AlphaISA::IPR_ASTER:
289      case AlphaISA::IPR_SIRR:
290      case AlphaISA::IPR_ICSR:
291      case AlphaISA::IPR_ICM:
292      case AlphaISA::IPR_DTB_CM:
293      case AlphaISA::IPR_IPLR:
294      case AlphaISA::IPR_INTID:
295      case AlphaISA::IPR_PMCTR:
296        // no side-effect
297        retval = ipr[idx];
298        break;
299
300      case AlphaISA::IPR_CC:
301        retval |= ipr[idx] & ULL(0xffffffff00000000);
302        retval |= curTick  & ULL(0x00000000ffffffff);
303        break;
304
305      case AlphaISA::IPR_VA:
306        retval = ipr[idx];
307        break;
308
309      case AlphaISA::IPR_VA_FORM:
310      case AlphaISA::IPR_MM_STAT:
311      case AlphaISA::IPR_IFAULT_VA_FORM:
312      case AlphaISA::IPR_EXC_MASK:
313      case AlphaISA::IPR_EXC_SUM:
314        retval = ipr[idx];
315        break;
316
317      case AlphaISA::IPR_DTB_PTE:
318        {
319            AlphaISA::PTE &pte = dtb->index(!misspeculating());
320
321            retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
322            retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
323            retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
324            retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
325            retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
326            retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
327            retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
328        }
329        break;
330
331        // write only registers
332      case AlphaISA::IPR_HWINT_CLR:
333      case AlphaISA::IPR_SL_XMIT:
334      case AlphaISA::IPR_DC_FLUSH:
335      case AlphaISA::IPR_IC_FLUSH:
336      case AlphaISA::IPR_ALT_MODE:
337      case AlphaISA::IPR_DTB_IA:
338      case AlphaISA::IPR_DTB_IAP:
339      case AlphaISA::IPR_ITB_IA:
340      case AlphaISA::IPR_ITB_IAP:
341        fault = Unimplemented_Opcode_Fault;
342        break;
343
344      default:
345        // invalid IPR
346        fault = Unimplemented_Opcode_Fault;
347        break;
348    }
349
350    return retval;
351}
352
353#ifdef DEBUG
354// Cause the simulator to break when changing to the following IPL
355int break_ipl = -1;
356#endif
357
358Fault
359ExecContext::setIpr(int idx, uint64_t val)
360{
361    uint64_t *ipr = regs.ipr;
362    uint64_t old;
363
364    if (misspeculating())
365        return No_Fault;
366
367    switch (idx) {
368      case AlphaISA::IPR_PALtemp0:
369      case AlphaISA::IPR_PALtemp1:
370      case AlphaISA::IPR_PALtemp2:
371      case AlphaISA::IPR_PALtemp3:
372      case AlphaISA::IPR_PALtemp4:
373      case AlphaISA::IPR_PALtemp5:
374      case AlphaISA::IPR_PALtemp6:
375      case AlphaISA::IPR_PALtemp7:
376      case AlphaISA::IPR_PALtemp8:
377      case AlphaISA::IPR_PALtemp9:
378      case AlphaISA::IPR_PALtemp10:
379      case AlphaISA::IPR_PALtemp11:
380      case AlphaISA::IPR_PALtemp12:
381      case AlphaISA::IPR_PALtemp13:
382      case AlphaISA::IPR_PALtemp14:
383      case AlphaISA::IPR_PALtemp15:
384      case AlphaISA::IPR_PALtemp16:
385      case AlphaISA::IPR_PALtemp17:
386      case AlphaISA::IPR_PALtemp18:
387      case AlphaISA::IPR_PALtemp19:
388      case AlphaISA::IPR_PALtemp20:
389      case AlphaISA::IPR_PALtemp21:
390      case AlphaISA::IPR_PALtemp22:
391      case AlphaISA::IPR_PAL_BASE:
392      case AlphaISA::IPR_IC_PERR_STAT:
393      case AlphaISA::IPR_DC_PERR_STAT:
394      case AlphaISA::IPR_PMCTR:
395        // write entire quad w/ no side-effect
396        ipr[idx] = val;
397        break;
398
399      case AlphaISA::IPR_CC_CTL:
400        // This IPR resets the cycle counter.  We assume this only
401        // happens once... let's verify that.
402        assert(ipr[idx] == 0);
403        ipr[idx] = 1;
404        break;
405
406      case AlphaISA::IPR_CC:
407        // This IPR only writes the upper 64 bits.  It's ok to write
408        // all 64 here since we mask out the lower 32 in rpcc (see
409        // isa_desc).
410        ipr[idx] = val;
411        break;
412
413      case AlphaISA::IPR_PALtemp23:
414        // write entire quad w/ no side-effect
415        old = ipr[idx];
416        ipr[idx] = val;
417        kernelStats->context(old, val);
418        break;
419
420      case AlphaISA::IPR_DTB_PTE:
421        // write entire quad w/ no side-effect, tag is forthcoming
422        ipr[idx] = val;
423        break;
424
425      case AlphaISA::IPR_EXC_ADDR:
426        // second least significant bit in PC is always zero
427        ipr[idx] = val & ~2;
428        break;
429
430      case AlphaISA::IPR_ASTRR:
431      case AlphaISA::IPR_ASTER:
432        // only write least significant four bits - privilege mask
433        ipr[idx] = val & 0xf;
434        break;
435
436      case AlphaISA::IPR_IPLR:
437#ifdef DEBUG
438        if (break_ipl != -1 && break_ipl == (val & 0x1f))
439            debug_break();
440#endif
441
442        // only write least significant five bits - interrupt level
443        ipr[idx] = val & 0x1f;
444        kernelStats->swpipl(ipr[idx]);
445        break;
446
447      case AlphaISA::IPR_DTB_CM:
448        if (val & 0x18)
449            kernelStats->mode(Kernel::user);
450        else
451            kernelStats->mode(Kernel::kernel);
452
453      case AlphaISA::IPR_ICM:
454        // only write two mode bits - processor mode
455        ipr[idx] = val & 0x18;
456        break;
457
458      case AlphaISA::IPR_ALT_MODE:
459        // only write two mode bits - processor mode
460        ipr[idx] = val & 0x18;
461        break;
462
463      case AlphaISA::IPR_MCSR:
464        // more here after optimization...
465        ipr[idx] = val;
466        break;
467
468      case AlphaISA::IPR_SIRR:
469        // only write software interrupt mask
470        ipr[idx] = val & 0x7fff0;
471        break;
472
473      case AlphaISA::IPR_ICSR:
474        ipr[idx] = val & ULL(0xffffff0300);
475        break;
476
477      case AlphaISA::IPR_IVPTBR:
478      case AlphaISA::IPR_MVPTBR:
479        ipr[idx] = val & ULL(0xffffffffc0000000);
480        break;
481
482      case AlphaISA::IPR_DC_TEST_CTL:
483        ipr[idx] = val & 0x1ffb;
484        break;
485
486      case AlphaISA::IPR_DC_MODE:
487      case AlphaISA::IPR_MAF_MODE:
488        ipr[idx] = val & 0x3f;
489        break;
490
491      case AlphaISA::IPR_ITB_ASN:
492        ipr[idx] = val & 0x7f0;
493        break;
494
495      case AlphaISA::IPR_DTB_ASN:
496        ipr[idx] = val & ULL(0xfe00000000000000);
497        break;
498
499      case AlphaISA::IPR_EXC_SUM:
500      case AlphaISA::IPR_EXC_MASK:
501        // any write to this register clears it
502        ipr[idx] = 0;
503        break;
504
505      case AlphaISA::IPR_INTID:
506      case AlphaISA::IPR_SL_RCV:
507      case AlphaISA::IPR_MM_STAT:
508      case AlphaISA::IPR_ITB_PTE_TEMP:
509      case AlphaISA::IPR_DTB_PTE_TEMP:
510        // read-only registers
511        return Unimplemented_Opcode_Fault;
512
513      case AlphaISA::IPR_HWINT_CLR:
514      case AlphaISA::IPR_SL_XMIT:
515      case AlphaISA::IPR_DC_FLUSH:
516      case AlphaISA::IPR_IC_FLUSH:
517        // the following are write only
518        ipr[idx] = val;
519        break;
520
521      case AlphaISA::IPR_DTB_IA:
522        // really a control write
523        ipr[idx] = 0;
524
525        dtb->flushAll();
526        break;
527
528      case AlphaISA::IPR_DTB_IAP:
529        // really a control write
530        ipr[idx] = 0;
531
532        dtb->flushProcesses();
533        break;
534
535      case AlphaISA::IPR_DTB_IS:
536        // really a control write
537        ipr[idx] = val;
538
539        dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
540        break;
541
542      case AlphaISA::IPR_DTB_TAG: {
543          struct AlphaISA::PTE pte;
544
545          // FIXME: granularity hints NYI...
546          if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
547              panic("PTE GH field != 0");
548
549          // write entire quad
550          ipr[idx] = val;
551
552          // construct PTE for new entry
553          pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
554          pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
555          pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
556          pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
557          pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
558          pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
559          pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
560
561          // insert new TAG/PTE value into data TLB
562          dtb->insert(val, pte);
563      }
564        break;
565
566      case AlphaISA::IPR_ITB_PTE: {
567          struct AlphaISA::PTE pte;
568
569          // FIXME: granularity hints NYI...
570          if (ITB_PTE_GH(val) != 0)
571              panic("PTE GH field != 0");
572
573          // write entire quad
574          ipr[idx] = val;
575
576          // construct PTE for new entry
577          pte.ppn = ITB_PTE_PPN(val);
578          pte.xre = ITB_PTE_XRE(val);
579          pte.xwe = 0;
580          pte.fonr = ITB_PTE_FONR(val);
581          pte.fonw = ITB_PTE_FONW(val);
582          pte.asma = ITB_PTE_ASMA(val);
583          pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
584
585          // insert new TAG/PTE value into data TLB
586          itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
587      }
588        break;
589
590      case AlphaISA::IPR_ITB_IA:
591        // really a control write
592        ipr[idx] = 0;
593
594        itb->flushAll();
595        break;
596
597      case AlphaISA::IPR_ITB_IAP:
598        // really a control write
599        ipr[idx] = 0;
600
601        itb->flushProcesses();
602        break;
603
604      case AlphaISA::IPR_ITB_IS:
605        // really a control write
606        ipr[idx] = val;
607
608        itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
609        break;
610
611      default:
612        // invalid IPR
613        return Unimplemented_Opcode_Fault;
614    }
615
616    // no error...
617    return No_Fault;
618}
619
620/**
621 * Check for special simulator handling of specific PAL calls.
622 * If return value is false, actual PAL call will be suppressed.
623 */
624bool
625ExecContext::simPalCheck(int palFunc)
626{
627    kernelStats->callpal(palFunc);
628
629    switch (palFunc) {
630      case PAL::halt:
631        halt();
632        if (--System::numSystemsRunning == 0)
633            new SimExitEvent("all cpus halted");
634        break;
635
636      case PAL::bpt:
637      case PAL::bugchk:
638        if (system->breakpoint())
639            return false;
640        break;
641    }
642
643    return true;
644}
645
646//Forward instantiation for FastCPU object
647template
648void AlphaISA::processInterrupts(FastCPU *xc);
649
650//Forward instantiation for FastCPU object
651template
652void AlphaISA::zeroRegisters(FastCPU *xc);
653
654#endif // FULL_SYSTEM
655