SConscript revision 9020
12207SN/A# -*- mode:python -*- 25254Sksewell@umich.edu 35254Sksewell@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 42207SN/A# All rights reserved. 55254Sksewell@umich.edu# 65254Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu# modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu# met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu# notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu# contributors may be used to endorse or promote products derived from 152207SN/A# this software without specific prior written permission. 165254Sksewell@umich.edu# 175254Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285254Sksewell@umich.edu# 295254Sksewell@umich.edu# Authors: Steve Reinhardt 305254Sksewell@umich.edu 312207SN/Aimport sys 322207SN/Aimport os 3311793Sbrandon.potter@amd.com 3411793Sbrandon.potter@amd.comImport('*') 352474SN/A 368229Snate@binkert.org################################################################# 372454SN/A# 382454SN/A# ISA "switch header" generation. 392680Sktlim@umich.edu# 408232Snate@binkert.org# Auto-generate arch headers that include the right ISA-specific 416650Sksewell@umich.edu# header based on the setting of THE_ISA preprocessor variable. 4211854Sbrandon.potter@amd.com# 436650Sksewell@umich.edu################################################################# 446650Sksewell@umich.edu 4511800Sbrandon.potter@amd.com# List of headers to generate 462474SN/Aisa_switch_hdrs = Split(''' 472207SN/A decoder.hh 482447SN/A interrupts.hh 492474SN/A isa.hh 502447SN/A isa_traits.hh 5111851Sbrandon.potter@amd.com kernel_stats.hh 5211851Sbrandon.potter@amd.com locked_mem.hh 532474SN/A microcode_rom.hh 542686Sksewell@umich.edu mmapped_ipr.hh 552686Sksewell@umich.edu mt.hh 562935Sksewell@umich.edu process.hh 572474SN/A predecoder.hh 582474SN/A registers.hh 592474SN/A remote_gdb.hh 602474SN/A stacktrace.hh 612686Sksewell@umich.edu tlb.hh 622686Sksewell@umich.edu types.hh 6310318Sandreas.hansson@arm.com utility.hh 642686Sksewell@umich.edu vtophys.hh 656811SMatt DeVuyst ''') 6611386Ssteve.reinhardt@amd.com 672474SN/A# Set up this directory to support switching headers 682474SN/Amake_switching_dir('arch', isa_switch_hdrs, env) 692474SN/A 7011851Sbrandon.potter@amd.com################################################################# 712474SN/A# 7211851Sbrandon.potter@amd.com# Include architecture-specific files. 736650Sksewell@umich.edu# 7410318Sandreas.hansson@arm.com################################################################# 752474SN/A 765958Sgblack@eecs.umich.edu# 776811SMatt DeVuyst# Build a SCons scanner for ISA files 786650Sksewell@umich.edu# 7911851Sbrandon.potter@amd.comimport SCons.Scanner 806650Sksewell@umich.edu 816811SMatt DeVuystisa_scanner = SCons.Scanner.Classic("ISAScan", 826811SMatt DeVuyst [".isa", ".ISA"], 8311389Sbrandon.potter@amd.com "SRCDIR", 8411389Sbrandon.potter@amd.com r'^\s*##include\s+"([\w/.-]*)"') 8511389Sbrandon.potter@amd.com 866650Sksewell@umich.eduenv.Append(SCANNERS = isa_scanner) 876650Sksewell@umich.edu 886650Sksewell@umich.edu# 896811SMatt DeVuyst# Now create a Builder object that uses isa_parser.py to generate C++ 906811SMatt DeVuyst# output from the ISA description (*.isa) files. 916811SMatt DeVuyst# 926811SMatt DeVuyst 936811SMatt DeVuystisa_parser = File('isa_parser.py') 946811SMatt DeVuyst 956811SMatt DeVuyst# The emitter patches up the sources & targets to include the 9610318Sandreas.hansson@arm.com# autogenerated files as targets and isa parser itself as a source. 976811SMatt DeVuystdef isa_desc_emitter(target, source, env): 986811SMatt DeVuyst cpu_models = list(env['CPU_MODELS']) 996811SMatt DeVuyst cpu_models.append('CheckerCPU') 1006811SMatt DeVuyst 1016811SMatt DeVuyst # Several files are generated from the ISA description. 1026811SMatt DeVuyst # We always get the basic decoder and header file. 1036811SMatt DeVuyst target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ] 1046811SMatt DeVuyst # We also get an execute file for each selected CPU model. 1056811SMatt DeVuyst target += [CpuModel.dict[cpu].filename for cpu in cpu_models] 1066811SMatt DeVuyst 1076811SMatt DeVuyst # List the isa parser as a source. 10811389Sbrandon.potter@amd.com source += [ isa_parser ] 10911389Sbrandon.potter@amd.com # Add in the CPU models. 11011389Sbrandon.potter@amd.com source += [ Value(m) for m in cpu_models ] 11111389Sbrandon.potter@amd.com 1126811SMatt DeVuyst return [os.path.join("generated", t) for t in target], source 1136811SMatt DeVuyst 1146811SMatt DeVuystARCH_DIR = Dir('.') 1156811SMatt DeVuyst 1166811SMatt DeVuyst# import ply here because SCons screws with sys.path when performing actions. 1176811SMatt DeVuystimport ply 1186811SMatt DeVuyst 1196811SMatt DeVuystdef isa_desc_action_func(target, source, env): 1206811SMatt DeVuyst # Add the current directory to the system path so we can import files 1216811SMatt DeVuyst sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ] 1226650Sksewell@umich.edu import isa_parser 1236650Sksewell@umich.edu 1246811SMatt DeVuyst # Skip over the ISA description itself and the parser to the CPU models. 1256811SMatt DeVuyst models = [ s.get_contents() for s in source[2:] ] 1266650Sksewell@umich.edu cpu_models = [CpuModel.dict[cpu] for cpu in models] 1276650Sksewell@umich.edu parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models) 1286650Sksewell@umich.edu parser.parse_isa_desc(source[0].abspath) 1296650Sksewell@umich.eduisa_desc_action = MakeAction(isa_desc_action_func, Transform("ISA DESC", 1)) 1306650Sksewell@umich.edu 1316650Sksewell@umich.edu# Also include the CheckerCPU as one of the models if it is being 1326650Sksewell@umich.edu# enabled via command line. 1336650Sksewell@umich.eduisa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter) 1346650Sksewell@umich.edu 1356650Sksewell@umich.eduenv.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) 1366811SMatt DeVuyst 1376811SMatt DeVuystDebugFlag('IntRegs') 1386811SMatt DeVuystDebugFlag('FloatRegs') 1396811SMatt DeVuystDebugFlag('MiscRegs') 1406811SMatt DeVuystCompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ]) 1416650Sksewell@umich.edu