SConscript revision 8961
14202Sbinkertn@umich.edu# -*- mode:python -*- 24202Sbinkertn@umich.edu 34202Sbinkertn@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 44202Sbinkertn@umich.edu# All rights reserved. 54202Sbinkertn@umich.edu# 64202Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 74202Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 84202Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 94202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 104202Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 114202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 124202Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 134202Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 144202Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 154202Sbinkertn@umich.edu# this software without specific prior written permission. 164202Sbinkertn@umich.edu# 174202Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 184202Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 194202Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 204202Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 214202Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 224202Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 234202Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 244202Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 254202Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 264202Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 274202Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 284202Sbinkertn@umich.edu# 294202Sbinkertn@umich.edu# Authors: Steve Reinhardt 304202Sbinkertn@umich.edu 314202Sbinkertn@umich.eduimport sys 324202Sbinkertn@umich.eduimport os 334202Sbinkertn@umich.edu 344202Sbinkertn@umich.eduImport('*') 354202Sbinkertn@umich.edu 364202Sbinkertn@umich.edu################################################################# 374202Sbinkertn@umich.edu# 38# ISA "switch header" generation. 39# 40# Auto-generate arch headers that include the right ISA-specific 41# header based on the setting of THE_ISA preprocessor variable. 42# 43################################################################# 44 45# List of headers to generate 46isa_switch_hdrs = Split(''' 47 interrupts.hh 48 isa.hh 49 isa_traits.hh 50 kernel_stats.hh 51 locked_mem.hh 52 microcode_rom.hh 53 mmapped_ipr.hh 54 mt.hh 55 process.hh 56 predecoder.hh 57 registers.hh 58 remote_gdb.hh 59 stacktrace.hh 60 tlb.hh 61 types.hh 62 utility.hh 63 vtophys.hh 64 ''') 65 66# Set up this directory to support switching headers 67make_switching_dir('arch', isa_switch_hdrs, env) 68 69################################################################# 70# 71# Include architecture-specific files. 72# 73################################################################# 74 75# 76# Build a SCons scanner for ISA files 77# 78import SCons.Scanner 79 80isa_scanner = SCons.Scanner.Classic("ISAScan", 81 [".isa", ".ISA"], 82 "SRCDIR", 83 r'^\s*##include\s+"([\w/.-]*)"') 84 85env.Append(SCANNERS = isa_scanner) 86 87# 88# Now create a Builder object that uses isa_parser.py to generate C++ 89# output from the ISA description (*.isa) files. 90# 91 92isa_parser = File('isa_parser.py') 93 94# The emitter patches up the sources & targets to include the 95# autogenerated files as targets and isa parser itself as a source. 96def isa_desc_emitter(target, source, env): 97 cpu_models = list(env['CPU_MODELS']) 98 cpu_models.append('CheckerCPU') 99 100 # Several files are generated from the ISA description. 101 # We always get the basic decoder and header file. 102 target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ] 103 # We also get an execute file for each selected CPU model. 104 target += [CpuModel.dict[cpu].filename for cpu in cpu_models] 105 106 # List the isa parser as a source. 107 source += [ isa_parser ] 108 # Add in the CPU models. 109 source += [ Value(m) for m in cpu_models ] 110 111 return [os.path.join("generated", t) for t in target], source 112 113ARCH_DIR = Dir('.') 114 115# import ply here because SCons screws with sys.path when performing actions. 116import ply 117 118def isa_desc_action_func(target, source, env): 119 # Add the current directory to the system path so we can import files 120 sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ] 121 import isa_parser 122 123 # Skip over the ISA description itself and the parser to the CPU models. 124 models = [ s.get_contents() for s in source[2:] ] 125 cpu_models = [CpuModel.dict[cpu] for cpu in models] 126 parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models) 127 parser.parse_isa_desc(source[0].abspath) 128isa_desc_action = MakeAction(isa_desc_action_func, Transform("ISA DESC", 1)) 129 130# Also include the CheckerCPU as one of the models if it is being 131# enabled via command line. 132isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter) 133 134env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) 135 136DebugFlag('IntRegs') 137DebugFlag('FloatRegs') 138DebugFlag('MiscRegs') 139CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ]) 140