SConscript revision 9920
1955SN/A# -*- mode:python -*- 2955SN/A 310841Sandreas.sandberg@arm.com# Copyright (c) 2006 The Regents of The University of Michigan 49812Sandreas.hansson@arm.com# All rights reserved. 59812Sandreas.hansson@arm.com# 69812Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 79812Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 89812Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 99812Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 109812Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 119812Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 129812Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 139812Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 149812Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 157816Ssteve.reinhardt@amd.com# this software without specific prior written permission. 165871Snate@binkert.org# 171762SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18955SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19955SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20955SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21955SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22955SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23955SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24955SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25955SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26955SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27955SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28955SN/A# 29955SN/A# Authors: Steve Reinhardt 30955SN/A 31955SN/Aimport sys 32955SN/Aimport os 33955SN/A 34955SN/AImport('*') 35955SN/A 36955SN/A################################################################# 37955SN/A# 38955SN/A# ISA "switch header" generation. 39955SN/A# 40955SN/A# Auto-generate arch headers that include the right ISA-specific 41955SN/A# header based on the setting of THE_ISA preprocessor variable. 422665Ssaidi@eecs.umich.edu# 432665Ssaidi@eecs.umich.edu################################################################# 445863Snate@binkert.org 45955SN/A# List of headers to generate 46955SN/Aisa_switch_hdrs = Split(''' 47955SN/A decoder.hh 48955SN/A interrupts.hh 49955SN/A isa.hh 508878Ssteve.reinhardt@amd.com isa_traits.hh 512632Sstever@eecs.umich.edu kernel_stats.hh 528878Ssteve.reinhardt@amd.com locked_mem.hh 532632Sstever@eecs.umich.edu microcode_rom.hh 54955SN/A mmapped_ipr.hh 558878Ssteve.reinhardt@amd.com mt.hh 562632Sstever@eecs.umich.edu process.hh 572761Sstever@eecs.umich.edu registers.hh 582632Sstever@eecs.umich.edu remote_gdb.hh 592632Sstever@eecs.umich.edu stacktrace.hh 602632Sstever@eecs.umich.edu tlb.hh 612761Sstever@eecs.umich.edu types.hh 622761Sstever@eecs.umich.edu utility.hh 632761Sstever@eecs.umich.edu vtophys.hh 648878Ssteve.reinhardt@amd.com ''') 658878Ssteve.reinhardt@amd.com 662761Sstever@eecs.umich.edu# Set up this directory to support switching headers 672761Sstever@eecs.umich.edumake_switching_dir('arch', isa_switch_hdrs, env) 682761Sstever@eecs.umich.edu 692761Sstever@eecs.umich.edu################################################################# 702761Sstever@eecs.umich.edu# 718878Ssteve.reinhardt@amd.com# Include architecture-specific files. 728878Ssteve.reinhardt@amd.com# 732632Sstever@eecs.umich.edu################################################################# 742632Sstever@eecs.umich.edu 758878Ssteve.reinhardt@amd.com# 768878Ssteve.reinhardt@amd.com# Build a SCons scanner for ISA files 772632Sstever@eecs.umich.edu# 78955SN/Aimport SCons.Scanner 79955SN/A 80955SN/Aisa_scanner = SCons.Scanner.Classic("ISAScan", 815863Snate@binkert.org [".isa", ".ISA"], 825863Snate@binkert.org "SRCDIR", 835863Snate@binkert.org r'^\s*##include\s+"([\w/.-]*)"') 845863Snate@binkert.org 855863Snate@binkert.orgenv.Append(SCANNERS = isa_scanner) 865863Snate@binkert.org 875863Snate@binkert.org# 885863Snate@binkert.org# Now create a Builder object that uses isa_parser.py to generate C++ 895863Snate@binkert.org# output from the ISA description (*.isa) files. 905863Snate@binkert.org# 915863Snate@binkert.org 928878Ssteve.reinhardt@amd.comisa_parser = File('isa_parser.py') 935863Snate@binkert.org 945863Snate@binkert.org# The emitter patches up the sources & targets to include the 955863Snate@binkert.org# autogenerated files as targets and isa parser itself as a source. 969812Sandreas.hansson@arm.comdef isa_desc_emitter(target, source, env): 979812Sandreas.hansson@arm.com cpu_models = list(env['CPU_MODELS']) 985863Snate@binkert.org cpu_models.append('CheckerCPU') 999812Sandreas.hansson@arm.com 1005863Snate@binkert.org # Several files are generated from the ISA description. 1015863Snate@binkert.org # We always get the basic decoder and header file. 1025863Snate@binkert.org target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ] 1039812Sandreas.hansson@arm.com # We also get an execute file for each selected CPU model. 1049812Sandreas.hansson@arm.com target += [CpuModel.dict[cpu].filename for cpu in cpu_models] 1055863Snate@binkert.org 1065863Snate@binkert.org # List the isa parser as a source. 1078878Ssteve.reinhardt@amd.com source += [ isa_parser ] 1085863Snate@binkert.org # Add in the CPU models. 1095863Snate@binkert.org source += [ Value(m) for m in cpu_models ] 1105863Snate@binkert.org 1116654Snate@binkert.org return [os.path.join("generated", t) for t in target], source 11210196SCurtis.Dunham@arm.com 113955SN/AARCH_DIR = Dir('.') 1145396Ssaidi@eecs.umich.edu 1155863Snate@binkert.org# import ply here because SCons screws with sys.path when performing actions. 1165863Snate@binkert.orgimport ply 1174202Sbinkertn@umich.edu 1185863Snate@binkert.orgdef isa_desc_action_func(target, source, env): 1195863Snate@binkert.org # Add the current directory to the system path so we can import files 1205863Snate@binkert.org sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ] 1215863Snate@binkert.org import isa_parser 122955SN/A 1236654Snate@binkert.org # Skip over the ISA description itself and the parser to the CPU models. 1245273Sstever@gmail.com models = [ s.get_contents() for s in source[2:] ] 1255871Snate@binkert.org cpu_models = [CpuModel.dict[cpu] for cpu in models] 1265273Sstever@gmail.com parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models) 1276655Snate@binkert.org parser.parse_isa_desc(source[0].abspath) 1288878Ssteve.reinhardt@amd.comisa_desc_action = MakeAction(isa_desc_action_func, Transform("ISA DESC", 1)) 1296655Snate@binkert.org 1306655Snate@binkert.org# Also include the CheckerCPU as one of the models if it is being 1319219Spower.jg@gmail.com# enabled via command line. 1326655Snate@binkert.orgisa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter) 1335871Snate@binkert.org 1346654Snate@binkert.orgenv.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) 1358947Sandreas.hansson@arm.com 1365396Ssaidi@eecs.umich.eduDebugFlag('IntRegs') 1378120Sgblack@eecs.umich.eduDebugFlag('FloatRegs') 1388120Sgblack@eecs.umich.eduDebugFlag('CCRegs') 1398120Sgblack@eecs.umich.eduDebugFlag('MiscRegs') 1408120Sgblack@eecs.umich.eduCompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'CCRegs', 'MiscRegs' ]) 1418120Sgblack@eecs.umich.edu