SConscript revision 8756
110259SAndrew.Bardsley@arm.com# -*- mode:python -*- 210259SAndrew.Bardsley@arm.com 310259SAndrew.Bardsley@arm.com# Copyright (c) 2006 The Regents of The University of Michigan 410259SAndrew.Bardsley@arm.com# All rights reserved. 510259SAndrew.Bardsley@arm.com# 610259SAndrew.Bardsley@arm.com# Redistribution and use in source and binary forms, with or without 710259SAndrew.Bardsley@arm.com# modification, are permitted provided that the following conditions are 810259SAndrew.Bardsley@arm.com# met: redistributions of source code must retain the above copyright 910259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer; 1010259SAndrew.Bardsley@arm.com# redistributions in binary form must reproduce the above copyright 1110259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer in the 1210259SAndrew.Bardsley@arm.com# documentation and/or other materials provided with the distribution; 1310259SAndrew.Bardsley@arm.com# neither the name of the copyright holders nor the names of its 1410259SAndrew.Bardsley@arm.com# contributors may be used to endorse or promote products derived from 1510259SAndrew.Bardsley@arm.com# this software without specific prior written permission. 1610259SAndrew.Bardsley@arm.com# 1710259SAndrew.Bardsley@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1810259SAndrew.Bardsley@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1910259SAndrew.Bardsley@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2010259SAndrew.Bardsley@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2110259SAndrew.Bardsley@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2210259SAndrew.Bardsley@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2310259SAndrew.Bardsley@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2410259SAndrew.Bardsley@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2510259SAndrew.Bardsley@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2610259SAndrew.Bardsley@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2710259SAndrew.Bardsley@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2810259SAndrew.Bardsley@arm.com# 2910259SAndrew.Bardsley@arm.com# Authors: Steve Reinhardt 3010259SAndrew.Bardsley@arm.com 3110259SAndrew.Bardsley@arm.comimport sys 3210259SAndrew.Bardsley@arm.com 3310259SAndrew.Bardsley@arm.comImport('*') 3410259SAndrew.Bardsley@arm.com 3510259SAndrew.Bardsley@arm.com################################################################# 3610259SAndrew.Bardsley@arm.com# 3710259SAndrew.Bardsley@arm.com# ISA "switch header" generation. 3810259SAndrew.Bardsley@arm.com# 3910259SAndrew.Bardsley@arm.com# Auto-generate arch headers that include the right ISA-specific 4010259SAndrew.Bardsley@arm.com# header based on the setting of THE_ISA preprocessor variable. 4110259SAndrew.Bardsley@arm.com# 4210259SAndrew.Bardsley@arm.com################################################################# 4310259SAndrew.Bardsley@arm.com 4410259SAndrew.Bardsley@arm.com# List of headers to generate 4510259SAndrew.Bardsley@arm.comisa_switch_hdrs = Split(''' 4610259SAndrew.Bardsley@arm.com faults.hh 4710259SAndrew.Bardsley@arm.com interrupts.hh 4810259SAndrew.Bardsley@arm.com isa.hh 4910259SAndrew.Bardsley@arm.com isa_traits.hh 5010259SAndrew.Bardsley@arm.com kernel_stats.hh 5110259SAndrew.Bardsley@arm.com locked_mem.hh 5210259SAndrew.Bardsley@arm.com microcode_rom.hh 5310259SAndrew.Bardsley@arm.com mmapped_ipr.hh 5410259SAndrew.Bardsley@arm.com mt.hh 5510259SAndrew.Bardsley@arm.com process.hh 5610259SAndrew.Bardsley@arm.com predecoder.hh 5710259SAndrew.Bardsley@arm.com registers.hh 5810259SAndrew.Bardsley@arm.com remote_gdb.hh 5910259SAndrew.Bardsley@arm.com stacktrace.hh 6010259SAndrew.Bardsley@arm.com tlb.hh 6110259SAndrew.Bardsley@arm.com types.hh 6210259SAndrew.Bardsley@arm.com utility.hh 6310259SAndrew.Bardsley@arm.com vtophys.hh 6410259SAndrew.Bardsley@arm.com ''') 6510259SAndrew.Bardsley@arm.com 6610259SAndrew.Bardsley@arm.com# Set up this directory to support switching headers 6710259SAndrew.Bardsley@arm.commake_switching_dir('arch', isa_switch_hdrs, env) 6810259SAndrew.Bardsley@arm.com 6910259SAndrew.Bardsley@arm.com################################################################# 7010259SAndrew.Bardsley@arm.com# 7110259SAndrew.Bardsley@arm.com# Include architecture-specific files. 7210259SAndrew.Bardsley@arm.com# 7310259SAndrew.Bardsley@arm.com################################################################# 7410259SAndrew.Bardsley@arm.com 7510259SAndrew.Bardsley@arm.com# 7610259SAndrew.Bardsley@arm.com# Build a SCons scanner for ISA files 7710259SAndrew.Bardsley@arm.com# 7810259SAndrew.Bardsley@arm.comimport SCons.Scanner 7910259SAndrew.Bardsley@arm.com 8010259SAndrew.Bardsley@arm.comisa_scanner = SCons.Scanner.Classic("ISAScan", 8110259SAndrew.Bardsley@arm.com [".isa", ".ISA"], 8210259SAndrew.Bardsley@arm.com "SRCDIR", 8310259SAndrew.Bardsley@arm.com r'^\s*##include\s+"([\w/.-]*)"') 8410259SAndrew.Bardsley@arm.com 8510259SAndrew.Bardsley@arm.comenv.Append(SCANNERS = isa_scanner) 8610259SAndrew.Bardsley@arm.com 8710259SAndrew.Bardsley@arm.com# 8810259SAndrew.Bardsley@arm.com# Now create a Builder object that uses isa_parser.py to generate C++ 8910259SAndrew.Bardsley@arm.com# output from the ISA description (*.isa) files. 9010259SAndrew.Bardsley@arm.com# 9110259SAndrew.Bardsley@arm.com 9210259SAndrew.Bardsley@arm.comisa_parser = File('isa_parser.py') 9310259SAndrew.Bardsley@arm.com 9410259SAndrew.Bardsley@arm.com# The emitter patches up the sources & targets to include the 9510259SAndrew.Bardsley@arm.com# autogenerated files as targets and isa parser itself as a source. 9610259SAndrew.Bardsley@arm.comdef isa_desc_emitter(target, source, env): 9710259SAndrew.Bardsley@arm.com cpu_models = list(env['CPU_MODELS']) 9810259SAndrew.Bardsley@arm.com if env['USE_CHECKER']: 9910259SAndrew.Bardsley@arm.com cpu_models.append('CheckerCPU') 10010259SAndrew.Bardsley@arm.com 10110259SAndrew.Bardsley@arm.com # Several files are generated from the ISA description. 10210259SAndrew.Bardsley@arm.com # We always get the basic decoder and header file. 10310259SAndrew.Bardsley@arm.com target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ] 10410259SAndrew.Bardsley@arm.com # We also get an execute file for each selected CPU model. 10510259SAndrew.Bardsley@arm.com target += [CpuModel.dict[cpu].filename for cpu in cpu_models] 10610259SAndrew.Bardsley@arm.com 10710259SAndrew.Bardsley@arm.com # List the isa parser as a source. 10810259SAndrew.Bardsley@arm.com source += [ isa_parser ] 10910259SAndrew.Bardsley@arm.com # Add in the CPU models. 11010259SAndrew.Bardsley@arm.com source += [ Value(m) for m in cpu_models ] 11110259SAndrew.Bardsley@arm.com 11210259SAndrew.Bardsley@arm.com return target, source 11310259SAndrew.Bardsley@arm.com 11410259SAndrew.Bardsley@arm.comARCH_DIR = Dir('.') 11510259SAndrew.Bardsley@arm.com 11610259SAndrew.Bardsley@arm.com# import ply here because SCons screws with sys.path when performing actions. 11710259SAndrew.Bardsley@arm.comimport ply 11811567Smitch.hayenga@arm.com 11911567Smitch.hayenga@arm.comdef isa_desc_action_func(target, source, env): 12011567Smitch.hayenga@arm.com # Add the current directory to the system path so we can import files 12110259SAndrew.Bardsley@arm.com sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ] 12210259SAndrew.Bardsley@arm.com import isa_parser 12310259SAndrew.Bardsley@arm.com 12410259SAndrew.Bardsley@arm.com # Skip over the ISA description itself and the parser to the CPU models. 12510259SAndrew.Bardsley@arm.com models = [ s.get_contents() for s in source[2:] ] 12610259SAndrew.Bardsley@arm.com cpu_models = [CpuModel.dict[cpu] for cpu in models] 12710259SAndrew.Bardsley@arm.com parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models) 12810259SAndrew.Bardsley@arm.com parser.parse_isa_desc(source[0].abspath) 12910259SAndrew.Bardsley@arm.comisa_desc_action = MakeAction(isa_desc_action_func, Transform("ISA DESC", 1)) 13010259SAndrew.Bardsley@arm.com 13110259SAndrew.Bardsley@arm.com# Also include the CheckerCPU as one of the models if it is being 13210259SAndrew.Bardsley@arm.com# enabled via command line. 13310259SAndrew.Bardsley@arm.comisa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter) 13410259SAndrew.Bardsley@arm.com 13510259SAndrew.Bardsley@arm.comenv.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) 13610259SAndrew.Bardsley@arm.com 13710259SAndrew.Bardsley@arm.comDebugFlag('IntRegs') 13810259SAndrew.Bardsley@arm.comDebugFlag('FloatRegs') 13910259SAndrew.Bardsley@arm.comDebugFlag('MiscRegs') 14010259SAndrew.Bardsley@arm.comCompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ]) 14110259SAndrew.Bardsley@arm.com