SConscript revision 6143
14202Sbinkertn@umich.edu# -*- mode:python -*- 24202Sbinkertn@umich.edu 34202Sbinkertn@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 44202Sbinkertn@umich.edu# All rights reserved. 54202Sbinkertn@umich.edu# 64202Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 74202Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 84202Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 94202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 104202Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 114202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 124202Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 134202Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 144202Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 154202Sbinkertn@umich.edu# this software without specific prior written permission. 164202Sbinkertn@umich.edu# 174202Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 184202Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 194202Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 204202Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 214202Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 224202Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 234202Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 244202Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 254202Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 264202Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 274202Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 284202Sbinkertn@umich.edu# 294202Sbinkertn@umich.edu# Authors: Steve Reinhardt 304202Sbinkertn@umich.edu 314202Sbinkertn@umich.eduimport sys 324202Sbinkertn@umich.edu 334295Sbinkertn@umich.eduImport('*') 344295Sbinkertn@umich.edu 354295Sbinkertn@umich.edu################################################################# 364295Sbinkertn@umich.edu# 374295Sbinkertn@umich.edu# ISA "switch header" generation. 384295Sbinkertn@umich.edu# 394295Sbinkertn@umich.edu# Auto-generate arch headers that include the right ISA-specific 404295Sbinkertn@umich.edu# header based on the setting of THE_ISA preprocessor variable. 414295Sbinkertn@umich.edu# 424295Sbinkertn@umich.edu################################################################# 434295Sbinkertn@umich.edu 444295Sbinkertn@umich.edu# List of headers to generate 454295Sbinkertn@umich.eduisa_switch_hdrs = Split(''' 464295Sbinkertn@umich.edu arguments.hh 474295Sbinkertn@umich.edu faults.hh 484295Sbinkertn@umich.edu interrupts.hh 494295Sbinkertn@umich.edu isa_traits.hh 504295Sbinkertn@umich.edu kernel_stats.hh 514295Sbinkertn@umich.edu locked_mem.hh 524295Sbinkertn@umich.edu microcode_rom.hh 534202Sbinkertn@umich.edu mmaped_ipr.hh 544202Sbinkertn@umich.edu process.hh 554202Sbinkertn@umich.edu predecoder.hh 564202Sbinkertn@umich.edu regfile.hh 574202Sbinkertn@umich.edu remote_gdb.hh 584202Sbinkertn@umich.edu stacktrace.hh 594202Sbinkertn@umich.edu tlb.hh 604202Sbinkertn@umich.edu types.hh 614202Sbinkertn@umich.edu utility.hh 624202Sbinkertn@umich.edu vtophys.hh 634202Sbinkertn@umich.edu ''') 644202Sbinkertn@umich.edu 654202Sbinkertn@umich.edu# Set up this directory to support switching headers 664202Sbinkertn@umich.edumake_switching_dir('arch', isa_switch_hdrs, env) 674202Sbinkertn@umich.edu 684202Sbinkertn@umich.edu################################################################# 694202Sbinkertn@umich.edu# 704202Sbinkertn@umich.edu# Include architecture-specific files. 714202Sbinkertn@umich.edu# 724202Sbinkertn@umich.edu################################################################# 734202Sbinkertn@umich.edu 744202Sbinkertn@umich.edu# 754202Sbinkertn@umich.edu# Build a SCons scanner for ISA files 764202Sbinkertn@umich.edu# 774202Sbinkertn@umich.eduimport SCons.Scanner 784202Sbinkertn@umich.edu 794202Sbinkertn@umich.eduisa_scanner = SCons.Scanner.Classic("ISAScan", 804202Sbinkertn@umich.edu [".isa", ".ISA"], 814202Sbinkertn@umich.edu "SRCDIR", 824202Sbinkertn@umich.edu r'^\s*##include\s+"([\w/.-]*)"') 834202Sbinkertn@umich.edu 844202Sbinkertn@umich.eduenv.Append(SCANNERS = isa_scanner) 854202Sbinkertn@umich.edu 864202Sbinkertn@umich.edu# 874202Sbinkertn@umich.edu# Now create a Builder object that uses isa_parser.py to generate C++ 884202Sbinkertn@umich.edu# output from the ISA description (*.isa) files. 894202Sbinkertn@umich.edu# 904202Sbinkertn@umich.edu 914202Sbinkertn@umich.edu# Convert to File node to fix path 924202Sbinkertn@umich.eduisa_parser = File('isa_parser.py') 934202Sbinkertn@umich.educpu_models_file = File('../cpu/cpu_models.py') 944202Sbinkertn@umich.edu 954202Sbinkertn@umich.edu# This sucks in the defintions of the CpuModel objects. 964202Sbinkertn@umich.eduexecfile(cpu_models_file.srcnode().abspath) 974202Sbinkertn@umich.edu 984202Sbinkertn@umich.edu# Several files are generated from the ISA description. 994202Sbinkertn@umich.edu# We always get the basic decoder and header file. 1004382Sbinkertn@umich.eduisa_desc_gen_files = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ] 1014382Sbinkertn@umich.edu# We also get an execute file for each selected CPU model. 102isa_desc_gen_files += [CpuModel.dict[cpu].filename 103 for cpu in env['CPU_MODELS']] 104 105# Also include the CheckerCPU as one of the models if it is being 106# enabled via command line. 107if env['USE_CHECKER']: 108 isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename] 109 110# The emitter patches up the sources & targets to include the 111# autogenerated files as targets and isa parser itself as a source. 112def isa_desc_emitter(target, source, env): 113 return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source) 114 115# Pieces are in place, so create the builder. 116python = sys.executable # use same Python binary used to run scons 117 118# Also include the CheckerCPU as one of the models if it is being 119# enabled via command line. 120if env['USE_CHECKER']: 121 isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU', 122 emitter = isa_desc_emitter) 123else: 124 isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS', 125 emitter = isa_desc_emitter) 126 127env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) 128 129TraceFlag('IntRegs') 130TraceFlag('FloatRegs') 131TraceFlag('MiscRegs') 132CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ]) 133