SConscript revision 6143
1955SN/A# -*- mode:python -*- 2955SN/A 310841Sandreas.sandberg@arm.com# Copyright (c) 2006 The Regents of The University of Michigan 49812Sandreas.hansson@arm.com# All rights reserved. 59812Sandreas.hansson@arm.com# 69812Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 79812Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 89812Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 99812Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 109812Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 119812Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 129812Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 139812Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 149812Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 157816Ssteve.reinhardt@amd.com# this software without specific prior written permission. 165871Snate@binkert.org# 171762SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18955SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19955SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20955SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21955SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22955SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23955SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24955SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25955SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26955SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27955SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28955SN/A# 29955SN/A# Authors: Steve Reinhardt 30955SN/A 31955SN/Aimport sys 32955SN/A 33955SN/AImport('*') 34955SN/A 35955SN/A################################################################# 36955SN/A# 37955SN/A# ISA "switch header" generation. 38955SN/A# 39955SN/A# Auto-generate arch headers that include the right ISA-specific 40955SN/A# header based on the setting of THE_ISA preprocessor variable. 41955SN/A# 422665Ssaidi@eecs.umich.edu################################################################# 432665Ssaidi@eecs.umich.edu 445863Snate@binkert.org# List of headers to generate 45955SN/Aisa_switch_hdrs = Split(''' 46955SN/A arguments.hh 47955SN/A faults.hh 48955SN/A interrupts.hh 49955SN/A isa_traits.hh 508878Ssteve.reinhardt@amd.com kernel_stats.hh 512632Sstever@eecs.umich.edu locked_mem.hh 528878Ssteve.reinhardt@amd.com microcode_rom.hh 532632Sstever@eecs.umich.edu mmaped_ipr.hh 54955SN/A process.hh 558878Ssteve.reinhardt@amd.com predecoder.hh 562632Sstever@eecs.umich.edu regfile.hh 572761Sstever@eecs.umich.edu remote_gdb.hh 582632Sstever@eecs.umich.edu stacktrace.hh 592632Sstever@eecs.umich.edu tlb.hh 602632Sstever@eecs.umich.edu types.hh 612761Sstever@eecs.umich.edu utility.hh 622761Sstever@eecs.umich.edu vtophys.hh 632761Sstever@eecs.umich.edu ''') 648878Ssteve.reinhardt@amd.com 658878Ssteve.reinhardt@amd.com# Set up this directory to support switching headers 662761Sstever@eecs.umich.edumake_switching_dir('arch', isa_switch_hdrs, env) 672761Sstever@eecs.umich.edu 682761Sstever@eecs.umich.edu################################################################# 692761Sstever@eecs.umich.edu# 702761Sstever@eecs.umich.edu# Include architecture-specific files. 718878Ssteve.reinhardt@amd.com# 728878Ssteve.reinhardt@amd.com################################################################# 732632Sstever@eecs.umich.edu 742632Sstever@eecs.umich.edu# 758878Ssteve.reinhardt@amd.com# Build a SCons scanner for ISA files 768878Ssteve.reinhardt@amd.com# 772632Sstever@eecs.umich.eduimport SCons.Scanner 78955SN/A 79955SN/Aisa_scanner = SCons.Scanner.Classic("ISAScan", 80955SN/A [".isa", ".ISA"], 815863Snate@binkert.org "SRCDIR", 825863Snate@binkert.org r'^\s*##include\s+"([\w/.-]*)"') 835863Snate@binkert.org 845863Snate@binkert.orgenv.Append(SCANNERS = isa_scanner) 855863Snate@binkert.org 865863Snate@binkert.org# 875863Snate@binkert.org# Now create a Builder object that uses isa_parser.py to generate C++ 885863Snate@binkert.org# output from the ISA description (*.isa) files. 895863Snate@binkert.org# 905863Snate@binkert.org 915863Snate@binkert.org# Convert to File node to fix path 928878Ssteve.reinhardt@amd.comisa_parser = File('isa_parser.py') 935863Snate@binkert.orgcpu_models_file = File('../cpu/cpu_models.py') 945863Snate@binkert.org 955863Snate@binkert.org# This sucks in the defintions of the CpuModel objects. 969812Sandreas.hansson@arm.comexecfile(cpu_models_file.srcnode().abspath) 979812Sandreas.hansson@arm.com 985863Snate@binkert.org# Several files are generated from the ISA description. 999812Sandreas.hansson@arm.com# We always get the basic decoder and header file. 1005863Snate@binkert.orgisa_desc_gen_files = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ] 1015863Snate@binkert.org# We also get an execute file for each selected CPU model. 1025863Snate@binkert.orgisa_desc_gen_files += [CpuModel.dict[cpu].filename 1039812Sandreas.hansson@arm.com for cpu in env['CPU_MODELS']] 1049812Sandreas.hansson@arm.com 1055863Snate@binkert.org# Also include the CheckerCPU as one of the models if it is being 1065863Snate@binkert.org# enabled via command line. 1078878Ssteve.reinhardt@amd.comif env['USE_CHECKER']: 1085863Snate@binkert.org isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename] 1095863Snate@binkert.org 1105863Snate@binkert.org# The emitter patches up the sources & targets to include the 1116654Snate@binkert.org# autogenerated files as targets and isa parser itself as a source. 11210196SCurtis.Dunham@arm.comdef isa_desc_emitter(target, source, env): 113955SN/A return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source) 1145396Ssaidi@eecs.umich.edu 1155863Snate@binkert.org# Pieces are in place, so create the builder. 1165863Snate@binkert.orgpython = sys.executable # use same Python binary used to run scons 1174202Sbinkertn@umich.edu 1185863Snate@binkert.org# Also include the CheckerCPU as one of the models if it is being 1195863Snate@binkert.org# enabled via command line. 1205863Snate@binkert.orgif env['USE_CHECKER']: 1215863Snate@binkert.org isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU', 122955SN/A emitter = isa_desc_emitter) 1236654Snate@binkert.orgelse: 1245273Sstever@gmail.com isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS', 1255871Snate@binkert.org emitter = isa_desc_emitter) 1265273Sstever@gmail.com 1276655Snate@binkert.orgenv.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) 1288878Ssteve.reinhardt@amd.com 1296655Snate@binkert.orgTraceFlag('IntRegs') 1306655Snate@binkert.orgTraceFlag('FloatRegs') 1319219Spower.jg@gmail.comTraceFlag('MiscRegs') 1326655Snate@binkert.orgCompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ]) 1335871Snate@binkert.org