SConscript revision 3565
16691Stjones1@inf.ed.ac.uk# -*- mode:python -*- 26691Stjones1@inf.ed.ac.uk 36691Stjones1@inf.ed.ac.uk# Copyright (c) 2006 The Regents of The University of Michigan 46691Stjones1@inf.ed.ac.uk# All rights reserved. 56691Stjones1@inf.ed.ac.uk# 66691Stjones1@inf.ed.ac.uk# Redistribution and use in source and binary forms, with or without 76691Stjones1@inf.ed.ac.uk# modification, are permitted provided that the following conditions are 86691Stjones1@inf.ed.ac.uk# met: redistributions of source code must retain the above copyright 96691Stjones1@inf.ed.ac.uk# notice, this list of conditions and the following disclaimer; 106691Stjones1@inf.ed.ac.uk# redistributions in binary form must reproduce the above copyright 116691Stjones1@inf.ed.ac.uk# notice, this list of conditions and the following disclaimer in the 126691Stjones1@inf.ed.ac.uk# documentation and/or other materials provided with the distribution; 136691Stjones1@inf.ed.ac.uk# neither the name of the copyright holders nor the names of its 146691Stjones1@inf.ed.ac.uk# contributors may be used to endorse or promote products derived from 156691Stjones1@inf.ed.ac.uk# this software without specific prior written permission. 166691Stjones1@inf.ed.ac.uk# 176691Stjones1@inf.ed.ac.uk# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186691Stjones1@inf.ed.ac.uk# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196691Stjones1@inf.ed.ac.uk# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206691Stjones1@inf.ed.ac.uk# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216691Stjones1@inf.ed.ac.uk# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226691Stjones1@inf.ed.ac.uk# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236691Stjones1@inf.ed.ac.uk# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246691Stjones1@inf.ed.ac.uk# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256691Stjones1@inf.ed.ac.uk# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266691Stjones1@inf.ed.ac.uk# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276691Stjones1@inf.ed.ac.uk# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286691Stjones1@inf.ed.ac.uk# 296691Stjones1@inf.ed.ac.uk# Authors: Steve Reinhardt 306691Stjones1@inf.ed.ac.uk 316691Stjones1@inf.ed.ac.ukimport os.path, sys 326691Stjones1@inf.ed.ac.uk 336691Stjones1@inf.ed.ac.uk# Import build environment variable from SConstruct. 346691Stjones1@inf.ed.ac.ukImport('env') 356691Stjones1@inf.ed.ac.uk 366691Stjones1@inf.ed.ac.uk# Right now there are no source files immediately in this directory 376691Stjones1@inf.ed.ac.uksources = [] 386691Stjones1@inf.ed.ac.uk 396691Stjones1@inf.ed.ac.uk################################################################# 406691Stjones1@inf.ed.ac.uk# 416691Stjones1@inf.ed.ac.uk# ISA "switch header" generation. 426691Stjones1@inf.ed.ac.uk# 436691Stjones1@inf.ed.ac.uk# Auto-generate arch headers that include the right ISA-specific 446691Stjones1@inf.ed.ac.uk# header based on the setting of THE_ISA preprocessor variable. 456691Stjones1@inf.ed.ac.uk# 466691Stjones1@inf.ed.ac.uk################################################################# 476691Stjones1@inf.ed.ac.uk 486691Stjones1@inf.ed.ac.uk# List of headers to generate 496691Stjones1@inf.ed.ac.ukisa_switch_hdrs = Split(''' 506691Stjones1@inf.ed.ac.uk arguments.hh 516691Stjones1@inf.ed.ac.uk faults.hh 526691Stjones1@inf.ed.ac.uk interrupts.hh 536691Stjones1@inf.ed.ac.uk isa_traits.hh 546691Stjones1@inf.ed.ac.uk kernel_stats.hh 556691Stjones1@inf.ed.ac.uk locked_mem.hh 566691Stjones1@inf.ed.ac.uk process.hh 576691Stjones1@inf.ed.ac.uk regfile.hh 586691Stjones1@inf.ed.ac.uk remote_gdb.hh 596691Stjones1@inf.ed.ac.uk stacktrace.hh 606691Stjones1@inf.ed.ac.uk syscallreturn.hh 616691Stjones1@inf.ed.ac.uk tlb.hh 62 types.hh 63 utility.hh 64 vtophys.hh 65 ''') 66 67# Set up this directory to support switching headers 68env.make_switching_dir('arch', isa_switch_hdrs, env) 69 70################################################################# 71# 72# Include architecture-specific files. 73# 74################################################################# 75 76# 77# Build a SCons scanner for ISA files 78# 79import SCons.Scanner 80 81isa_scanner = SCons.Scanner.Classic("ISAScan", 82 [".isa", ".ISA"], 83 "SRCDIR", 84 r'^\s*##include\s+"([\w/.-]*)"') 85 86env.Append(SCANNERS = isa_scanner) 87 88# 89# Now create a Builder object that uses isa_parser.py to generate C++ 90# output from the ISA description (*.isa) files. 91# 92 93# Convert to File node to fix path 94isa_parser = File('isa_parser.py') 95cpu_models_file = File('../cpu/cpu_models.py') 96 97# This sucks in the defintions of the CpuModel objects. 98execfile(cpu_models_file.srcnode().abspath) 99 100# Several files are generated from the ISA description. 101# We always get the basic decoder and header file. 102isa_desc_gen_files = Split('decoder.cc decoder.hh') 103# We also get an execute file for each selected CPU model. 104isa_desc_gen_files += [CpuModel.dict[cpu].filename 105 for cpu in env['CPU_MODELS']] 106 107# Also include the CheckerCPU as one of the models if it is being 108# enabled via command line. 109if env['USE_CHECKER']: 110 isa_desc_gen_files += [CpuModel.dict['CheckerCPU'].filename] 111 112# The emitter patches up the sources & targets to include the 113# autogenerated files as targets and isa parser itself as a source. 114def isa_desc_emitter(target, source, env): 115 return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source) 116 117# Pieces are in place, so create the builder. 118python = sys.executable # use same Python binary used to run scons 119 120# Also include the CheckerCPU as one of the models if it is being 121# enabled via command line. 122if env['USE_CHECKER']: 123 isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU', 124 emitter = isa_desc_emitter) 125else: 126 isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS', 127 emitter = isa_desc_emitter) 128 129env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder }) 130 131# 132# Now include other ISA-specific sources from the ISA subdirectories. 133# 134 135isa = env['TARGET_ISA'] # someday this may be a list of ISAs 136 137# Let the target architecture define what additional sources it needs 138sources += SConscript(os.path.join(isa, 'SConscript'), exports = 'env') 139 140Return('sources') 141