1/* 2 * Copyright (c) 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Nathan Binkert 41 * Ali Saidi 42 * Andreas Sandberg 43 */ 44 45#ifndef __GEM5_ASM_GENERIC_M5OPS_H__ 46#define __GEM5_ASM_GENERIC_M5OPS_H__ 47 48#include <gem5/asm/generic/m5op_flags.h> 49 50#define M5OP_ARM 0x00 51#define M5OP_QUIESCE 0x01 52#define M5OP_QUIESCE_NS 0x02 53#define M5OP_QUIESCE_CYCLE 0x03 54#define M5OP_QUIESCE_TIME 0x04 55#define M5OP_RPNS 0x07 56#define M5OP_WAKE_CPU 0x09 57#define M5OP_DEPRECATED1 0x10 // obsolete ivlb 58#define M5OP_DEPRECATED2 0x11 // obsolete ivle 59#define M5OP_DEPRECATED3 0x20 // deprecated exit function 60#define M5OP_EXIT 0x21 61#define M5OP_FAIL 0x22 62#define M5OP_INIT_PARAM 0x30 63#define M5OP_LOAD_SYMBOL 0x31 64#define M5OP_RESET_STATS 0x40 65#define M5OP_DUMP_STATS 0x41 66#define M5OP_DUMP_RESET_STATS 0x42 67#define M5OP_CHECKPOINT 0x43 68#define M5OP_WRITE_FILE 0x4F 69#define M5OP_READ_FILE 0x50 70#define M5OP_DEBUG_BREAK 0x51 71#define M5OP_SWITCH_CPU 0x52 72#define M5OP_ADD_SYMBOL 0x53 73#define M5OP_PANIC 0x54 74 75#define M5OP_RESERVED2 0x56 // Reserved for user 76#define M5OP_RESERVED3 0x57 // Reserved for user 77#define M5OP_RESERVED4 0x58 // Reserved for user 78#define M5OP_RESERVED5 0x59 // Reserved for user 79 80#define M5OP_WORK_BEGIN 0x5a 81#define M5OP_WORK_END 0x5b 82 83#define M5OP_SE_SYSCALL 0x60 84#define M5OP_SE_PAGE_FAULT 0x61 85#define M5OP_DIST_TOGGLE_SYNC 0x62 86 87// These operations are for critical path annotation 88#define M5OP_ANNOTATE 0x55 89#define M5OP_AN_BSM 0x1 90#define M5OP_AN_ESM 0x2 91#define M5OP_AN_BEGIN 0x3 92#define M5OP_AN_END 0x4 93#define M5OP_AN_Q 0x6 94#define M5OP_AN_DQ 0x7 95#define M5OP_AN_WF 0x8 96#define M5OP_AN_WE 0x9 97#define M5OP_AN_RQ 0xA 98#define M5OP_AN_WS 0xB 99#define M5OP_AN_SQ 0xC 100#define M5OP_AN_AQ 0xD 101#define M5OP_AN_PQ 0xE 102#define M5OP_AN_L 0xF 103#define M5OP_AN_IDENTIFY 0x10 104#define M5OP_AN_GETID 0x11 105 106 107#define M5OP_FOREACH \ 108 M5OP(m5_arm, M5OP_ARM, 0); \ 109 M5OP(m5_quiesce, M5OP_QUIESCE, 0); \ 110 M5OP(m5_quiesce_ns, M5OP_QUIESCE_NS, 0); \ 111 M5OP(m5_quiesce_cycle, M5OP_QUIESCE_CYCLE, 0); \ 112 M5OP(m5_quiesce_time, M5OP_QUIESCE_TIME, 0); \ 113 M5OP(m5_rpns, M5OP_RPNS, 0); \ 114 M5OP(m5_wake_cpu, M5OP_WAKE_CPU, 0); \ 115 M5OP(m5_exit, M5OP_EXIT, 0); \ 116 M5OP(m5_fail, M5OP_FAIL, 0); \ 117 M5OP(m5_init_param, M5OP_INIT_PARAM, 0); \ 118 M5OP(m5_load_symbol, M5OP_LOAD_SYMBOL, 0); \ 119 M5OP(m5_reset_stats, M5OP_RESET_STATS, 0); \ 120 M5OP(m5_dump_stats, M5OP_DUMP_STATS, 0); \ 121 M5OP(m5_dump_reset_stats, M5OP_DUMP_RESET_STATS, 0); \ 122 M5OP(m5_checkpoint, M5OP_CHECKPOINT, 0); \ 123 M5OP(m5_read_file, M5OP_READ_FILE, 0); \ 124 M5OP(m5_write_file, M5OP_WRITE_FILE, 0); \ 125 M5OP(m5_debug_break, M5OP_DEBUG_BREAK, 0); \ 126 M5OP(m5_switch_cpu, M5OP_SWITCH_CPU, 0); \ 127 M5OP(m5_add_symbol, M5OP_ADD_SYMBOL, 0); \ 128 M5OP(m5_panic, M5OP_PANIC, 0); \ 129 M5OP(m5_work_begin, M5OP_WORK_BEGIN, 0); \ 130 M5OP(m5_work_end, M5OP_WORK_END, 0); \ 131 M5OP(m5_dist_toggle_sync, M5OP_DIST_TOGGLE_SYNC, 0); 132 133#define M5OP_FOREACH_ANNOTATION \ 134 M5_ANNOTATION(m5a_bsm, M5OP_AN_BSM); \ 135 M5_ANNOTATION(m5a_esm, M5OP_AN_ESM); \ 136 M5_ANNOTATION(m5a_begin, M5OP_AN_BEGIN); \ 137 M5_ANNOTATION(m5a_end, M5OP_AN_END); \ 138 M5_ANNOTATION(m5a_q, M5OP_AN_Q); \ 139 M5_ANNOTATION(m5a_dq, M5OP_AN_DQ); \ 140 M5_ANNOTATION(m5a_wf, M5OP_AN_WF); \ 141 M5_ANNOTATION(m5a_we, M5OP_AN_WE); \ 142 M5_ANNOTATION(m5a_rq, M5OP_AN_RQ); \ 143 M5_ANNOTATION(m5a_ws, M5OP_AN_WS); \ 144 M5_ANNOTATION(m5a_sq, M5OP_AN_SQ); \ 145 M5_ANNOTATION(m5a_aq, M5OP_AN_AQ); \ 146 M5_ANNOTATION(m5a_pq, M5OP_AN_PQ); \ 147 M5_ANNOTATION(m5a_l, M5OP_AN_L); \ 148 M5_ANNOTATION(m5a_identify, M5OP_AN_IDENTIFY); \ 149 M5_ANNOTATION(m5a_getid, M5OP_AN_GETID); 150 151#endif // __GEM5_ASM_GENERIC_M5OPS_H__ 152