1/* 2 * Copyright (c) 2014-2015 ARM Limited 3 * All rights reserved 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18#ifndef _MIDGARD_REGMAP_H_ 19#define _MIDGARD_REGMAP_H_ 20 21/* 22 * Begin Register Offsets 23 */ 24 25#define GPU_CONTROL_BASE 0x0000 26#define GPU_CONTROL_REG(r) (GPU_CONTROL_BASE + (r)) 27#define GPU_ID 0x000 /* (RO) GPU and revision identifier */ 28#define L2_FEATURES 0x004 /* (RO) Level 2 cache features */ 29#define L3_FEATURES 0x008 /* (RO) Level 3 cache features */ 30#define TILER_FEATURES 0x00C /* (RO) Tiler Features */ 31#define MEM_FEATURES 0x010 /* (RO) Memory system features */ 32#define MMU_FEATURES 0x014 /* (RO) MMU features */ 33#define AS_PRESENT 0x018 /* (RO) Address space slots present */ 34#define JS_PRESENT 0x01C /* (RO) Job slots present */ 35#define GPU_IRQ_RAWSTAT 0x020 /* (RW) */ 36#define GPU_IRQ_CLEAR 0x024 /* (WO) */ 37#define GPU_IRQ_MASK 0x028 /* (RW) */ 38#define GPU_IRQ_STATUS 0x02C /* (RO) */ 39 40/* IRQ flags */ 41#define GPU_FAULT (1 << 0) /* A GPU Fault has occurred */ 42#define MULTIPLE_GPU_FAULTS (1 << 7) /* More than one GPU Fault occurred. */ 43#define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. Intended to use with SOFT_RESET 44 commands which may take time. */ 45#define POWER_CHANGED_SINGLE (1 << 9) /* Set when a single core has finished powering up or down. */ 46#define POWER_CHANGED_ALL (1 << 10) /* Set when all cores have finished powering up or down 47 and the power manager is idle. */ 48 49#define PRFCNT_SAMPLE_COMPLETED (1 << 16) /* Set when a performance count sample has completed. */ 50#define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */ 51 52#define GPU_IRQ_REG_ALL (GPU_FAULT | MULTIPLE_GPU_FAULTS | RESET_COMPLETED \ 53 | POWER_CHANGED_ALL | PRFCNT_SAMPLE_COMPLETED) 54 55#define GPU_COMMAND 0x030 /* (WO) */ 56#define GPU_STATUS 0x034 /* (RO) */ 57 58#define GROUPS_L2_COHERENT (1 << 0) /* Cores groups are l2 coherent */ 59#define GROUPS_L3_COHERENT (1 << 1) /* Cores groups are l3 coherent */ 60 61#define GPU_FAULTSTATUS 0x03C /* (RO) GPU exception type and fault status */ 62#define GPU_FAULTADDRESS_LO 0x040 /* (RO) GPU exception fault address, low word */ 63#define GPU_FAULTADDRESS_HI 0x044 /* (RO) GPU exception fault address, high word */ 64 65#define PWR_KEY 0x050 /* (WO) Power manager key register */ 66#define PWR_OVERRIDE0 0x054 /* (RW) Power manager override settings */ 67#define PWR_OVERRIDE1 0x058 /* (RW) Power manager override settings */ 68 69#define PRFCNT_BASE_LO 0x060 /* (RW) Performance counter memory region base address, low word */ 70#define PRFCNT_BASE_HI 0x064 /* (RW) Performance counter memory region base address, high word */ 71#define PRFCNT_CONFIG 0x068 /* (RW) Performance counter configuration */ 72#define PRFCNT_JM_EN 0x06C /* (RW) Performance counter enable flags for Job Manager */ 73#define PRFCNT_SHADER_EN 0x070 /* (RW) Performance counter enable flags for shader cores */ 74#define PRFCNT_TILER_EN 0x074 /* (RW) Performance counter enable flags for tiler */ 75#define PRFCNT_L3_CACHE_EN 0x078 /* (RW) Performance counter enable flags for L3 cache */ 76#define PRFCNT_MMU_L2_EN 0x07C /* (RW) Performance counter enable flags for MMU/L2 cache */ 77 78#define CYCLE_COUNT_LO 0x090 /* (RO) Cycle counter, low word */ 79#define CYCLE_COUNT_HI 0x094 /* (RO) Cycle counter, high word */ 80#define TIMESTAMP_LO 0x098 /* (RO) Global time stamp counter, low word */ 81#define TIMESTAMP_HI 0x09C /* (RO) Global time stamp counter, high word */ 82 83#define THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */ 84#define THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */ 85#define THREAD_MAX_BARRIER_SIZE 0x0A8 /* (RO) Maximum threads waiting at a barrier */ 86#define THREAD_FEATURES 0x0AC /* (RO) Thread features */ 87 88#define TEXTURE_FEATURES_0 0x0B0 /* (RO) Support flags for indexed texture formats 0..31 */ 89#define TEXTURE_FEATURES_1 0x0B4 /* (RO) Support flags for indexed texture formats 32..63 */ 90#define TEXTURE_FEATURES_2 0x0B8 /* (RO) Support flags for indexed texture formats 64..95 */ 91 92#define TEXTURE_FEATURES_REG(n) GPU_CONTROL_REG(TEXTURE_FEATURES_0 + ((n) << 2)) 93 94#define JS0_FEATURES 0x0C0 /* (RO) Features of job slot 0 */ 95#define JS1_FEATURES 0x0C4 /* (RO) Features of job slot 1 */ 96#define JS2_FEATURES 0x0C8 /* (RO) Features of job slot 2 */ 97#define JS3_FEATURES 0x0CC /* (RO) Features of job slot 3 */ 98#define JS4_FEATURES 0x0D0 /* (RO) Features of job slot 4 */ 99#define JS5_FEATURES 0x0D4 /* (RO) Features of job slot 5 */ 100#define JS6_FEATURES 0x0D8 /* (RO) Features of job slot 6 */ 101#define JS7_FEATURES 0x0DC /* (RO) Features of job slot 7 */ 102#define JS8_FEATURES 0x0E0 /* (RO) Features of job slot 8 */ 103#define JS9_FEATURES 0x0E4 /* (RO) Features of job slot 9 */ 104#define JS10_FEATURES 0x0E8 /* (RO) Features of job slot 10 */ 105#define JS11_FEATURES 0x0EC /* (RO) Features of job slot 11 */ 106#define JS12_FEATURES 0x0F0 /* (RO) Features of job slot 12 */ 107#define JS13_FEATURES 0x0F4 /* (RO) Features of job slot 13 */ 108#define JS14_FEATURES 0x0F8 /* (RO) Features of job slot 14 */ 109#define JS15_FEATURES 0x0FC /* (RO) Features of job slot 15 */ 110 111#define JS_FEATURES_REG(n) GPU_CONTROL_REG(JS0_FEATURES + ((n) << 2)) 112 113#define SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */ 114#define SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */ 115 116#define TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */ 117#define TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */ 118 119#define L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */ 120#define L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */ 121 122#define L3_PRESENT_LO 0x130 /* (RO) Level 3 cache present bitmap, low word */ 123#define L3_PRESENT_HI 0x134 /* (RO) Level 3 cache present bitmap, high word */ 124 125#define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */ 126#define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */ 127 128#define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */ 129#define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */ 130 131#define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */ 132#define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */ 133 134#define L3_READY_LO 0x170 /* (RO) Level 3 cache ready bitmap, low word */ 135#define L3_READY_HI 0x174 /* (RO) Level 3 cache ready bitmap, high word */ 136 137#define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */ 138#define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */ 139 140#define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */ 141#define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */ 142 143#define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */ 144#define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */ 145 146#define L3_PWRON_LO 0x1B0 /* (WO) Level 3 cache power on bitmap, low word */ 147#define L3_PWRON_HI 0x1B4 /* (WO) Level 3 cache power on bitmap, high word */ 148 149#define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */ 150#define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */ 151 152#define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */ 153#define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */ 154 155#define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */ 156#define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */ 157 158#define L3_PWROFF_LO 0x1F0 /* (WO) Level 3 cache power off bitmap, low word */ 159#define L3_PWROFF_HI 0x1F4 /* (WO) Level 3 cache power off bitmap, high word */ 160 161#define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */ 162#define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */ 163 164#define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */ 165#define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */ 166 167#define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */ 168#define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */ 169 170#define L3_PWRTRANS_LO 0x230 /* (RO) Level 3 cache power transition bitmap, low word */ 171#define L3_PWRTRANS_HI 0x234 /* (RO) Level 3 cache power transition bitmap, high word */ 172 173#define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */ 174#define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */ 175 176#define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */ 177#define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */ 178 179#define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */ 180#define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */ 181 182#define L3_PWRACTIVE_LO 0x270 /* (RO) Level 3 cache active bitmap, low word */ 183#define L3_PWRACTIVE_HI 0x274 /* (RO) Level 3 cache active bitmap, high word */ 184 185#define SHADER_CONFIG 0xF04 /* (RW) Shader core configuration settings (Mali-T60x additional register) */ 186#define L2_MMU_CONFIG 0xF0C /* (RW) Configuration of the L2 cache and MMU (Mali-T60x additional register) */ 187 188#define JOB_CONTROL_BASE 0x1000 189 190#define JOB_CONTROL_REG(r) (JOB_CONTROL_BASE + (r)) 191 192#define JOB_IRQ_RAWSTAT 0x000 /* Raw interrupt status register */ 193#define JOB_IRQ_CLEAR 0x004 /* Interrupt clear register */ 194#define JOB_IRQ_MASK 0x008 /* Interrupt mask register */ 195#define JOB_IRQ_STATUS 0x00C /* Interrupt status register */ 196#define JOB_IRQ_JS_STATE 0x010 /* status==active and _next == busy snapshot from last JOB_IRQ_CLEAR */ 197#define JOB_IRQ_THROTTLE 0x014 /* cycles to delay delivering an interrupt externally. The JOB_IRQ_STATUS is NOT affected by this, just the delivery of the interrupt. */ 198 199#define JOB_SLOT0 0x800 /* Configuration registers for job slot 0 */ 200#define JOB_SLOT1 0x880 /* Configuration registers for job slot 1 */ 201#define JOB_SLOT2 0x900 /* Configuration registers for job slot 2 */ 202#define JOB_SLOT3 0x980 /* Configuration registers for job slot 3 */ 203#define JOB_SLOT4 0xA00 /* Configuration registers for job slot 4 */ 204#define JOB_SLOT5 0xA80 /* Configuration registers for job slot 5 */ 205#define JOB_SLOT6 0xB00 /* Configuration registers for job slot 6 */ 206#define JOB_SLOT7 0xB80 /* Configuration registers for job slot 7 */ 207#define JOB_SLOT8 0xC00 /* Configuration registers for job slot 8 */ 208#define JOB_SLOT9 0xC80 /* Configuration registers for job slot 9 */ 209#define JOB_SLOT10 0xD00 /* Configuration registers for job slot 10 */ 210#define JOB_SLOT11 0xD80 /* Configuration registers for job slot 11 */ 211#define JOB_SLOT12 0xE00 /* Configuration registers for job slot 12 */ 212#define JOB_SLOT13 0xE80 /* Configuration registers for job slot 13 */ 213#define JOB_SLOT14 0xF00 /* Configuration registers for job slot 14 */ 214#define JOB_SLOT15 0xF80 /* Configuration registers for job slot 15 */ 215 216#define JOB_SLOT_REG(n, r) (JOB_CONTROL_REG(JOB_SLOT0 + ((n) << 7)) + (r)) 217 218#define JSn_HEAD_LO 0x00 /* (RO) Job queue head pointer for job slot n, low word */ 219#define JSn_HEAD_HI 0x04 /* (RO) Job queue head pointer for job slot n, high word */ 220#define JSn_TAIL_LO 0x08 /* (RO) Job queue tail pointer for job slot n, low word */ 221#define JSn_TAIL_HI 0x0C /* (RO) Job queue tail pointer for job slot n, high word */ 222#define JSn_AFFINITY_LO 0x10 /* (RO) Core affinity mask for job slot n, low word */ 223#define JSn_AFFINITY_HI 0x14 /* (RO) Core affinity mask for job slot n, high word */ 224#define JSn_CONFIG 0x18 /* (RO) Configuration settings for job slot n */ 225 226#define JSn_COMMAND 0x20 /* (WO) Command register for job slot n */ 227#define JSn_STATUS 0x24 /* (RO) Status register for job slot n */ 228 229#define JSn_HEAD_NEXT_LO 0x40 /* (RW) Next job queue head pointer for job slot n, low word */ 230#define JSn_HEAD_NEXT_HI 0x44 /* (RW) Next job queue head pointer for job slot n, high word */ 231 232#define JSn_AFFINITY_NEXT_LO 0x50 /* (RW) Next core affinity mask for job slot n, low word */ 233#define JSn_AFFINITY_NEXT_HI 0x54 /* (RW) Next core affinity mask for job slot n, high word */ 234#define JSn_CONFIG_NEXT 0x58 /* (RW) Next configuration settings for job slot n */ 235 236#define JSn_COMMAND_NEXT 0x60 /* (RW) Next command register for job slot n */ 237 238#define MEMORY_MANAGEMENT_BASE 0x2000 239#define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r)) 240 241#define MMU_IRQ_RAWSTAT 0x000 /* (RW) Raw interrupt status register */ 242#define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */ 243#define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */ 244#define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */ 245 246#define MMU_AS0 0x400 /* Configuration registers for address space 0 */ 247#define MMU_AS1 0x440 /* Configuration registers for address space 1 */ 248#define MMU_AS2 0x480 /* Configuration registers for address space 2 */ 249#define MMU_AS3 0x4C0 /* Configuration registers for address space 3 */ 250#define MMU_AS4 0x500 /* Configuration registers for address space 4 */ 251#define MMU_AS5 0x540 /* Configuration registers for address space 5 */ 252#define MMU_AS6 0x580 /* Configuration registers for address space 6 */ 253#define MMU_AS7 0x5C0 /* Configuration registers for address space 7 */ 254#define MMU_AS8 0x600 /* Configuration registers for address space 8 */ 255#define MMU_AS9 0x640 /* Configuration registers for address space 9 */ 256#define MMU_AS10 0x680 /* Configuration registers for address space 10 */ 257#define MMU_AS11 0x6C0 /* Configuration registers for address space 11 */ 258#define MMU_AS12 0x700 /* Configuration registers for address space 12 */ 259#define MMU_AS13 0x740 /* Configuration registers for address space 13 */ 260#define MMU_AS14 0x780 /* Configuration registers for address space 14 */ 261#define MMU_AS15 0x7C0 /* Configuration registers for address space 15 */ 262 263#define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r)) 264 265#define ASn_TRANSTAB_LO 0x00 /* (RW) Translation Table Base Address for address space n, low word */ 266#define ASn_TRANSTAB_HI 0x04 /* (RW) Translation Table Base Address for address space n, high word */ 267#define ASn_MEMATTR_LO 0x08 /* (RW) Memory attributes for address space n, low word. */ 268#define ASn_MEMATTR_HI 0x0C /* (RW) Memory attributes for address space n, high word. */ 269#define ASn_LOCKADDR_LO 0x10 /* (RW) Lock region address for address space n, low word */ 270#define ASn_LOCKADDR_HI 0x14 /* (RW) Lock region address for address space n, high word */ 271#define ASn_COMMAND 0x18 /* (WO) MMU command register for address space n */ 272#define ASn_FAULTSTATUS 0x1C /* (RO) MMU fault status register for address space n */ 273#define ASn_FAULTADDRESS_LO 0x20 /* (RO) Fault Address for address space n, low word */ 274#define ASn_FAULTADDRESS_HI 0x24 /* (RO) Fault Address for address space n, high word */ 275#define ASn_STATUS 0x28 /* (RO) Status flags for address space n */ 276 277/* End Register Offsets */ 278 279/* 280 * MMU_IRQ_RAWSTAT register values. Values are valid also for 281 MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers. 282 */ 283 284#define MMU_REGS_PAGE_FAULT_FLAGS 16 285 286/* Macros return bit number to retrvie page fault or bus eror flag from MMU registers */ 287#define MMU_REGS_PAGE_FAULT_FLAG(n) (n) 288#define MMU_REGS_BUS_ERROR_FLAG(n) (n + MMU_REGS_PAGE_FAULT_FLAGS) 289 290/* 291 * Begin MMU TRANSTAB register values 292 */ 293#define ASn_TRANSTAB_ADDR_SPACE_MASK 0xfffff000 294#define ASn_TRANSTAB_ADRMODE_UNMAPPED (0u << 0) 295#define ASn_TRANSTAB_ADRMODE_IDENTITY (1u << 1) 296#define ASn_TRANSTAB_ADRMODE_TABLE (3u << 0) 297#define ASn_TRANSTAB_READ_INNER (1u << 2) 298#define ASn_TRANSTAB_SHARE_OUTER (1u << 4) 299 300#define MMU_TRANSTAB_ADRMODE_MASK 0x00000003 301 302/* 303 * Begin MMU STATUS register values 304 */ 305#define ASn_STATUS_FLUSH_ACTIVE 0x01 306 307#define ASn_FAULTSTATUS_ACCESS_TYPE_MASK (0x3<<8) 308#define ASn_FAULTSTATUS_ACCESS_TYPE_EX (0x1<<8) 309#define ASn_FAULTSTATUS_ACCESS_TYPE_READ (0x2<<8) 310#define ASn_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3<<8) 311 312/* 313 * Begin Command Values 314 */ 315 316/* JSn_COMMAND register commands */ 317#define JSn_COMMAND_NOP 0x00 /* NOP Operation. Writing this value is ignored */ 318#define JSn_COMMAND_START 0x01 /* Start processing a job chain. Writing this value is ignored */ 319#define JSn_COMMAND_SOFT_STOP 0x02 /* Gently stop processing a job chain */ 320#define JSn_COMMAND_HARD_STOP 0x03 /* Rudely stop processing a job chain */ 321#define JSn_COMMAND_SOFT_STOP_0 0x04 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */ 322#define JSn_COMMAND_HARD_STOP_0 0x05 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */ 323#define JSn_COMMAND_SOFT_STOP_1 0x06 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */ 324#define JSn_COMMAND_HARD_STOP_1 0x07 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */ 325 326/* ASn_COMMAND register commands */ 327#define ASn_COMMAND_NOP 0x00 /* NOP Operation */ 328#define ASn_COMMAND_UPDATE 0x01 /* Broadcasts the values in ASn_TRANSTAB and ASn_MEMATTR to all MMUs */ 329#define ASn_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */ 330#define ASn_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */ 331#define ASn_COMMAND_FLUSH 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs 332 (deprecated - only for use with T60x) */ 333#define ASn_COMMAND_FLUSH_PT 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs */ 334#define ASn_COMMAND_FLUSH_MEM 0x05 /* Wait for memory accesses to complete, flush all the L1s cache then 335 flush all L2 caches then issue a flush region command to all MMUs */ 336 337/* Possible values of JSn_CONFIG and JSn_CONFIG_NEXT registers */ 338#define JSn_CONFIG_START_FLUSH_NO_ACTION (0u << 0) 339#define JSn_CONFIG_START_FLUSH_CLEAN (1u << 8) 340#define JSn_CONFIG_START_FLUSH_CLEAN_INVALIDATE (3u << 8) 341#define JSn_CONFIG_START_MMU (1u << 10) 342#define JSn_CONFIG_JOB_CHAIN_FLAG (1u << 11) 343#define JSn_CONFIG_END_FLUSH_NO_ACTION JSn_CONFIG_START_FLUSH_NO_ACTION 344#define JSn_CONFIG_END_FLUSH_CLEAN (1u << 12) 345#define JSn_CONFIG_END_FLUSH_CLEAN_INVALIDATE (3u << 12) 346#define JSn_CONFIG_THREAD_PRI(n) ((n) << 16) 347 348/* JSn_STATUS register values */ 349 350/* NOTE: Please keep this values in sync with enum base_jd_event_code in mali_base_kernel.h. 351 * The values are separated to avoid dependency of userspace and kernel code. 352 */ 353 354/* Group of values representing the job status insead a particular fault */ 355#define JSn_STATUS_NO_EXCEPTION_BASE 0x00 356#define JSn_STATUS_INTERRUPTED (JSn_STATUS_NO_EXCEPTION_BASE + 0x02) /* 0x02 means INTERRUPTED */ 357#define JSn_STATUS_STOPPED (JSn_STATUS_NO_EXCEPTION_BASE + 0x03) /* 0x03 means STOPPED */ 358#define JSn_STATUS_TERMINATED (JSn_STATUS_NO_EXCEPTION_BASE + 0x04) /* 0x04 means TERMINATED */ 359 360/* General fault values */ 361#define JSn_STATUS_FAULT_BASE 0x40 362#define JSn_STATUS_CONFIG_FAULT (JSn_STATUS_FAULT_BASE) /* 0x40 means CONFIG FAULT */ 363#define JSn_STATUS_POWER_FAULT (JSn_STATUS_FAULT_BASE + 0x01) /* 0x41 means POWER FAULT */ 364#define JSn_STATUS_READ_FAULT (JSn_STATUS_FAULT_BASE + 0x02) /* 0x42 means READ FAULT */ 365#define JSn_STATUS_WRITE_FAULT (JSn_STATUS_FAULT_BASE + 0x03) /* 0x43 means WRITE FAULT */ 366#define JSn_STATUS_AFFINITY_FAULT (JSn_STATUS_FAULT_BASE + 0x04) /* 0x44 means AFFINITY FAULT */ 367#define JSn_STATUS_BUS_FAULT (JSn_STATUS_FAULT_BASE + 0x08) /* 0x48 means BUS FAULT */ 368 369/* Instruction or data faults */ 370#define JSn_STATUS_INSTRUCTION_FAULT_BASE 0x50 371#define JSn_STATUS_INSTR_INVALID_PC (JSn_STATUS_INSTRUCTION_FAULT_BASE) /* 0x50 means INSTR INVALID PC */ 372#define JSn_STATUS_INSTR_INVALID_ENC (JSn_STATUS_INSTRUCTION_FAULT_BASE + 0x01) /* 0x51 means INSTR INVALID ENC */ 373#define JSn_STATUS_INSTR_TYPE_MISMATCH (JSn_STATUS_INSTRUCTION_FAULT_BASE + 0x02) /* 0x52 means INSTR TYPE MISMATCH */ 374#define JSn_STATUS_INSTR_OPERAND_FAULT (JSn_STATUS_INSTRUCTION_FAULT_BASE + 0x03) /* 0x53 means INSTR OPERAND FAULT */ 375#define JSn_STATUS_INSTR_TLS_FAULT (JSn_STATUS_INSTRUCTION_FAULT_BASE + 0x04) /* 0x54 means INSTR TLS FAULT */ 376#define JSn_STATUS_INSTR_BARRIER_FAULT (JSn_STATUS_INSTRUCTION_FAULT_BASE + 0x05) /* 0x55 means INSTR BARRIER FAULT */ 377#define JSn_STATUS_INSTR_ALIGN_FAULT (JSn_STATUS_INSTRUCTION_FAULT_BASE + 0x06) /* 0x56 means INSTR ALIGN FAULT */ 378/* NOTE: No fault with 0x57 code defined in spec. */ 379#define JSn_STATUS_DATA_INVALID_FAULT (JSn_STATUS_INSTRUCTION_FAULT_BASE + 0x08) /* 0x58 means DATA INVALID FAULT */ 380#define JSn_STATUS_TILE_RANGE_FAULT (JSn_STATUS_INSTRUCTION_FAULT_BASE + 0x09) /* 0x59 means TILE RANGE FAULT */ 381#define JSn_STATUS_ADDRESS_RANGE_FAULT (JSn_STATUS_INSTRUCTION_FAULT_BASE + 0x0A) /* 0x5A means ADDRESS RANGE FAULT */ 382 383/* Other faults */ 384#define JSn_STATUS_MEMORY_FAULT_BASE 0x60 385#define JSn_STATUS_OUT_OF_MEMORY (JSn_STATUS_MEMORY_FAULT_BASE) /* 0x60 means OUT OF MEMORY */ 386#define JSn_STATUS_UNKNOWN 0x7F /* 0x7F means UNKNOWN */ 387 388/* GPU_COMMAND values */ 389#define GPU_COMMAND_NOP 0x00 /* No operation, nothing happens */ 390#define GPU_COMMAND_SOFT_RESET 0x01 /* Stop all external bus interfaces, and then reset the entire GPU. */ 391#define GPU_COMMAND_HARD_RESET 0x02 /* Immediately reset the entire GPU. */ 392#define GPU_COMMAND_PRFCNT_CLEAR 0x03 /* Clear all performance counters, setting them all to zero. */ 393#define GPU_COMMAND_PRFCNT_SAMPLE 0x04 /* Sample all performance counters, writing them out to memory */ 394#define GPU_COMMAND_CYCLE_COUNT_START 0x05 /* Starts the cycle counter, and system timestamp propagation */ 395#define GPU_COMMAND_CYCLE_COUNT_STOP 0x06 /* Stops the cycle counter, and system timestamp propagation */ 396#define GPU_COMMAND_CLEAN_CACHES 0x07 /* Clean all caches */ 397#define GPU_COMMAND_CLEAN_INV_CACHES 0x08 /* Clean and invalidate all caches */ 398 399/* End Command Values */ 400 401/* GPU_STATUS values */ 402#define GPU_STATUS_PRFCNT_ACTIVE (1 << 2) /* Set if the performance counters are active. */ 403 404/* PRFCNT_CONFIG register values */ 405#define PRFCNT_CONFIG_AS_SHIFT 4 /* address space bitmap starts from bit 4 of the register */ 406#define PRFCNT_CONFIG_MODE_OFF 0 /* The performance counters are disabled. */ 407#define PRFCNT_CONFIG_MODE_MANUAL 1 /* The performance counters are enabled, but are only written out when a PRFCNT_SAMPLE command is issued using the GPU_COMMAND register. */ 408#define PRFCNT_CONFIG_MODE_TILE 2 /* The performance counters are enabled, and are written out each time a tile finishes rendering. */ 409 410/* AS<n>_MEMATTR values: */ 411/* Use GPU implementation-defined caching policy. */ 412#define ASn_MEMATTR_IMPL_DEF_CACHE_POLICY 0x48 413/* The attribute set to force all resources to be cached. */ 414#define ASn_MEMATTR_FORCE_TO_CACHE_ALL 0x4F 415/* Inner write-alloc cache setup, no outer caching */ 416#define ASn_MEMATTR_WRITE_ALLOC 0x4D 417/* symbol for default MEMATTR to use */ 418#define ASn_MEMATTR_INDEX_DEFAULT 0 419/* HW implementation defined caching */ 420#define ASn_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY 0 421/* Force cache on */ 422#define ASn_MEMATTR_INDEX_FORCE_TO_CACHE_ALL 1 423/* Write-alloc inner */ 424#define ASn_MEMATTR_INDEX_WRITE_ALLOC 2 425 426/* GPU_ID register */ 427#define GPU_ID_VERSION_STATUS_SHIFT 0 428#define GPU_ID_VERSION_MINOR_SHIFT 4 429#define GPU_ID_VERSION_MAJOR_SHIFT 12 430#define GPU_ID_VERSION_PRODUCT_ID_SHIFT 16 431#define GPU_ID_VERSION_STATUS (0xF << GPU_ID_VERSION_STATUS_SHIFT) 432#define GPU_ID_VERSION_MINOR (0xFF << GPU_ID_VERSION_MINOR_SHIFT) 433#define GPU_ID_VERSION_MAJOR (0xF << GPU_ID_VERSION_MAJOR_SHIFT) 434#define GPU_ID_VERSION_PRODUCT_ID (0xFFFF << GPU_ID_VERSION_PRODUCT_ID_SHIFT) 435 436/* Values for GPU_ID_VERSION_PRODUCT_ID bitfield */ 437#define GPU_ID_PI_T60X 0x6956 438#define GPU_ID_PI_T62X 0x0620 439#define GPU_ID_PI_T76X 0x0750 440#define GPU_ID_PI_T72X 0x0720 441 442/* Values for GPU_ID_VERSION_STATUS field for PRODUCT_ID GPU_ID_PI_T60X */ 443#define GPU_ID_S_15DEV0 0x1 444#define GPU_ID_S_EAC 0x2 445 446/* Helper macro to create a GPU_ID assuming valid values for id, major, minor, status */ 447#define GPU_ID_MAKE(id, major, minor, status) \ 448 (((id) << GPU_ID_VERSION_PRODUCT_ID_SHIFT) | \ 449 ((major) << GPU_ID_VERSION_MAJOR_SHIFT) | \ 450 ((minor) << GPU_ID_VERSION_MINOR_SHIFT) | \ 451 ((status) << GPU_ID_VERSION_STATUS_SHIFT)) 452 453/* End GPU_ID register */ 454 455/* JS<n>_FEATURES register */ 456 457#define JSn_FEATURE_NULL_JOB (1u << 1) 458#define JSn_FEATURE_SET_VALUE_JOB (1u << 2) 459#define JSn_FEATURE_CACHE_FLUSH_JOB (1u << 3) 460#define JSn_FEATURE_COMPUTE_JOB (1u << 4) 461#define JSn_FEATURE_VERTEX_JOB (1u << 5) 462#define JSn_FEATURE_GEOMETRY_JOB (1u << 6) 463#define JSn_FEATURE_TILER_JOB (1u << 7) 464#define JSn_FEATURE_FUSED_JOB (1u << 8) 465#define JSn_FEATURE_FRAGMENT_JOB (1u << 9) 466 467/* End JS<n>_FEATURES register */ 468 469/* L2_MMU_CONFIG register */ 470#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT (24) 471#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 472#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 473#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 474#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 475 476#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT (26) 477#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 478#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 479#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 480#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 481/* End L2_MMU_CONFIG register */ 482 483/* THREAD_* registers */ 484 485/* THREAD_FEATURES IMPLEMENTATION_TECHNOLOGY values */ 486#define IMPLEMENTATION_UNSPECIFIED 0 487#define IMPLEMENTATION_SILICON 1 488#define IMPLEMENTATION_FPGA 2 489#define IMPLEMENTATION_MODEL 3 490 491/* Default values when registers are not supported by the implemented hardware */ 492#define THREAD_MT_DEFAULT 256 493#define THREAD_MWS_DEFAULT 256 494#define THREAD_MBS_DEFAULT 256 495#define THREAD_MR_DEFAULT 1024 496#define THREAD_MTQ_DEFAULT 4 497#define THREAD_MTGS_DEFAULT 10 498 499/* End THREAD_* registers */ 500 501/* SHADER_CONFIG register */ 502 503#define SC_ALT_COUNTERS (1ul << 3) 504#define SC_OVERRIDE_FWD_PIXEL_KILL (1ul << 4) 505#define SC_SDC_DISABLE_OQ_DISCARD (1ul << 6) 506#define SC_LS_PAUSEBUFFER_DISABLE (1ul << 16) 507#define SC_ENABLE_TEXGRD_FLAGS (1ul << 25) 508/* End SHADER_CONFIG register */ 509 510#endif /* _MIDGARD_REGMAP_H_ */ 511