1<?xml version="1.0" ?>
2<component id="root" name="root">
3	<component id="system" name="system" type="System">
4		<param name="core_tech_node" value="40"/>
5		<param name="target_core_clockrate" value="1700"/>
6		<param name="temperature" value="380"/>
7		<param name="interconnect_projection_type" value="1"/>
8		<param name="device_type" value="0"/>
9		<param name="longer_channel_device" value="0"/>
10		<param name="machine_bits" value="64"/>
11		<param name="virtual_address_width" value="64"/>
12		<param name="physical_address_width" value="36"/>
13		<param name="virtual_memory_page_size" value="4096"/>
14		<param name="wire_is_mat_type" value="2"/>
15		<param name="wire_os_mat_type" value="2"/>
16		<param name="delay_wt" value="100"/>
17		<param name="area_wt" value="0"/>
18		<param name="dynamic_power_wt" value="100"/>
19		<param name="leakage_power_wt" value="0"/>
20		<param name="cycle_time_wt" value="0"/>
21		<param name="delay_dev" value="10000"/>
22		<param name="area_dev" value="10000"/>
23		<param name="dynamic_power_dev" value="10000"/>
24		<param name="leakage_power_dev" value="10000"/>
25		<param name="cycle_time_dev" value="10000"/>
26		<param name="ed" value="2"/>
27		<param name="burst_len" value="1"/>
28		<param name="int_prefetch_w" value="1"/>
29		<param name="page_sz_bits" value="0"/>
30		<param name="rpters_in_htree" value="1"/>
31		<param name="ver_htree_wires_over_array" value="0"/>
32		<param name="nuca" value="0"/>
33		<param name="nuca_bank_count" value="0"/>
34		<param name="force_cache_config" value="0"/>
35		<param name="wt" value="0"/>
36		<param name="force_wiretype" value="0"/>
37		<param name="print_detail" value="1"/>
38		<param name="add_ecc_b_" value="1"/>
39		<stat name="total_cycles" value="150"/>
40		<component id="system.core0" name="core0" type="Core">
41			<param name="clock_rate" value="1700"/>
42			<param name="opt_local" value="0"/>
43			<param name="instruction_length" value="32"/>
44			<param name="opcode_width" value="8"/>
45			<param name="x86" value="1"/>
46			<param name="micro_opcode_width" value="8"/>
47			<param name="machine_type" value="0"/>
48			<param name="number_hardware_threads" value="2"/>
49			<param name="fetch_width" value="1"/>
50			<param name="number_instruction_fetch_ports" value="1"/>
51			<param name="decode_width" value="2"/>
52			<param name="issue_width" value="2"/>
53			<param name="peak_issue_width" value="2"/>
54			<param name="commit_width" value="2"/>
55			<param name="fp_issue_width" value="2"/>
56			<param name="prediction_width" value="1"/>
57			<param name="int_pipelines" value="2"/>
58			<param name="fp_pipelines" value="1"/>
59			<param name="int_pipeline_depth" value="12"/>
60			<param name="fp_pipeline_depth" value="13"/>
61			<param name="ALU_per_core" value="2"/>
62			<param name="MUL_per_core" value="1"/>
63			<param name="FPU_per_core" value="1"/>
64			<param name="instruction_buffer_size" value="16"/>
65			<param name="instruction_window_scheme" value="0"/>
66			<param name="instruction_window_size" value="7"/>
67			<param name="fp_instruction_window_size" value="18"/>
68			<param name="ROB_size" value="56"/>
69			<param name="archi_Regs_IRF_size" value="30"/>
70			<param name="archi_Regs_FRF_size" value="48"/>
71			<param name="phy_Regs_IRF_size" value="34"/>
72			<param name="phy_Regs_FRF_size" value="40"/>
73			<param name="rename_scheme" value="0"/>
74			<param name="register_window_size" value="0"/>
75			<param name="store_buffer_size" value="32"/>
76			<param name="load_buffer_size" value="22"/>
77			<param name="memory_ports" value="1"/>
78			<param name="RAS_size" value="16"/>
79			<param name="execu_wire_mat_type" value="2"/>
80			<param name="execu_bypass_base_width" value="1"/>
81			<param name="execu_bypass_base_height" value="1"/>
82			<param name="execu_bypass_start_wiring_level"value="3"/>
83			<param name="execu_bypass_route_over_perc" value="1"/>
84			<param name="globalCheckpoint" value="32"/>
85			<param name="perThreadState" value="8"/>
86			<param name="ROB_assoc" value="1"/>
87			<param name="ROB_nbanks" value="1"/>
88			<param name="ROB_tag_width" value="0"/>
89			<param name="scheduler_assoc" value="0"/>
90			<param name="scheduler_nbanks" value="1"/>
91			<param name="register_window_assoc" value="1"/>
92			<param name="register_window_nbanks" value="1"/>
93			<param name="register_window_tag_width" value="0"/>
94			<param name="register_window_rw_ports" value="1"/>
95			<param name="phy_Regs_IRF_assoc" value="1"/>
96			<param name="phy_Regs_IRF_nbanks" value="1"/>
97			<param name="phy_Regs_IRF_tag_width" value="0"/>
98			<param name="phy_Regs_IRF_rd_ports" value="1"/>
99			<param name="phy_Regs_IRF_wr_ports" value="1"/>
100			<param name="phy_Regs_FRF_assoc" value="1"/>
101			<param name="phy_Regs_FRF_nbanks" value="1"/>
102			<param name="phy_Regs_FRF_tag_width" value="0"/>
103			<param name="phy_Regs_FRF_rd_ports" value="1"/>
104			<param name="phy_Regs_FRF_wr_ports" value="1"/>
105			<param name="front_rat_nbanks" value="1"/>
106			<param name="front_rat_rw_ports" value="1"/>
107			<param name="retire_rat_nbanks" value="1"/>
108			<param name="retire_rat_rw_ports" value="0"/>
109			<param name="freelist_nbanks" value="1"/>
110			<param name="freelist_rw_ports" value="1"/>
111			<param name="load_buffer_assoc" value="0"/>
112			<param name="load_buffer_nbanks" value="1"/>
113			<param name="store_buffer_assoc" value="0"/>
114			<param name="store_buffer_nbanks" value="1"/>
115			<param name="instruction_buffer_assoc" value="1"/>
116			<param name="instruction_buffer_nbanks" value="1"/>
117			<param name="instruction_buffer_tag_width" value="0"/>
118			<stat name="total_instructions" value="100"/>
119			<stat name="int_instructions" value="50"/>
120			<stat name="fp_instructions" value="50"/>
121			<stat name="branch_instructions" value="20"/>
122			<stat name="branch_mispredictions" value="2"/>
123			<stat name="load_instructions" value="50"/>
124			<stat name="store_instructions" value="15"/>
125			<stat name="committed_instructions" value="100"/>
126			<stat name="committed_int_instructions" value="50"/>
127			<stat name="committed_fp_instructions" value="50"/>
128			<stat name="pipeline_duty_cycle" value="1"/>
129			<stat name="total_cycles" value="150"/>
130			<stat name="idle_cycles" value="30"/>
131			<stat name="busy_cycles" value="120"/>
132			<stat name="ROB_reads" value="100"/>
133			<stat name="ROB_writes" value="100"/>
134			<stat name="rename_reads" value="100"/>
135			<stat name="rename_writes" value="50"/>
136			<stat name="fp_rename_reads" value="100"/>
137			<stat name="fp_rename_writes" value="50"/>
138			<stat name="inst_window_reads" value="50"/>
139			<stat name="inst_window_writes" value="50"/>
140			<stat name="inst_window_wakeup_accesses" value="50"/>
141			<stat name="fp_inst_window_reads" value="50"/>
142			<stat name="fp_inst_window_writes" value="50"/>
143			<stat name="fp_inst_window_wakeup_accesses" value="50"/>
144			<stat name="int_regfile_reads" value="100"/>
145			<stat name="float_regfile_reads" value="100"/>
146			<stat name="int_regfile_writes" value="50"/>
147			<stat name="float_regfile_writes" value="50"/>
148			<stat name="function_calls" value="0"/>
149			<stat name="context_switches" value="0"/>
150			<stat name="ialu_accesses" value="15"/>
151			<stat name="fpu_accesses" value="15"/>
152			<stat name="mul_accesses" value="15"/>
153			<stat name="cdb_alu_accesses" value="15"/>
154			<stat name="cdb_mul_accesses" value="15"/>
155			<stat name="cdb_fpu_accesses" value="15"/>
156			<stat name="IFU_duty_cycle" value="1"/>
157			<stat name="LSU_duty_cycle" value="1"/>
158			<stat name="MemManU_I_duty_cycle" value="1"/>
159			<stat name="MemManU_D_duty_cycle" value="1"/>
160			<stat name="ALU_duty_cycle" value="1"/>
161			<stat name="MUL_duty_cycle" value="1"/>
162			<stat name="FPU_duty_cycle" value="1"/>
163			<stat name="ALU_cdb_duty_cycle" value="1"/>
164			<stat name="MUL_cdb_duty_cycle" value="1"/>
165			<stat name="FPU_cdb_duty_cycle" value="1"/>
166			<component id="system.core0.predictor" name="PBT" type="BranchPredictor">
167				<param name="assoc" value="1"/>
168				<param name="nbanks" value="1"/>
169				<param name="local_l1_predictor_size" value="12"/>
170				<param name="local_l2_predictor_size" value="4"/>
171				<param name="local_predictor_entries" value="8192"/>
172				<param name="global_predictor_entries" value="8192"/>
173				<param name="global_predictor_bits" value="4"/>
174				<param name="chooser_predictor_entries" value="8192"/>
175				<param name="chooser_predictor_bits" value="4"/>
176			</component>
177			<component id="system.core0.itlb" name="itlb" type="InstructionTLB">
178				<param name="number_entries" value="512"/>
179				<param name="latency" value="8"/>
180				<param name="throughput" value="3"/>
181				<param name="assoc" value="0"/>
182				<param name="nbanks" value="1"/>
183				<stat name="total_accesses" value="50"/>
184				<stat name="total_misses" value="3"/>
185				<stat name="conflicts" value="3"/>
186			</component>
187			<component id="system.core0.icache" name="Instruction Cache" type="CacheUnit">
188				<param name="level" value="1"/>
189				<param name="size" value="32768"/>
190				<param name="block_size" value="64"/>
191				<param name="assoc" value="2"/>
192				<param name="num_banks" value="1"/>
193				<param name="latency" value="8"/>
194				<param name="throughput" value="3"/>
195				<param name="miss_buffer_size" value="2"/>
196				<param name="fetch_buffer_size" value="2"/>
197				<param name="prefetch_buffer_size" value="2"/>
198				<param name="writeback_buffer_size" value="0"/>
199				<param name="device_type" value="0"/>
200				<param name="clockrate" value="0"/>
201				<param name="tech_type" value="0"/>
202				<param name="Directory_type" value="2"/>
203				<param name="core_type" value="1"/>
204				<param name="wire_mat_type" value="2"/>
205				<param name="wire_type" value="0"/>
206				<param name="miss_buffer_assoc" value="0"/>
207				<param name="fetch_buffer_assoc" value="0"/>
208				<param name="prefetch_buffer_assoc" value="0"/>
209				<param name="writeback_buffer_assoc" value="0"/>
210				<param name="miss_buffer_banks" value="1"/>
211				<param name="fetch_buffer_banks" value="1"/>
212				<param name="prefetch_buffer_banks" value="1"/>
213				<param name="writeback_buffer_banks" value="1"/>
214				<param name="cache_access_mode" value="0"/>
215				<param name="miss_buff_access_mode" value="2"/>
216				<param name="fetch_buff_access_mode" value="2"/>
217				<param name="prefetch_buff_access_mode" value="2"/>
218				<param name="writeback_buff_access_mode"value="2"/>
219				<param name="cache_rw_ports" value="1"/>
220				<param name="cache_rd_ports" value="0"/>
221				<param name="cache_wr_ports" value="0"/>
222				<param name="cache_se_rd_ports" value="0"/>
223				<param name="cache_search_ports" value="0"/>
224				<param name="miss_buff_rw_ports" value="1"/>
225				<param name="miss_buff_rd_ports" value="0"/>
226				<param name="miss_buff_wr_ports" value="0"/>
227				<param name="miss_buff_se_rd_ports" value="0"/>
228				<param name="miss_buff_search_ports" value="1"/>
229				<param name="fetch_buff_rw_ports" value="1"/>
230				<param name="fetch_buff_rd_ports" value="0"/>
231				<param name="fetch_buff_wr_ports" value="0"/>
232				<param name="fetch_buff_se_rd_ports" value="0"/>
233				<param name="fetch_buff_search_ports" value="1"/>
234				<param name="pf_buff_rw_ports" value="1"/>
235				<param name="pf_buff_rd_ports" value="0"/>
236				<param name="pf_buff_wr_ports" value="0"/>
237				<param name="pf_buff_se_rd_ports" value="0"/>
238				<param name="pf_buff_search_ports" value="1"/>
239				<param name="wb_buff_rw_ports" value="1"/>
240				<param name="wb_buff_rd_ports" value="0"/>
241				<param name="wb_buff_wr_ports" value="0"/>
242				<param name="wb_buff_se_rd_ports" value="0"/>
243				<param name="wb_buff_search_ports" value="1"/>
244				<param name="pure_ram" value="0"/>
245				<stat name="read_accesses" value="50"/>
246				<stat name="read_misses" value="12"/>
247				<stat name="conflicts" value="1"/>
248				<stat name="duty_cycle" value="1"/>
249			</component>
250			<component id="system.core0.dtlb" name="dtlb" type="DataTLB">
251				<param name="number_entries" value="512"/>
252				<param name="latency" value="8"/>
253				<param name="throughput" value="3"/>
254				<param name="assoc" value="0"/>
255				<param name="nbanks" value="1"/>
256				<stat name="read_accesses" value="65"/>
257				<stat name="read_misses" value="1"/>
258				<stat name="conflicts" value="1"/>
259			</component>
260			<component id="system.core0.dcache" name="Data Cache" type="CacheUnit">
261				<param name="level" value="1"/>
262				<param name="size" value="32768"/>
263				<param name="block_size" value="64"/>
264				<param name="assoc" value="8"/>
265				<param name="num_banks" value="1"/>
266				<param name="latency" value="8"/>
267				<param name="throughput" value="3"/>
268				<param name="miss_buffer_size" value="8"/>
269				<param name="fetch_buffer_size" value="8"/>
270				<param name="prefetch_buffer_size" value="8"/>
271				<param name="writeback_buffer_size" value="8"/>
272				<param name="device_type" value="0"/>
273				<param name="clockrate" value="0"/>
274				<param name="tech_type" value="0"/>
275				<param name="Directory_type" value="2"/>
276				<param name="core_type" value="1"/>
277				<param name="wire_mat_type" value="2"/>
278				<param name="wire_type" value="0"/>
279				<param name="miss_buffer_assoc" value="0"/>
280				<param name="fetch_buffer_assoc" value="0"/>
281				<param name="prefetch_buffer_assoc" value="0"/>
282				<param name="writeback_buffer_assoc" value="0"/>
283				<param name="miss_buffer_banks" value="1"/>
284				<param name="fetch_buffer_banks" value="1"/>
285				<param name="prefetch_buffer_banks" value="1"/>
286				<param name="writeback_buffer_banks" value="1"/>
287				<param name="cache_access_mode" value="0"/>
288				<param name="miss_buff_access_mode" value="2"/>
289				<param name="fetch_buff_access_mode" value="2"/>
290				<param name="prefetch_buff_access_mode" value="2"/>
291				<param name="writeback_buff_access_mode"value="2"/>
292				<param name="cache_rw_ports" value="1"/>
293				<param name="cache_rd_ports" value="0"/>
294				<param name="cache_wr_ports" value="0"/>
295				<param name="cache_se_rd_ports" value="0"/>
296				<param name="cache_search_ports" value="0"/>
297				<param name="miss_buff_rw_ports" value="1"/>
298				<param name="miss_buff_rd_ports" value="0"/>
299				<param name="miss_buff_wr_ports" value="0"/>
300				<param name="miss_buff_se_rd_ports" value="0"/>
301				<param name="miss_buff_search_ports" value="1"/>
302				<param name="fetch_buff_rw_ports" value="1"/>
303				<param name="fetch_buff_rd_ports" value="0"/>
304				<param name="fetch_buff_wr_ports" value="0"/>
305				<param name="fetch_buff_se_rd_ports" value="0"/>
306				<param name="fetch_buff_search_ports" value="1"/>
307				<param name="pf_buff_rw_ports" value="1"/>
308				<param name="pf_buff_rd_ports" value="0"/>
309				<param name="pf_buff_wr_ports" value="0"/>
310				<param name="pf_buff_se_rd_ports" value="0"/>
311				<param name="pf_buff_search_ports" value="1"/>
312				<param name="wb_buff_rw_ports" value="1"/>
313				<param name="wb_buff_rd_ports" value="0"/>
314				<param name="wb_buff_wr_ports" value="0"/>
315				<param name="wb_buff_se_rd_ports" value="0"/>
316				<param name="wb_buff_search_ports" value="1"/>
317				<param name="pure_ram" value="0"/>
318				<stat name="read_accesses" value="50"/>
319				<stat name="write_accesses" value="15"/>
320				<stat name="read_misses" value="12"/>
321				<stat name="write_misses" value="3"/>
322				<stat name="conflicts" value="1"/>
323				<stat name="duty_cycle" value="1"/>
324			</component>
325			<component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer">
326				<param name="size" value="8192"/>
327				<param name="block_size" value="4"/>
328				<param name="assoc" value="2"/>
329				<param name="num_banks" value="1"/>
330				<param name="latency" value="1"/>
331				<param name="throughput" value="3"/>
332				<param name="rw_ports" value="1"/>
333				<stat name="read_accesses" value="20"/>
334				<stat name="write_accesses" value="20"/>
335			</component>
336		</component>
337	</component>
338</component>
339