1/***************************************************************************** 2 * McPAT/CACTI 3 * SOFTWARE LICENSE AGREEMENT 4 * Copyright 2012 Hewlett-Packard Development Company, L.P. 5 * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 6 * All Rights Reserved 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are 10 * met: redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer; 12 * redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution; 15 * neither the name of the copyright holders nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 ***************************************************************************/ 32 33 34#include "basic_circuit.h" 35 36#include "parameter.h" 37 38double wire_resistance(double resistivity, double wire_width, 39 double wire_thickness, 40 double barrier_thickness, double dishing_thickness, 41 double alpha_scatter) { 42 double resistance; 43 resistance = alpha_scatter * resistivity / 44 ((wire_thickness - barrier_thickness - dishing_thickness) * 45 (wire_width - 2 * barrier_thickness)); 46 return(resistance); 47} 48 49double wire_capacitance(double wire_width, double wire_thickness, 50 double wire_spacing, 51 double ild_thickness, double miller_value, 52 double horiz_dielectric_constant, 53 double vert_dielectric_constant, double fringe_cap) { 54 double vertical_cap, sidewall_cap, total_cap; 55 vertical_cap = 2 * PERMITTIVITY_FREE_SPACE * vert_dielectric_constant * wire_width / ild_thickness; 56 sidewall_cap = 2 * PERMITTIVITY_FREE_SPACE * miller_value * horiz_dielectric_constant * wire_thickness / wire_spacing; 57 total_cap = vertical_cap + sidewall_cap + fringe_cap; 58 return(total_cap); 59} 60 61 62void init_tech_params(double technology, bool is_tag) { 63 int iter, tech, tech_lo, tech_hi; 64 double curr_alpha, curr_vpp; 65 double wire_width, wire_thickness, wire_spacing, 66 fringe_cap, pmos_to_nmos_sizing_r; 67// double aspect_ratio,ild_thickness, miller_value = 1.5, horiz_dielectric_constant, vert_dielectric_constant; 68 double barrier_thickness, dishing_thickness, alpha_scatter; 69 double curr_vdd_dram_cell, curr_v_th_dram_access_transistor, curr_I_on_dram_cell, curr_c_dram_cell; 70 71 uint32_t ram_cell_tech_type = (is_tag) ? g_ip->tag_arr_ram_cell_tech_type : g_ip->data_arr_ram_cell_tech_type; 72 uint32_t peri_global_tech_type = (is_tag) ? g_ip->tag_arr_peri_global_tech_type : g_ip->data_arr_peri_global_tech_type; 73 74 technology = technology * 1000.0; // in the unit of nm 75 76 // initialize parameters 77 g_tp.reset(); 78 double gmp_to_gmn_multiplier_periph_global = 0; 79 80 double curr_Wmemcella_dram, curr_Wmemcellpmos_dram, curr_Wmemcellnmos_dram, 81 curr_area_cell_dram, curr_asp_ratio_cell_dram, curr_Wmemcella_sram, 82 curr_Wmemcellpmos_sram, curr_Wmemcellnmos_sram, curr_area_cell_sram, 83 curr_asp_ratio_cell_sram, curr_I_off_dram_cell_worst_case_length_temp; 84 double curr_Wmemcella_cam, curr_Wmemcellpmos_cam, curr_Wmemcellnmos_cam, curr_area_cell_cam,//Sheng: CAM data 85 curr_asp_ratio_cell_cam; 86 double SENSE_AMP_D, SENSE_AMP_P; // J 87 double area_cell_dram = 0; 88 double asp_ratio_cell_dram = 0; 89 double area_cell_sram = 0; 90 double asp_ratio_cell_sram = 0; 91 double area_cell_cam = 0; 92 double asp_ratio_cell_cam = 0; 93 double mobility_eff_periph_global = 0; 94 double Vdsat_periph_global = 0; 95 double nmos_effective_resistance_multiplier; 96 double width_dram_access_transistor; 97 98 double curr_logic_scaling_co_eff = 0;//This is based on the reported numbers of Intel Merom 65nm, Penryn45nm and IBM cell 90/65/45 date 99 double curr_core_tx_density = 0;//this is density per um^2; 90, ...22nm based on Intel Penryn 100 double curr_chip_layout_overhead = 0; 101 double curr_macro_layout_overhead = 0; 102 double curr_sckt_co_eff = 0; 103 104 if (technology < 181 && technology > 179) { 105 tech_lo = 180; 106 tech_hi = 180; 107 } else if (technology < 91 && technology > 89) { 108 tech_lo = 90; 109 tech_hi = 90; 110 } else if (technology < 66 && technology > 64) { 111 tech_lo = 65; 112 tech_hi = 65; 113 } else if (technology < 46 && technology > 44) { 114 tech_lo = 45; 115 tech_hi = 45; 116 } else if (technology < 33 && technology > 31) { 117 tech_lo = 32; 118 tech_hi = 32; 119 } else if (technology < 23 && technology > 21) { 120 tech_lo = 22; 121 tech_hi = 22; 122 if (ram_cell_tech_type == 3 ) { 123 cout << "current version does not support eDRAM technologies at " 124 << "22nm" << endl; 125 exit(0); 126 } 127 } else if (technology < 180 && technology > 90) { 128 tech_lo = 180; 129 tech_hi = 90; 130 } else if (technology < 90 && technology > 65) { 131 tech_lo = 90; 132 tech_hi = 65; 133 } else if (technology < 65 && technology > 45) { 134 tech_lo = 65; 135 tech_hi = 45; 136 } else if (technology < 45 && technology > 32) { 137 tech_lo = 45; 138 tech_hi = 32; 139 } else if (technology < 32 && technology > 22) { 140 tech_lo = 32; 141 tech_hi = 22; 142 } 143// else if (technology < 22 && technology > 16) 144// { 145// tech_lo = 22; 146// tech_hi = 16; 147// } 148 else { 149 cout << "Invalid technology nodes" << endl; 150 exit(0); 151 } 152 153 double vdd[NUMBER_TECH_FLAVORS]; 154 double Lphy[NUMBER_TECH_FLAVORS]; 155 double Lelec[NUMBER_TECH_FLAVORS]; 156 double t_ox[NUMBER_TECH_FLAVORS]; 157 double v_th[NUMBER_TECH_FLAVORS]; 158 double c_ox[NUMBER_TECH_FLAVORS]; 159 double mobility_eff[NUMBER_TECH_FLAVORS]; 160 double Vdsat[NUMBER_TECH_FLAVORS]; 161 double c_g_ideal[NUMBER_TECH_FLAVORS]; 162 double c_fringe[NUMBER_TECH_FLAVORS]; 163 double c_junc[NUMBER_TECH_FLAVORS]; 164 double I_on_n[NUMBER_TECH_FLAVORS]; 165 double I_on_p[NUMBER_TECH_FLAVORS]; 166 double Rnchannelon[NUMBER_TECH_FLAVORS]; 167 double Rpchannelon[NUMBER_TECH_FLAVORS]; 168 double n_to_p_eff_curr_drv_ratio[NUMBER_TECH_FLAVORS]; 169 double I_off_n[NUMBER_TECH_FLAVORS][101]; 170 double I_g_on_n[NUMBER_TECH_FLAVORS][101]; 171 double gmp_to_gmn_multiplier[NUMBER_TECH_FLAVORS]; 172 double long_channel_leakage_reduction[NUMBER_TECH_FLAVORS]; 173 174 for (iter = 0; iter <= 1; ++iter) { 175 // linear interpolation 176 if (iter == 0) { 177 tech = tech_lo; 178 if (tech_lo == tech_hi) { 179 curr_alpha = 1; 180 } else { 181 curr_alpha = (technology - tech_hi) / (tech_lo - tech_hi); 182 } 183 } else { 184 tech = tech_hi; 185 if (tech_lo == tech_hi) { 186 break; 187 } else { 188 curr_alpha = (tech_lo - technology) / (tech_lo - tech_hi); 189 } 190 } 191 192 if (tech == 180) { 193 //180nm technology-node. Corresponds to year 1999 in ITRS 194 //Only HP transistor was of interest that 180nm since leakage power was not a big issue. Performance was the king 195 //MASTAR does not contain data for 0.18um process. The following parameters are projected based on ITRS 2000 update and IBM 0.18 Cu Spice input 196 bool Aggre_proj = false; 197 SENSE_AMP_D = .28e-9; // s 198 SENSE_AMP_P = 14.7e-15; // J 199 vdd[0] = 1.5; 200 Lphy[0] = 0.12;//Lphy is the physical gate-length. micron 201 Lelec[0] = 0.10;//Lelec is the electrical gate-length. micron 202 t_ox[0] = 1.2e-3 * (Aggre_proj ? 1.9 / 1.2 : 2);//micron 203 v_th[0] = Aggre_proj ? 0.36 : 0.4407;//V 204 c_ox[0] = 1.79e-14 * (Aggre_proj ? 1.9 / 1.2 : 2);//F/micron2 205 mobility_eff[0] = 302.16 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 206 Vdsat[0] = 0.128 * 2; //V 207 c_g_ideal[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 6.64e-16;//F/micron 208 c_fringe[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 0.08e-15;//F/micron 209 c_junc[0] = (Aggre_proj ? 1.9 / 1.2 : 2) * 1e-15;//F/micron2 210 I_on_n[0] = 750e-6;//A/micron 211 I_on_p[0] = 350e-6;//A/micron 212 //Note that nmos_effective_resistance_multiplier, n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are calculated offline 213 nmos_effective_resistance_multiplier = 1.54; 214 n_to_p_eff_curr_drv_ratio[0] = 2.45; 215 gmp_to_gmn_multiplier[0] = 1.22; 216 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron 217 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron 218 long_channel_leakage_reduction[0] = 1; 219 I_off_n[0][0] = 7e-10;//A/micron 220 I_off_n[0][10] = 8.26e-10; 221 I_off_n[0][20] = 9.74e-10; 222 I_off_n[0][30] = 1.15e-9; 223 I_off_n[0][40] = 1.35e-9; 224 I_off_n[0][50] = 1.60e-9; 225 I_off_n[0][60] = 1.88e-9; 226 I_off_n[0][70] = 2.29e-9; 227 I_off_n[0][80] = 2.70e-9; 228 I_off_n[0][90] = 3.19e-9; 229 I_off_n[0][100] = 3.76e-9; 230 231 I_g_on_n[0][0] = 1.65e-10;//A/micron 232 I_g_on_n[0][10] = 1.65e-10; 233 I_g_on_n[0][20] = 1.65e-10; 234 I_g_on_n[0][30] = 1.65e-10; 235 I_g_on_n[0][40] = 1.65e-10; 236 I_g_on_n[0][50] = 1.65e-10; 237 I_g_on_n[0][60] = 1.65e-10; 238 I_g_on_n[0][70] = 1.65e-10; 239 I_g_on_n[0][80] = 1.65e-10; 240 I_g_on_n[0][90] = 1.65e-10; 241 I_g_on_n[0][100] = 1.65e-10; 242 243 //SRAM cell properties 244 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 245 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 246 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 247 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 248 curr_asp_ratio_cell_sram = 1.46; 249 //CAM cell properties //TODO: data need to be revisited 250 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 251 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 252 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 253 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um;//360 254 curr_asp_ratio_cell_cam = 2.92;//2.5 255 //Empirical undifferetiated core/FU coefficient 256 curr_logic_scaling_co_eff = 1.5;//linear scaling from 90nm 257 curr_core_tx_density = 1.25 * 0.7 * 0.7 * 0.4; 258 curr_sckt_co_eff = 1.11; 259 curr_chip_layout_overhead = 1.0;//die measurement results based on Niagara 1 and 2 260 curr_macro_layout_overhead = 1.0;//EDA placement and routing tool rule of thumb 261 262 } 263 264 if (tech == 90) { 265 SENSE_AMP_D = .28e-9; // s 266 SENSE_AMP_P = 14.7e-15; // J 267 //90nm technology-node. Corresponds to year 2004 in ITRS 268 //ITRS HP device type 269 vdd[0] = 1.2; 270 Lphy[0] = 0.037;//Lphy is the physical gate-length. micron 271 Lelec[0] = 0.0266;//Lelec is the electrical gate-length. micron 272 t_ox[0] = 1.2e-3;//micron 273 v_th[0] = 0.23707;//V 274 c_ox[0] = 1.79e-14;//F/micron2 275 mobility_eff[0] = 342.16 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 276 Vdsat[0] = 0.128; //V 277 c_g_ideal[0] = 6.64e-16;//F/micron 278 c_fringe[0] = 0.08e-15;//F/micron 279 c_junc[0] = 1e-15;//F/micron2 280 I_on_n[0] = 1076.9e-6;//A/micron 281 I_on_p[0] = 712.6e-6;//A/micron 282 //Note that nmos_effective_resistance_multiplier, n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier values are calculated offline 283 nmos_effective_resistance_multiplier = 1.54; 284 n_to_p_eff_curr_drv_ratio[0] = 2.45; 285 gmp_to_gmn_multiplier[0] = 1.22; 286 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron 287 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron 288 long_channel_leakage_reduction[0] = 1; 289 I_off_n[0][0] = 3.24e-8;//A/micron 290 I_off_n[0][10] = 4.01e-8; 291 I_off_n[0][20] = 4.90e-8; 292 I_off_n[0][30] = 5.92e-8; 293 I_off_n[0][40] = 7.08e-8; 294 I_off_n[0][50] = 8.38e-8; 295 I_off_n[0][60] = 9.82e-8; 296 I_off_n[0][70] = 1.14e-7; 297 I_off_n[0][80] = 1.29e-7; 298 I_off_n[0][90] = 1.43e-7; 299 I_off_n[0][100] = 1.54e-7; 300 301 I_g_on_n[0][0] = 1.65e-8;//A/micron 302 I_g_on_n[0][10] = 1.65e-8; 303 I_g_on_n[0][20] = 1.65e-8; 304 I_g_on_n[0][30] = 1.65e-8; 305 I_g_on_n[0][40] = 1.65e-8; 306 I_g_on_n[0][50] = 1.65e-8; 307 I_g_on_n[0][60] = 1.65e-8; 308 I_g_on_n[0][70] = 1.65e-8; 309 I_g_on_n[0][80] = 1.65e-8; 310 I_g_on_n[0][90] = 1.65e-8; 311 I_g_on_n[0][100] = 1.65e-8; 312 313 //ITRS LSTP device type 314 vdd[1] = 1.3; 315 Lphy[1] = 0.075; 316 Lelec[1] = 0.0486; 317 t_ox[1] = 2.2e-3; 318 v_th[1] = 0.48203; 319 c_ox[1] = 1.22e-14; 320 mobility_eff[1] = 356.76 * (1e-2 * 1e6 * 1e-2 * 1e6); 321 Vdsat[1] = 0.373; 322 c_g_ideal[1] = 9.15e-16; 323 c_fringe[1] = 0.08e-15; 324 c_junc[1] = 1e-15; 325 I_on_n[1] = 503.6e-6; 326 I_on_p[1] = 235.1e-6; 327 nmos_effective_resistance_multiplier = 1.92; 328 n_to_p_eff_curr_drv_ratio[1] = 2.44; 329 gmp_to_gmn_multiplier[1] = 0.88; 330 Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1]; 331 Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; 332 long_channel_leakage_reduction[1] = 1; 333 I_off_n[1][0] = 2.81e-12; 334 I_off_n[1][10] = 4.76e-12; 335 I_off_n[1][20] = 7.82e-12; 336 I_off_n[1][30] = 1.25e-11; 337 I_off_n[1][40] = 1.94e-11; 338 I_off_n[1][50] = 2.94e-11; 339 I_off_n[1][60] = 4.36e-11; 340 I_off_n[1][70] = 6.32e-11; 341 I_off_n[1][80] = 8.95e-11; 342 I_off_n[1][90] = 1.25e-10; 343 I_off_n[1][100] = 1.7e-10; 344 345 I_g_on_n[1][0] = 3.87e-11;//A/micron 346 I_g_on_n[1][10] = 3.87e-11; 347 I_g_on_n[1][20] = 3.87e-11; 348 I_g_on_n[1][30] = 3.87e-11; 349 I_g_on_n[1][40] = 3.87e-11; 350 I_g_on_n[1][50] = 3.87e-11; 351 I_g_on_n[1][60] = 3.87e-11; 352 I_g_on_n[1][70] = 3.87e-11; 353 I_g_on_n[1][80] = 3.87e-11; 354 I_g_on_n[1][90] = 3.87e-11; 355 I_g_on_n[1][100] = 3.87e-11; 356 357 //ITRS LOP device type 358 vdd[2] = 0.9; 359 Lphy[2] = 0.053; 360 Lelec[2] = 0.0354; 361 t_ox[2] = 1.5e-3; 362 v_th[2] = 0.30764; 363 c_ox[2] = 1.59e-14; 364 mobility_eff[2] = 460.39 * (1e-2 * 1e6 * 1e-2 * 1e6); 365 Vdsat[2] = 0.113; 366 c_g_ideal[2] = 8.45e-16; 367 c_fringe[2] = 0.08e-15; 368 c_junc[2] = 1e-15; 369 I_on_n[2] = 386.6e-6; 370 I_on_p[2] = 209.7e-6; 371 nmos_effective_resistance_multiplier = 1.77; 372 n_to_p_eff_curr_drv_ratio[2] = 2.54; 373 gmp_to_gmn_multiplier[2] = 0.98; 374 Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2]; 375 Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; 376 long_channel_leakage_reduction[2] = 1; 377 I_off_n[2][0] = 2.14e-9; 378 I_off_n[2][10] = 2.9e-9; 379 I_off_n[2][20] = 3.87e-9; 380 I_off_n[2][30] = 5.07e-9; 381 I_off_n[2][40] = 6.54e-9; 382 I_off_n[2][50] = 8.27e-8; 383 I_off_n[2][60] = 1.02e-7; 384 I_off_n[2][70] = 1.20e-7; 385 I_off_n[2][80] = 1.36e-8; 386 I_off_n[2][90] = 1.52e-8; 387 I_off_n[2][100] = 1.73e-8; 388 389 I_g_on_n[2][0] = 4.31e-8;//A/micron 390 I_g_on_n[2][10] = 4.31e-8; 391 I_g_on_n[2][20] = 4.31e-8; 392 I_g_on_n[2][30] = 4.31e-8; 393 I_g_on_n[2][40] = 4.31e-8; 394 I_g_on_n[2][50] = 4.31e-8; 395 I_g_on_n[2][60] = 4.31e-8; 396 I_g_on_n[2][70] = 4.31e-8; 397 I_g_on_n[2][80] = 4.31e-8; 398 I_g_on_n[2][90] = 4.31e-8; 399 I_g_on_n[2][100] = 4.31e-8; 400 401 if (ram_cell_tech_type == lp_dram) { 402 //LP-DRAM cell access transistor technology parameters 403 curr_vdd_dram_cell = 1.2; 404 Lphy[3] = 0.12; 405 Lelec[3] = 0.0756; 406 curr_v_th_dram_access_transistor = 0.4545; 407 width_dram_access_transistor = 0.14; 408 curr_I_on_dram_cell = 45e-6; 409 curr_I_off_dram_cell_worst_case_length_temp = 21.1e-12; 410 curr_Wmemcella_dram = width_dram_access_transistor; 411 curr_Wmemcellpmos_dram = 0; 412 curr_Wmemcellnmos_dram = 0; 413 curr_area_cell_dram = 0.168; 414 curr_asp_ratio_cell_dram = 1.46; 415 curr_c_dram_cell = 20e-15; 416 417 //LP-DRAM wordline transistor parameters 418 curr_vpp = 1.6; 419 t_ox[3] = 2.2e-3; 420 v_th[3] = 0.4545; 421 c_ox[3] = 1.22e-14; 422 mobility_eff[3] = 323.95 * (1e-2 * 1e6 * 1e-2 * 1e6); 423 Vdsat[3] = 0.3; 424 c_g_ideal[3] = 1.47e-15; 425 c_fringe[3] = 0.08e-15; 426 c_junc[3] = 1e-15; 427 I_on_n[3] = 321.6e-6; 428 I_on_p[3] = 203.3e-6; 429 nmos_effective_resistance_multiplier = 1.65; 430 n_to_p_eff_curr_drv_ratio[3] = 1.95; 431 gmp_to_gmn_multiplier[3] = 0.90; 432 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 433 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 434 long_channel_leakage_reduction[3] = 1; 435 I_off_n[3][0] = 1.42e-11; 436 I_off_n[3][10] = 2.25e-11; 437 I_off_n[3][20] = 3.46e-11; 438 I_off_n[3][30] = 5.18e-11; 439 I_off_n[3][40] = 7.58e-11; 440 I_off_n[3][50] = 1.08e-10; 441 I_off_n[3][60] = 1.51e-10; 442 I_off_n[3][70] = 2.02e-10; 443 I_off_n[3][80] = 2.57e-10; 444 I_off_n[3][90] = 3.14e-10; 445 I_off_n[3][100] = 3.85e-10; 446 } else if (ram_cell_tech_type == comm_dram) { 447 //COMM-DRAM cell access transistor technology parameters 448 curr_vdd_dram_cell = 1.6; 449 Lphy[3] = 0.09; 450 Lelec[3] = 0.0576; 451 curr_v_th_dram_access_transistor = 1; 452 width_dram_access_transistor = 0.09; 453 curr_I_on_dram_cell = 20e-6; 454 curr_I_off_dram_cell_worst_case_length_temp = 1e-15; 455 curr_Wmemcella_dram = width_dram_access_transistor; 456 curr_Wmemcellpmos_dram = 0; 457 curr_Wmemcellnmos_dram = 0; 458 curr_area_cell_dram = 6 * 0.09 * 0.09; 459 curr_asp_ratio_cell_dram = 1.5; 460 curr_c_dram_cell = 30e-15; 461 462 //COMM-DRAM wordline transistor parameters 463 curr_vpp = 3.7; 464 t_ox[3] = 5.5e-3; 465 v_th[3] = 1.0; 466 c_ox[3] = 5.65e-15; 467 mobility_eff[3] = 302.2 * (1e-2 * 1e6 * 1e-2 * 1e6); 468 Vdsat[3] = 0.32; 469 c_g_ideal[3] = 5.08e-16; 470 c_fringe[3] = 0.08e-15; 471 c_junc[3] = 1e-15; 472 I_on_n[3] = 1094.3e-6; 473 I_on_p[3] = I_on_n[3] / 2; 474 nmos_effective_resistance_multiplier = 1.62; 475 n_to_p_eff_curr_drv_ratio[3] = 2.05; 476 gmp_to_gmn_multiplier[3] = 0.90; 477 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 478 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 479 long_channel_leakage_reduction[3] = 1; 480 I_off_n[3][0] = 5.80e-15; 481 I_off_n[3][10] = 1.21e-14; 482 I_off_n[3][20] = 2.42e-14; 483 I_off_n[3][30] = 4.65e-14; 484 I_off_n[3][40] = 8.60e-14; 485 I_off_n[3][50] = 1.54e-13; 486 I_off_n[3][60] = 2.66e-13; 487 I_off_n[3][70] = 4.45e-13; 488 I_off_n[3][80] = 7.17e-13; 489 I_off_n[3][90] = 1.11e-12; 490 I_off_n[3][100] = 1.67e-12; 491 } 492 493 //SRAM cell properties 494 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 495 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 496 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 497 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 498 curr_asp_ratio_cell_sram = 1.46; 499 //CAM cell properties //TODO: data need to be revisited 500 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 501 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 502 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 503 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um;//360 504 curr_asp_ratio_cell_cam = 2.92;//2.5 505 //Empirical undifferetiated core/FU coefficient 506 curr_logic_scaling_co_eff = 1; 507 curr_core_tx_density = 1.25 * 0.7 * 0.7; 508 curr_sckt_co_eff = 1.1539; 509 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 510 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 511 512 513 } 514 515 if (tech == 65) { 516 //65nm technology-node. Corresponds to year 2007 in ITRS 517 //ITRS HP device type 518 SENSE_AMP_D = .2e-9; // s 519 SENSE_AMP_P = 5.7e-15; // J 520 vdd[0] = 1.1; 521 Lphy[0] = 0.025; 522 Lelec[0] = 0.019; 523 t_ox[0] = 1.1e-3; 524 v_th[0] = .19491; 525 c_ox[0] = 1.88e-14; 526 mobility_eff[0] = 436.24 * (1e-2 * 1e6 * 1e-2 * 1e6); 527 Vdsat[0] = 7.71e-2; 528 c_g_ideal[0] = 4.69e-16; 529 c_fringe[0] = 0.077e-15; 530 c_junc[0] = 1e-15; 531 I_on_n[0] = 1197.2e-6; 532 I_on_p[0] = 870.8e-6; 533 nmos_effective_resistance_multiplier = 1.50; 534 n_to_p_eff_curr_drv_ratio[0] = 2.41; 535 gmp_to_gmn_multiplier[0] = 1.38; 536 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0]; 537 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; 538 long_channel_leakage_reduction[0] = 1 / 3.74; 539 //Using MASTAR, @380K, increase Lgate until Ion reduces to 90% or Lgate increase by 10%, whichever comes first 540 //Ioff(Lgate normal)/Ioff(Lgate long)= 3.74. 541 I_off_n[0][0] = 1.96e-7; 542 I_off_n[0][10] = 2.29e-7; 543 I_off_n[0][20] = 2.66e-7; 544 I_off_n[0][30] = 3.05e-7; 545 I_off_n[0][40] = 3.49e-7; 546 I_off_n[0][50] = 3.95e-7; 547 I_off_n[0][60] = 4.45e-7; 548 I_off_n[0][70] = 4.97e-7; 549 I_off_n[0][80] = 5.48e-7; 550 I_off_n[0][90] = 5.94e-7; 551 I_off_n[0][100] = 6.3e-7; 552 I_g_on_n[0][0] = 4.09e-8;//A/micron 553 I_g_on_n[0][10] = 4.09e-8; 554 I_g_on_n[0][20] = 4.09e-8; 555 I_g_on_n[0][30] = 4.09e-8; 556 I_g_on_n[0][40] = 4.09e-8; 557 I_g_on_n[0][50] = 4.09e-8; 558 I_g_on_n[0][60] = 4.09e-8; 559 I_g_on_n[0][70] = 4.09e-8; 560 I_g_on_n[0][80] = 4.09e-8; 561 I_g_on_n[0][90] = 4.09e-8; 562 I_g_on_n[0][100] = 4.09e-8; 563 564 //ITRS LSTP device type 565 vdd[1] = 1.2; 566 Lphy[1] = 0.045; 567 Lelec[1] = 0.0298; 568 t_ox[1] = 1.9e-3; 569 v_th[1] = 0.52354; 570 c_ox[1] = 1.36e-14; 571 mobility_eff[1] = 341.21 * (1e-2 * 1e6 * 1e-2 * 1e6); 572 Vdsat[1] = 0.128; 573 c_g_ideal[1] = 6.14e-16; 574 c_fringe[1] = 0.08e-15; 575 c_junc[1] = 1e-15; 576 I_on_n[1] = 519.2e-6; 577 I_on_p[1] = 266e-6; 578 nmos_effective_resistance_multiplier = 1.96; 579 n_to_p_eff_curr_drv_ratio[1] = 2.23; 580 gmp_to_gmn_multiplier[1] = 0.99; 581 Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1]; 582 Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; 583 long_channel_leakage_reduction[1] = 1 / 2.82; 584 I_off_n[1][0] = 9.12e-12; 585 I_off_n[1][10] = 1.49e-11; 586 I_off_n[1][20] = 2.36e-11; 587 I_off_n[1][30] = 3.64e-11; 588 I_off_n[1][40] = 5.48e-11; 589 I_off_n[1][50] = 8.05e-11; 590 I_off_n[1][60] = 1.15e-10; 591 I_off_n[1][70] = 1.59e-10; 592 I_off_n[1][80] = 2.1e-10; 593 I_off_n[1][90] = 2.62e-10; 594 I_off_n[1][100] = 3.21e-10; 595 596 I_g_on_n[1][0] = 1.09e-10;//A/micron 597 I_g_on_n[1][10] = 1.09e-10; 598 I_g_on_n[1][20] = 1.09e-10; 599 I_g_on_n[1][30] = 1.09e-10; 600 I_g_on_n[1][40] = 1.09e-10; 601 I_g_on_n[1][50] = 1.09e-10; 602 I_g_on_n[1][60] = 1.09e-10; 603 I_g_on_n[1][70] = 1.09e-10; 604 I_g_on_n[1][80] = 1.09e-10; 605 I_g_on_n[1][90] = 1.09e-10; 606 I_g_on_n[1][100] = 1.09e-10; 607 608 //ITRS LOP device type 609 vdd[2] = 0.8; 610 Lphy[2] = 0.032; 611 Lelec[2] = 0.0216; 612 t_ox[2] = 1.2e-3; 613 v_th[2] = 0.28512; 614 c_ox[2] = 1.87e-14; 615 mobility_eff[2] = 495.19 * (1e-2 * 1e6 * 1e-2 * 1e6); 616 Vdsat[2] = 0.292; 617 c_g_ideal[2] = 6e-16; 618 c_fringe[2] = 0.08e-15; 619 c_junc[2] = 1e-15; 620 I_on_n[2] = 573.1e-6; 621 I_on_p[2] = 340.6e-6; 622 nmos_effective_resistance_multiplier = 1.82; 623 n_to_p_eff_curr_drv_ratio[2] = 2.28; 624 gmp_to_gmn_multiplier[2] = 1.11; 625 Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2]; 626 Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; 627 long_channel_leakage_reduction[2] = 1 / 2.05; 628 I_off_n[2][0] = 4.9e-9; 629 I_off_n[2][10] = 6.49e-9; 630 I_off_n[2][20] = 8.45e-9; 631 I_off_n[2][30] = 1.08e-8; 632 I_off_n[2][40] = 1.37e-8; 633 I_off_n[2][50] = 1.71e-8; 634 I_off_n[2][60] = 2.09e-8; 635 I_off_n[2][70] = 2.48e-8; 636 I_off_n[2][80] = 2.84e-8; 637 I_off_n[2][90] = 3.13e-8; 638 I_off_n[2][100] = 3.42e-8; 639 640 I_g_on_n[2][0] = 9.61e-9;//A/micron 641 I_g_on_n[2][10] = 9.61e-9; 642 I_g_on_n[2][20] = 9.61e-9; 643 I_g_on_n[2][30] = 9.61e-9; 644 I_g_on_n[2][40] = 9.61e-9; 645 I_g_on_n[2][50] = 9.61e-9; 646 I_g_on_n[2][60] = 9.61e-9; 647 I_g_on_n[2][70] = 9.61e-9; 648 I_g_on_n[2][80] = 9.61e-9; 649 I_g_on_n[2][90] = 9.61e-9; 650 I_g_on_n[2][100] = 9.61e-9; 651 652 if (ram_cell_tech_type == lp_dram) { 653 //LP-DRAM cell access transistor technology parameters 654 curr_vdd_dram_cell = 1.2; 655 Lphy[3] = 0.12; 656 Lelec[3] = 0.0756; 657 curr_v_th_dram_access_transistor = 0.43806; 658 width_dram_access_transistor = 0.09; 659 curr_I_on_dram_cell = 36e-6; 660 curr_I_off_dram_cell_worst_case_length_temp = 19.6e-12; 661 curr_Wmemcella_dram = width_dram_access_transistor; 662 curr_Wmemcellpmos_dram = 0; 663 curr_Wmemcellnmos_dram = 0; 664 curr_area_cell_dram = 0.11; 665 curr_asp_ratio_cell_dram = 1.46; 666 curr_c_dram_cell = 20e-15; 667 668 //LP-DRAM wordline transistor parameters 669 curr_vpp = 1.6; 670 t_ox[3] = 2.2e-3; 671 v_th[3] = 0.43806; 672 c_ox[3] = 1.22e-14; 673 mobility_eff[3] = 328.32 * (1e-2 * 1e6 * 1e-2 * 1e6); 674 Vdsat[3] = 0.43806; 675 c_g_ideal[3] = 1.46e-15; 676 c_fringe[3] = 0.08e-15; 677 c_junc[3] = 1e-15 ; 678 I_on_n[3] = 399.8e-6; 679 I_on_p[3] = 243.4e-6; 680 nmos_effective_resistance_multiplier = 1.65; 681 n_to_p_eff_curr_drv_ratio[3] = 2.05; 682 gmp_to_gmn_multiplier[3] = 0.90; 683 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 684 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 685 long_channel_leakage_reduction[3] = 1; 686 I_off_n[3][0] = 2.23e-11; 687 I_off_n[3][10] = 3.46e-11; 688 I_off_n[3][20] = 5.24e-11; 689 I_off_n[3][30] = 7.75e-11; 690 I_off_n[3][40] = 1.12e-10; 691 I_off_n[3][50] = 1.58e-10; 692 I_off_n[3][60] = 2.18e-10; 693 I_off_n[3][70] = 2.88e-10; 694 I_off_n[3][80] = 3.63e-10; 695 I_off_n[3][90] = 4.41e-10; 696 I_off_n[3][100] = 5.36e-10; 697 } else if (ram_cell_tech_type == comm_dram) { 698 //COMM-DRAM cell access transistor technology parameters 699 curr_vdd_dram_cell = 1.3; 700 Lphy[3] = 0.065; 701 Lelec[3] = 0.0426; 702 curr_v_th_dram_access_transistor = 1; 703 width_dram_access_transistor = 0.065; 704 curr_I_on_dram_cell = 20e-6; 705 curr_I_off_dram_cell_worst_case_length_temp = 1e-15; 706 curr_Wmemcella_dram = width_dram_access_transistor; 707 curr_Wmemcellpmos_dram = 0; 708 curr_Wmemcellnmos_dram = 0; 709 curr_area_cell_dram = 6 * 0.065 * 0.065; 710 curr_asp_ratio_cell_dram = 1.5; 711 curr_c_dram_cell = 30e-15; 712 713 //COMM-DRAM wordline transistor parameters 714 curr_vpp = 3.3; 715 t_ox[3] = 5e-3; 716 v_th[3] = 1.0; 717 c_ox[3] = 6.16e-15; 718 mobility_eff[3] = 303.44 * (1e-2 * 1e6 * 1e-2 * 1e6); 719 Vdsat[3] = 0.385; 720 c_g_ideal[3] = 4e-16; 721 c_fringe[3] = 0.08e-15; 722 c_junc[3] = 1e-15 ; 723 I_on_n[3] = 1031e-6; 724 I_on_p[3] = I_on_n[3] / 2; 725 nmos_effective_resistance_multiplier = 1.69; 726 n_to_p_eff_curr_drv_ratio[3] = 2.39; 727 gmp_to_gmn_multiplier[3] = 0.90; 728 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 729 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 730 long_channel_leakage_reduction[3] = 1; 731 I_off_n[3][0] = 1.80e-14; 732 I_off_n[3][10] = 3.64e-14; 733 I_off_n[3][20] = 7.03e-14; 734 I_off_n[3][30] = 1.31e-13; 735 I_off_n[3][40] = 2.35e-13; 736 I_off_n[3][50] = 4.09e-13; 737 I_off_n[3][60] = 6.89e-13; 738 I_off_n[3][70] = 1.13e-12; 739 I_off_n[3][80] = 1.78e-12; 740 I_off_n[3][90] = 2.71e-12; 741 I_off_n[3][100] = 3.99e-12; 742 } 743 744 //SRAM cell properties 745 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 746 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 747 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 748 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 749 curr_asp_ratio_cell_sram = 1.46; 750 //CAM cell properties //TODO: data need to be revisited 751 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 752 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 753 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 754 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; 755 curr_asp_ratio_cell_cam = 2.92; 756 //Empirical undifferetiated core/FU coefficient 757 curr_logic_scaling_co_eff = 0.7; //Rather than scale proportionally to square of feature size, only scale linearly according to IBM cell processor 758 curr_core_tx_density = 1.25 * 0.7; 759 curr_sckt_co_eff = 1.1359; 760 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 761 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 762 } 763 764 if (tech == 45) { 765 //45nm technology-node. Corresponds to year 2010 in ITRS 766 //ITRS HP device type 767 SENSE_AMP_D = .04e-9; // s 768 SENSE_AMP_P = 2.7e-15; // J 769 vdd[0] = 1.0; 770 Lphy[0] = 0.018; 771 Lelec[0] = 0.01345; 772 t_ox[0] = 0.65e-3; 773 v_th[0] = .18035; 774 c_ox[0] = 3.77e-14; 775 mobility_eff[0] = 266.68 * (1e-2 * 1e6 * 1e-2 * 1e6); 776 Vdsat[0] = 9.38E-2; 777 c_g_ideal[0] = 6.78e-16; 778 c_fringe[0] = 0.05e-15; 779 c_junc[0] = 1e-15; 780 I_on_n[0] = 2046.6e-6; 781 //There are certain problems with the ITRS PMOS numbers in MASTAR for 45nm. So we are using 65nm values of 782 //n_to_p_eff_curr_drv_ratio and gmp_to_gmn_multiplier for 45nm 783 I_on_p[0] = I_on_n[0] / 2;//This value is fixed arbitrarily but I_on_p is not being used in CACTI 784 nmos_effective_resistance_multiplier = 1.51; 785 n_to_p_eff_curr_drv_ratio[0] = 2.41; 786 gmp_to_gmn_multiplier[0] = 1.38; 787 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0]; 788 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0]; 789 //Using MASTAR, @380K, increase Lgate until Ion reduces to 90%, 790 //Ioff(Lgate normal)/Ioff(Lgate long)= 3.74 791 long_channel_leakage_reduction[0] = 1 / 3.546; 792 I_off_n[0][0] = 2.8e-7; 793 I_off_n[0][10] = 3.28e-7; 794 I_off_n[0][20] = 3.81e-7; 795 I_off_n[0][30] = 4.39e-7; 796 I_off_n[0][40] = 5.02e-7; 797 I_off_n[0][50] = 5.69e-7; 798 I_off_n[0][60] = 6.42e-7; 799 I_off_n[0][70] = 7.2e-7; 800 I_off_n[0][80] = 8.03e-7; 801 I_off_n[0][90] = 8.91e-7; 802 I_off_n[0][100] = 9.84e-7; 803 804 I_g_on_n[0][0] = 3.59e-8;//A/micron 805 I_g_on_n[0][10] = 3.59e-8; 806 I_g_on_n[0][20] = 3.59e-8; 807 I_g_on_n[0][30] = 3.59e-8; 808 I_g_on_n[0][40] = 3.59e-8; 809 I_g_on_n[0][50] = 3.59e-8; 810 I_g_on_n[0][60] = 3.59e-8; 811 I_g_on_n[0][70] = 3.59e-8; 812 I_g_on_n[0][80] = 3.59e-8; 813 I_g_on_n[0][90] = 3.59e-8; 814 I_g_on_n[0][100] = 3.59e-8; 815 816 //ITRS LSTP device type 817 vdd[1] = 1.1; 818 Lphy[1] = 0.028; 819 Lelec[1] = 0.0212; 820 t_ox[1] = 1.4e-3; 821 v_th[1] = 0.50245; 822 c_ox[1] = 2.01e-14; 823 mobility_eff[1] = 363.96 * (1e-2 * 1e6 * 1e-2 * 1e6); 824 Vdsat[1] = 9.12e-2; 825 c_g_ideal[1] = 5.18e-16; 826 c_fringe[1] = 0.08e-15; 827 c_junc[1] = 1e-15; 828 I_on_n[1] = 666.2e-6; 829 I_on_p[1] = I_on_n[1] / 2; 830 nmos_effective_resistance_multiplier = 1.99; 831 n_to_p_eff_curr_drv_ratio[1] = 2.23; 832 gmp_to_gmn_multiplier[1] = 0.99; 833 Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1]; 834 Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; 835 long_channel_leakage_reduction[1] = 1 / 2.08; 836 I_off_n[1][0] = 1.01e-11; 837 I_off_n[1][10] = 1.65e-11; 838 I_off_n[1][20] = 2.62e-11; 839 I_off_n[1][30] = 4.06e-11; 840 I_off_n[1][40] = 6.12e-11; 841 I_off_n[1][50] = 9.02e-11; 842 I_off_n[1][60] = 1.3e-10; 843 I_off_n[1][70] = 1.83e-10; 844 I_off_n[1][80] = 2.51e-10; 845 I_off_n[1][90] = 3.29e-10; 846 I_off_n[1][100] = 4.1e-10; 847 848 I_g_on_n[1][0] = 9.47e-12;//A/micron 849 I_g_on_n[1][10] = 9.47e-12; 850 I_g_on_n[1][20] = 9.47e-12; 851 I_g_on_n[1][30] = 9.47e-12; 852 I_g_on_n[1][40] = 9.47e-12; 853 I_g_on_n[1][50] = 9.47e-12; 854 I_g_on_n[1][60] = 9.47e-12; 855 I_g_on_n[1][70] = 9.47e-12; 856 I_g_on_n[1][80] = 9.47e-12; 857 I_g_on_n[1][90] = 9.47e-12; 858 I_g_on_n[1][100] = 9.47e-12; 859 860 //ITRS LOP device type 861 vdd[2] = 0.7; 862 Lphy[2] = 0.022; 863 Lelec[2] = 0.016; 864 t_ox[2] = 0.9e-3; 865 v_th[2] = 0.22599; 866 c_ox[2] = 2.82e-14;//F/micron2 867 mobility_eff[2] = 508.9 * (1e-2 * 1e6 * 1e-2 * 1e6); 868 Vdsat[2] = 5.71e-2; 869 c_g_ideal[2] = 6.2e-16; 870 c_fringe[2] = 0.073e-15; 871 c_junc[2] = 1e-15; 872 I_on_n[2] = 748.9e-6; 873 I_on_p[2] = I_on_n[2] / 2; 874 nmos_effective_resistance_multiplier = 1.76; 875 n_to_p_eff_curr_drv_ratio[2] = 2.28; 876 gmp_to_gmn_multiplier[2] = 1.11; 877 Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2]; 878 Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; 879 long_channel_leakage_reduction[2] = 1 / 1.92; 880 I_off_n[2][0] = 4.03e-9; 881 I_off_n[2][10] = 5.02e-9; 882 I_off_n[2][20] = 6.18e-9; 883 I_off_n[2][30] = 7.51e-9; 884 I_off_n[2][40] = 9.04e-9; 885 I_off_n[2][50] = 1.08e-8; 886 I_off_n[2][60] = 1.27e-8; 887 I_off_n[2][70] = 1.47e-8; 888 I_off_n[2][80] = 1.66e-8; 889 I_off_n[2][90] = 1.84e-8; 890 I_off_n[2][100] = 2.03e-8; 891 892 I_g_on_n[2][0] = 3.24e-8;//A/micron 893 I_g_on_n[2][10] = 4.01e-8; 894 I_g_on_n[2][20] = 4.90e-8; 895 I_g_on_n[2][30] = 5.92e-8; 896 I_g_on_n[2][40] = 7.08e-8; 897 I_g_on_n[2][50] = 8.38e-8; 898 I_g_on_n[2][60] = 9.82e-8; 899 I_g_on_n[2][70] = 1.14e-7; 900 I_g_on_n[2][80] = 1.29e-7; 901 I_g_on_n[2][90] = 1.43e-7; 902 I_g_on_n[2][100] = 1.54e-7; 903 904 if (ram_cell_tech_type == lp_dram) { 905 //LP-DRAM cell access transistor technology parameters 906 curr_vdd_dram_cell = 1.1; 907 Lphy[3] = 0.078; 908 Lelec[3] = 0.0504;// Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors. 909 curr_v_th_dram_access_transistor = 0.44559; 910 width_dram_access_transistor = 0.079; 911 curr_I_on_dram_cell = 36e-6;//A 912 curr_I_off_dram_cell_worst_case_length_temp = 19.5e-12; 913 curr_Wmemcella_dram = width_dram_access_transistor; 914 curr_Wmemcellpmos_dram = 0; 915 curr_Wmemcellnmos_dram = 0; 916 curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0; 917 curr_asp_ratio_cell_dram = 1.46; 918 curr_c_dram_cell = 20e-15; 919 920 //LP-DRAM wordline transistor parameters 921 curr_vpp = 1.5; 922 t_ox[3] = 2.1e-3; 923 v_th[3] = 0.44559; 924 c_ox[3] = 1.41e-14; 925 mobility_eff[3] = 426.30 * (1e-2 * 1e6 * 1e-2 * 1e6); 926 Vdsat[3] = 0.181; 927 c_g_ideal[3] = 1.10e-15; 928 c_fringe[3] = 0.08e-15; 929 c_junc[3] = 1e-15; 930 I_on_n[3] = 456e-6; 931 I_on_p[3] = I_on_n[3] / 2; 932 nmos_effective_resistance_multiplier = 1.65; 933 n_to_p_eff_curr_drv_ratio[3] = 2.05; 934 gmp_to_gmn_multiplier[3] = 0.90; 935 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 936 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 937 long_channel_leakage_reduction[3] = 1; 938 I_off_n[3][0] = 2.54e-11; 939 I_off_n[3][10] = 3.94e-11; 940 I_off_n[3][20] = 5.95e-11; 941 I_off_n[3][30] = 8.79e-11; 942 I_off_n[3][40] = 1.27e-10; 943 I_off_n[3][50] = 1.79e-10; 944 I_off_n[3][60] = 2.47e-10; 945 I_off_n[3][70] = 3.31e-10; 946 I_off_n[3][80] = 4.26e-10; 947 I_off_n[3][90] = 5.27e-10; 948 I_off_n[3][100] = 6.46e-10; 949 } else if (ram_cell_tech_type == comm_dram) { 950 //COMM-DRAM cell access transistor technology parameters 951 curr_vdd_dram_cell = 1.1; 952 Lphy[3] = 0.045; 953 Lelec[3] = 0.0298; 954 curr_v_th_dram_access_transistor = 1; 955 width_dram_access_transistor = 0.045; 956 curr_I_on_dram_cell = 20e-6;//A 957 curr_I_off_dram_cell_worst_case_length_temp = 1e-15; 958 curr_Wmemcella_dram = width_dram_access_transistor; 959 curr_Wmemcellpmos_dram = 0; 960 curr_Wmemcellnmos_dram = 0; 961 curr_area_cell_dram = 6 * 0.045 * 0.045; 962 curr_asp_ratio_cell_dram = 1.5; 963 curr_c_dram_cell = 30e-15; 964 965 //COMM-DRAM wordline transistor parameters 966 curr_vpp = 2.7; 967 t_ox[3] = 4e-3; 968 v_th[3] = 1.0; 969 c_ox[3] = 7.98e-15; 970 mobility_eff[3] = 368.58 * (1e-2 * 1e6 * 1e-2 * 1e6); 971 Vdsat[3] = 0.147; 972 c_g_ideal[3] = 3.59e-16; 973 c_fringe[3] = 0.08e-15; 974 c_junc[3] = 1e-15; 975 I_on_n[3] = 999.4e-6; 976 I_on_p[3] = I_on_n[3] / 2; 977 nmos_effective_resistance_multiplier = 1.69; 978 n_to_p_eff_curr_drv_ratio[3] = 1.95; 979 gmp_to_gmn_multiplier[3] = 0.90; 980 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 981 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 982 long_channel_leakage_reduction[3] = 1; 983 I_off_n[3][0] = 1.31e-14; 984 I_off_n[3][10] = 2.68e-14; 985 I_off_n[3][20] = 5.25e-14; 986 I_off_n[3][30] = 9.88e-14; 987 I_off_n[3][40] = 1.79e-13; 988 I_off_n[3][50] = 3.15e-13; 989 I_off_n[3][60] = 5.36e-13; 990 I_off_n[3][70] = 8.86e-13; 991 I_off_n[3][80] = 1.42e-12; 992 I_off_n[3][90] = 2.20e-12; 993 I_off_n[3][100] = 3.29e-12; 994 } 995 996 997 //SRAM cell properties 998 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 999 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 1000 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 1001 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 1002 curr_asp_ratio_cell_sram = 1.46; 1003 //CAM cell properties //TODO: data need to be revisited 1004 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 1005 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 1006 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 1007 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; 1008 curr_asp_ratio_cell_cam = 2.92; 1009 //Empirical undifferetiated core/FU coefficient 1010 curr_logic_scaling_co_eff = 0.7 * 0.7; 1011 curr_core_tx_density = 1.25; 1012 curr_sckt_co_eff = 1.1387; 1013 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 1014 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 1015 } 1016 1017 if (tech == 32) { 1018 SENSE_AMP_D = .03e-9; // s 1019 SENSE_AMP_P = 2.16e-15; // J 1020 //For 2013, MPU/ASIC stagger-contacted M1 half-pitch is 32 nm (so this is 32 nm 1021 //technology i.e. FEATURESIZE = 0.032). Using the SOI process numbers for 1022 //HP and LSTP. 1023 vdd[0] = 0.9; 1024 Lphy[0] = 0.013; 1025 Lelec[0] = 0.01013; 1026 t_ox[0] = 0.5e-3; 1027 v_th[0] = 0.21835; 1028 c_ox[0] = 4.11e-14; 1029 mobility_eff[0] = 361.84 * (1e-2 * 1e6 * 1e-2 * 1e6); 1030 Vdsat[0] = 5.09E-2; 1031 c_g_ideal[0] = 5.34e-16; 1032 c_fringe[0] = 0.04e-15; 1033 c_junc[0] = 1e-15; 1034 I_on_n[0] = 2211.7e-6; 1035 I_on_p[0] = I_on_n[0] / 2; 1036 nmos_effective_resistance_multiplier = 1.49; 1037 n_to_p_eff_curr_drv_ratio[0] = 2.41; 1038 gmp_to_gmn_multiplier[0] = 1.38; 1039 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron 1040 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron 1041 long_channel_leakage_reduction[0] = 1 / 3.706; 1042 //Using MASTAR, @300K (380K does not work in MASTAR), increase Lgate until Ion reduces to 95% or Lgate increase by 5% (DG device can only increase by 5%), 1043 //whichever comes first 1044 I_off_n[0][0] = 1.52e-7; 1045 I_off_n[0][10] = 1.55e-7; 1046 I_off_n[0][20] = 1.59e-7; 1047 I_off_n[0][30] = 1.68e-7; 1048 I_off_n[0][40] = 1.90e-7; 1049 I_off_n[0][50] = 2.69e-7; 1050 I_off_n[0][60] = 5.32e-7; 1051 I_off_n[0][70] = 1.02e-6; 1052 I_off_n[0][80] = 1.62e-6; 1053 I_off_n[0][90] = 2.73e-6; 1054 I_off_n[0][100] = 6.1e-6; 1055 1056 I_g_on_n[0][0] = 6.55e-8;//A/micron 1057 I_g_on_n[0][10] = 6.55e-8; 1058 I_g_on_n[0][20] = 6.55e-8; 1059 I_g_on_n[0][30] = 6.55e-8; 1060 I_g_on_n[0][40] = 6.55e-8; 1061 I_g_on_n[0][50] = 6.55e-8; 1062 I_g_on_n[0][60] = 6.55e-8; 1063 I_g_on_n[0][70] = 6.55e-8; 1064 I_g_on_n[0][80] = 6.55e-8; 1065 I_g_on_n[0][90] = 6.55e-8; 1066 I_g_on_n[0][100] = 6.55e-8; 1067 1068 //LSTP device type 1069 vdd[1] = 1; 1070 Lphy[1] = 0.020; 1071 Lelec[1] = 0.0173; 1072 t_ox[1] = 1.2e-3; 1073 v_th[1] = 0.513; 1074 c_ox[1] = 2.29e-14; 1075 mobility_eff[1] = 347.46 * (1e-2 * 1e6 * 1e-2 * 1e6); 1076 Vdsat[1] = 8.64e-2; 1077 c_g_ideal[1] = 4.58e-16; 1078 c_fringe[1] = 0.053e-15; 1079 c_junc[1] = 1e-15; 1080 I_on_n[1] = 683.6e-6; 1081 I_on_p[1] = I_on_n[1] / 2; 1082 nmos_effective_resistance_multiplier = 1.99; 1083 n_to_p_eff_curr_drv_ratio[1] = 2.23; 1084 gmp_to_gmn_multiplier[1] = 0.99; 1085 Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1]; 1086 Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1]; 1087 long_channel_leakage_reduction[1] = 1 / 1.93; 1088 I_off_n[1][0] = 2.06e-11; 1089 I_off_n[1][10] = 3.30e-11; 1090 I_off_n[1][20] = 5.15e-11; 1091 I_off_n[1][30] = 7.83e-11; 1092 I_off_n[1][40] = 1.16e-10; 1093 I_off_n[1][50] = 1.69e-10; 1094 I_off_n[1][60] = 2.40e-10; 1095 I_off_n[1][70] = 3.34e-10; 1096 I_off_n[1][80] = 4.54e-10; 1097 I_off_n[1][90] = 5.96e-10; 1098 I_off_n[1][100] = 7.44e-10; 1099 1100 I_g_on_n[1][0] = 3.73e-11;//A/micron 1101 I_g_on_n[1][10] = 3.73e-11; 1102 I_g_on_n[1][20] = 3.73e-11; 1103 I_g_on_n[1][30] = 3.73e-11; 1104 I_g_on_n[1][40] = 3.73e-11; 1105 I_g_on_n[1][50] = 3.73e-11; 1106 I_g_on_n[1][60] = 3.73e-11; 1107 I_g_on_n[1][70] = 3.73e-11; 1108 I_g_on_n[1][80] = 3.73e-11; 1109 I_g_on_n[1][90] = 3.73e-11; 1110 I_g_on_n[1][100] = 3.73e-11; 1111 1112 //LOP device type 1113 vdd[2] = 0.6; 1114 Lphy[2] = 0.016; 1115 Lelec[2] = 0.01232; 1116 t_ox[2] = 0.9e-3; 1117 v_th[2] = 0.24227; 1118 c_ox[2] = 2.84e-14; 1119 mobility_eff[2] = 513.52 * (1e-2 * 1e6 * 1e-2 * 1e6); 1120 Vdsat[2] = 4.64e-2; 1121 c_g_ideal[2] = 4.54e-16; 1122 c_fringe[2] = 0.057e-15; 1123 c_junc[2] = 1e-15; 1124 I_on_n[2] = 827.8e-6; 1125 I_on_p[2] = I_on_n[2] / 2; 1126 nmos_effective_resistance_multiplier = 1.73; 1127 n_to_p_eff_curr_drv_ratio[2] = 2.28; 1128 gmp_to_gmn_multiplier[2] = 1.11; 1129 Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2]; 1130 Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2]; 1131 long_channel_leakage_reduction[2] = 1 / 1.89; 1132 I_off_n[2][0] = 5.94e-8; 1133 I_off_n[2][10] = 7.23e-8; 1134 I_off_n[2][20] = 8.7e-8; 1135 I_off_n[2][30] = 1.04e-7; 1136 I_off_n[2][40] = 1.22e-7; 1137 I_off_n[2][50] = 1.43e-7; 1138 I_off_n[2][60] = 1.65e-7; 1139 I_off_n[2][70] = 1.90e-7; 1140 I_off_n[2][80] = 2.15e-7; 1141 I_off_n[2][90] = 2.39e-7; 1142 I_off_n[2][100] = 2.63e-7; 1143 1144 I_g_on_n[2][0] = 2.93e-9;//A/micron 1145 I_g_on_n[2][10] = 2.93e-9; 1146 I_g_on_n[2][20] = 2.93e-9; 1147 I_g_on_n[2][30] = 2.93e-9; 1148 I_g_on_n[2][40] = 2.93e-9; 1149 I_g_on_n[2][50] = 2.93e-9; 1150 I_g_on_n[2][60] = 2.93e-9; 1151 I_g_on_n[2][70] = 2.93e-9; 1152 I_g_on_n[2][80] = 2.93e-9; 1153 I_g_on_n[2][90] = 2.93e-9; 1154 I_g_on_n[2][100] = 2.93e-9; 1155 1156 if (ram_cell_tech_type == lp_dram) { 1157 //LP-DRAM cell access transistor technology parameters 1158 curr_vdd_dram_cell = 1.0; 1159 Lphy[3] = 0.056; 1160 Lelec[3] = 0.0419;//Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors. 1161 curr_v_th_dram_access_transistor = 0.44129; 1162 width_dram_access_transistor = 0.056; 1163 curr_I_on_dram_cell = 36e-6; 1164 curr_I_off_dram_cell_worst_case_length_temp = 18.9e-12; 1165 curr_Wmemcella_dram = width_dram_access_transistor; 1166 curr_Wmemcellpmos_dram = 0; 1167 curr_Wmemcellnmos_dram = 0; 1168 curr_area_cell_dram = width_dram_access_transistor * Lphy[3] * 10.0; 1169 curr_asp_ratio_cell_dram = 1.46; 1170 curr_c_dram_cell = 20e-15; 1171 1172 //LP-DRAM wordline transistor parameters 1173 curr_vpp = 1.5; 1174 t_ox[3] = 2e-3; 1175 v_th[3] = 0.44467; 1176 c_ox[3] = 1.48e-14; 1177 mobility_eff[3] = 408.12 * (1e-2 * 1e6 * 1e-2 * 1e6); 1178 Vdsat[3] = 0.174; 1179 c_g_ideal[3] = 7.45e-16; 1180 c_fringe[3] = 0.053e-15; 1181 c_junc[3] = 1e-15; 1182 I_on_n[3] = 1055.4e-6; 1183 I_on_p[3] = I_on_n[3] / 2; 1184 nmos_effective_resistance_multiplier = 1.65; 1185 n_to_p_eff_curr_drv_ratio[3] = 2.05; 1186 gmp_to_gmn_multiplier[3] = 0.90; 1187 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 1188 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 1189 long_channel_leakage_reduction[3] = 1; 1190 I_off_n[3][0] = 3.57e-11; 1191 I_off_n[3][10] = 5.51e-11; 1192 I_off_n[3][20] = 8.27e-11; 1193 I_off_n[3][30] = 1.21e-10; 1194 I_off_n[3][40] = 1.74e-10; 1195 I_off_n[3][50] = 2.45e-10; 1196 I_off_n[3][60] = 3.38e-10; 1197 I_off_n[3][70] = 4.53e-10; 1198 I_off_n[3][80] = 5.87e-10; 1199 I_off_n[3][90] = 7.29e-10; 1200 I_off_n[3][100] = 8.87e-10; 1201 } else if (ram_cell_tech_type == comm_dram) { 1202 //COMM-DRAM cell access transistor technology parameters 1203 curr_vdd_dram_cell = 1.0; 1204 Lphy[3] = 0.032; 1205 Lelec[3] = 0.0205;//Assume Lelec is 30% lesser than Lphy for DRAM access and wordline transistors. 1206 curr_v_th_dram_access_transistor = 1; 1207 width_dram_access_transistor = 0.032; 1208 curr_I_on_dram_cell = 20e-6; 1209 curr_I_off_dram_cell_worst_case_length_temp = 1e-15; 1210 curr_Wmemcella_dram = width_dram_access_transistor; 1211 curr_Wmemcellpmos_dram = 0; 1212 curr_Wmemcellnmos_dram = 0; 1213 curr_area_cell_dram = 6 * 0.032 * 0.032; 1214 curr_asp_ratio_cell_dram = 1.5; 1215 curr_c_dram_cell = 30e-15; 1216 1217 //COMM-DRAM wordline transistor parameters 1218 curr_vpp = 2.6; 1219 t_ox[3] = 4e-3; 1220 v_th[3] = 1.0; 1221 c_ox[3] = 7.99e-15; 1222 mobility_eff[3] = 380.76 * (1e-2 * 1e6 * 1e-2 * 1e6); 1223 Vdsat[3] = 0.129; 1224 c_g_ideal[3] = 2.56e-16; 1225 c_fringe[3] = 0.053e-15; 1226 c_junc[3] = 1e-15; 1227 I_on_n[3] = 1024.5e-6; 1228 I_on_p[3] = I_on_n[3] / 2; 1229 nmos_effective_resistance_multiplier = 1.69; 1230 n_to_p_eff_curr_drv_ratio[3] = 1.95; 1231 gmp_to_gmn_multiplier[3] = 0.90; 1232 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3]; 1233 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3]; 1234 long_channel_leakage_reduction[3] = 1; 1235 I_off_n[3][0] = 3.63e-14; 1236 I_off_n[3][10] = 7.18e-14; 1237 I_off_n[3][20] = 1.36e-13; 1238 I_off_n[3][30] = 2.49e-13; 1239 I_off_n[3][40] = 4.41e-13; 1240 I_off_n[3][50] = 7.55e-13; 1241 I_off_n[3][60] = 1.26e-12; 1242 I_off_n[3][70] = 2.03e-12; 1243 I_off_n[3][80] = 3.19e-12; 1244 I_off_n[3][90] = 4.87e-12; 1245 I_off_n[3][100] = 7.16e-12; 1246 } 1247 1248 //SRAM cell properties 1249 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 1250 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 1251 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 1252 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 1253 curr_asp_ratio_cell_sram = 1.46; 1254 //CAM cell properties //TODO: data need to be revisited 1255 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 1256 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 1257 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 1258 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; 1259 curr_asp_ratio_cell_cam = 2.92; 1260 //Empirical undifferetiated core/FU coefficient 1261 curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7; 1262 curr_core_tx_density = 1.25 / 0.7; 1263 curr_sckt_co_eff = 1.1111; 1264 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 1265 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 1266 } 1267 1268 if (tech == 22) { 1269 SENSE_AMP_D = .03e-9; // s 1270 SENSE_AMP_P = 2.16e-15; // J 1271 //For 2016, MPU/ASIC stagger-contacted M1 half-pitch is 22 nm (so this is 22 nm 1272 //technology i.e. FEATURESIZE = 0.022). Using the DG process numbers for HP. 1273 //22 nm HP 1274 vdd[0] = 0.8; 1275 Lphy[0] = 0.009;//Lphy is the physical gate-length. 1276 Lelec[0] = 0.00468;//Lelec is the electrical gate-length. 1277 t_ox[0] = 0.55e-3;//micron 1278 v_th[0] = 0.1395;//V 1279 c_ox[0] = 3.63e-14;//F/micron2 1280 mobility_eff[0] = 426.07 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 1281 Vdsat[0] = 2.33e-2; //V/micron 1282 c_g_ideal[0] = 3.27e-16;//F/micron 1283 c_fringe[0] = 0.06e-15;//F/micron 1284 c_junc[0] = 0;//F/micron2 1285 I_on_n[0] = 2626.4e-6;//A/micron 1286 I_on_p[0] = I_on_n[0] / 2;//A/micron //This value for I_on_p is not really used. 1287 nmos_effective_resistance_multiplier = 1.45; 1288 n_to_p_eff_curr_drv_ratio[0] = 2; //Wpmos/Wnmos = 2 in 2007 MASTAR. Look in 1289 //"Dynamic" tab of Device workspace. 1290 gmp_to_gmn_multiplier[0] = 1.38; //Just using the 32nm SOI value. 1291 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron 1292 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron 1293 long_channel_leakage_reduction[0] = 1 / 3.274; 1294 //From 22nm, leakage current are directly from ITRS report rather 1295 //than MASTAR, since MASTAR has serious bugs there. 1296 I_off_n[0][0] = 1.52e-7 / 1.5 * 1.2; 1297 I_off_n[0][10] = 1.55e-7 / 1.5 * 1.2; 1298 I_off_n[0][20] = 1.59e-7 / 1.5 * 1.2; 1299 I_off_n[0][30] = 1.68e-7 / 1.5 * 1.2; 1300 I_off_n[0][40] = 1.90e-7 / 1.5 * 1.2; 1301 I_off_n[0][50] = 2.69e-7 / 1.5 * 1.2; 1302 I_off_n[0][60] = 5.32e-7 / 1.5 * 1.2; 1303 I_off_n[0][70] = 1.02e-6 / 1.5 * 1.2; 1304 I_off_n[0][80] = 1.62e-6 / 1.5 * 1.2; 1305 I_off_n[0][90] = 2.73e-6 / 1.5 * 1.2; 1306 I_off_n[0][100] = 6.1e-6 / 1.5 * 1.2; 1307 //for 22nm DG HP 1308 I_g_on_n[0][0] = 1.81e-9;//A/micron 1309 I_g_on_n[0][10] = 1.81e-9; 1310 I_g_on_n[0][20] = 1.81e-9; 1311 I_g_on_n[0][30] = 1.81e-9; 1312 I_g_on_n[0][40] = 1.81e-9; 1313 I_g_on_n[0][50] = 1.81e-9; 1314 I_g_on_n[0][60] = 1.81e-9; 1315 I_g_on_n[0][70] = 1.81e-9; 1316 I_g_on_n[0][80] = 1.81e-9; 1317 I_g_on_n[0][90] = 1.81e-9; 1318 I_g_on_n[0][100] = 1.81e-9; 1319 1320 //22 nm LSTP DG 1321 vdd[1] = 0.8; 1322 Lphy[1] = 0.014; 1323 Lelec[1] = 0.008;//Lelec is the electrical gate-length. 1324 t_ox[1] = 1.1e-3;//micron 1325 v_th[1] = 0.40126;//V 1326 c_ox[1] = 2.30e-14;//F/micron2 1327 mobility_eff[1] = 738.09 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 1328 Vdsat[1] = 6.64e-2; //V/micron 1329 c_g_ideal[1] = 3.22e-16;//F/micron 1330 c_fringe[1] = 0.08e-15; 1331 c_junc[1] = 0;//F/micron2 1332 I_on_n[1] = 727.6e-6;//A/micron 1333 I_on_p[1] = I_on_n[1] / 2; 1334 nmos_effective_resistance_multiplier = 1.99; 1335 n_to_p_eff_curr_drv_ratio[1] = 2; 1336 gmp_to_gmn_multiplier[1] = 0.99; 1337 Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] / I_on_n[1];//ohm-micron 1338 Rpchannelon[1] = n_to_p_eff_curr_drv_ratio[1] * Rnchannelon[1];//ohm-micron 1339 long_channel_leakage_reduction[1] = 1 / 1.89; 1340 I_off_n[1][0] = 2.43e-11; 1341 I_off_n[1][10] = 4.85e-11; 1342 I_off_n[1][20] = 9.68e-11; 1343 I_off_n[1][30] = 1.94e-10; 1344 I_off_n[1][40] = 3.87e-10; 1345 I_off_n[1][50] = 7.73e-10; 1346 I_off_n[1][60] = 3.55e-10; 1347 I_off_n[1][70] = 3.09e-9; 1348 I_off_n[1][80] = 6.19e-9; 1349 I_off_n[1][90] = 1.24e-8; 1350 I_off_n[1][100] = 2.48e-8; 1351 1352 I_g_on_n[1][0] = 4.51e-10;//A/micron 1353 I_g_on_n[1][10] = 4.51e-10; 1354 I_g_on_n[1][20] = 4.51e-10; 1355 I_g_on_n[1][30] = 4.51e-10; 1356 I_g_on_n[1][40] = 4.51e-10; 1357 I_g_on_n[1][50] = 4.51e-10; 1358 I_g_on_n[1][60] = 4.51e-10; 1359 I_g_on_n[1][70] = 4.51e-10; 1360 I_g_on_n[1][80] = 4.51e-10; 1361 I_g_on_n[1][90] = 4.51e-10; 1362 I_g_on_n[1][100] = 4.51e-10; 1363 1364 //22 nm LOP 1365 vdd[2] = 0.6; 1366 Lphy[2] = 0.011; 1367 Lelec[2] = 0.00604;//Lelec is the electrical gate-length. 1368 t_ox[2] = 0.8e-3;//micron 1369 v_th[2] = 0.2315;//V 1370 c_ox[2] = 2.87e-14;//F/micron2 1371 mobility_eff[2] = 698.37 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 1372 Vdsat[2] = 1.81e-2; //V/micron 1373 c_g_ideal[2] = 3.16e-16;//F/micron 1374 c_fringe[2] = 0.08e-15; 1375 c_junc[2] = 0;//F/micron2 This is Cj0 not Cjunc in MASTAR results->Dynamic Tab 1376 I_on_n[2] = 916.1e-6;//A/micron 1377 I_on_p[2] = I_on_n[2] / 2; 1378 nmos_effective_resistance_multiplier = 1.73; 1379 n_to_p_eff_curr_drv_ratio[2] = 2; 1380 gmp_to_gmn_multiplier[2] = 1.11; 1381 Rnchannelon[2] = nmos_effective_resistance_multiplier * vdd[2] / I_on_n[2];//ohm-micron 1382 Rpchannelon[2] = n_to_p_eff_curr_drv_ratio[2] * Rnchannelon[2];//ohm-micron 1383 long_channel_leakage_reduction[2] = 1 / 2.38; 1384 1385 I_off_n[2][0] = 1.31e-8; 1386 I_off_n[2][10] = 2.60e-8; 1387 I_off_n[2][20] = 5.14e-8; 1388 I_off_n[2][30] = 1.02e-7; 1389 I_off_n[2][40] = 2.02e-7; 1390 I_off_n[2][50] = 3.99e-7; 1391 I_off_n[2][60] = 7.91e-7; 1392 I_off_n[2][70] = 1.09e-6; 1393 I_off_n[2][80] = 2.09e-6; 1394 I_off_n[2][90] = 4.04e-6; 1395 I_off_n[2][100] = 4.48e-6; 1396 1397 I_g_on_n[2][0] = 2.74e-9;//A/micron 1398 I_g_on_n[2][10] = 2.74e-9; 1399 I_g_on_n[2][20] = 2.74e-9; 1400 I_g_on_n[2][30] = 2.74e-9; 1401 I_g_on_n[2][40] = 2.74e-9; 1402 I_g_on_n[2][50] = 2.74e-9; 1403 I_g_on_n[2][60] = 2.74e-9; 1404 I_g_on_n[2][70] = 2.74e-9; 1405 I_g_on_n[2][80] = 2.74e-9; 1406 I_g_on_n[2][90] = 2.74e-9; 1407 I_g_on_n[2][100] = 2.74e-9; 1408 1409 1410 1411 if (ram_cell_tech_type == 3) {} else if (ram_cell_tech_type == 4) { 1412 //22 nm commodity DRAM cell access transistor technology parameters. 1413 //parameters 1414 curr_vdd_dram_cell = 0.9;//0.45;//This value has reduced greatly in 2007 ITRS for all technology nodes. In 1415 //2005 ITRS, the value was about twice the value in 2007 ITRS 1416 Lphy[3] = 0.022;//micron 1417 Lelec[3] = 0.0181;//micron. 1418 curr_v_th_dram_access_transistor = 1;//V 1419 width_dram_access_transistor = 0.022;//micron 1420 curr_I_on_dram_cell = 20e-6; //This is a typical value that I have always 1421 //kept constant. In reality this could perhaps be lower 1422 curr_I_off_dram_cell_worst_case_length_temp = 1e-15;//A 1423 curr_Wmemcella_dram = width_dram_access_transistor; 1424 curr_Wmemcellpmos_dram = 0; 1425 curr_Wmemcellnmos_dram = 0; 1426 curr_area_cell_dram = 6 * 0.022 * 0.022;//micron2. 1427 curr_asp_ratio_cell_dram = 0.667; 1428 curr_c_dram_cell = 30e-15;//This is a typical value that I have alwaus 1429 //kept constant. 1430 1431 //22 nm commodity DRAM wordline transistor parameters obtained using MASTAR. 1432 curr_vpp = 2.3;//vpp. V 1433 t_ox[3] = 3.5e-3;//micron 1434 v_th[3] = 1.0;//V 1435 c_ox[3] = 9.06e-15;//F/micron2 1436 mobility_eff[3] = 367.29 * (1e-2 * 1e6 * 1e-2 * 1e6);//micron2 / Vs 1437 Vdsat[3] = 0.0972; //V/micron 1438 c_g_ideal[3] = 1.99e-16;//F/micron 1439 c_fringe[3] = 0.053e-15;//F/micron 1440 c_junc[3] = 1e-15;//F/micron2 1441 I_on_n[3] = 910.5e-6;//A/micron 1442 I_on_p[3] = I_on_n[3] / 2;//This value for I_on_p is not really used. 1443 nmos_effective_resistance_multiplier = 1.69;//Using the value from 32nm. 1444 // 1445 n_to_p_eff_curr_drv_ratio[3] = 1.95;//Using the value from 32nm 1446 gmp_to_gmn_multiplier[3] = 0.90; 1447 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];//ohm-micron 1448 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];//ohm-micron 1449 long_channel_leakage_reduction[3] = 1; 1450 I_off_n[3][0] = 1.1e-13; //A/micron 1451 I_off_n[3][10] = 2.11e-13; 1452 I_off_n[3][20] = 3.88e-13; 1453 I_off_n[3][30] = 6.9e-13; 1454 I_off_n[3][40] = 1.19e-12; 1455 I_off_n[3][50] = 1.98e-12; 1456 I_off_n[3][60] = 3.22e-12; 1457 I_off_n[3][70] = 5.09e-12; 1458 I_off_n[3][80] = 7.85e-12; 1459 I_off_n[3][90] = 1.18e-11; 1460 I_off_n[3][100] = 1.72e-11; 1461 1462 } else { 1463 //some error handler 1464 } 1465 1466 //SRAM cell properties 1467 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 1468 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 1469 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 1470 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 1471 curr_asp_ratio_cell_sram = 1.46; 1472 //CAM cell properties //TODO: data need to be revisited 1473 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 1474 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 1475 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 1476 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; 1477 curr_asp_ratio_cell_cam = 2.92; 1478 //Empirical undifferetiated core/FU coefficient 1479 curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7 * 0.7; 1480 curr_core_tx_density = 1.25 / 0.7 / 0.7; 1481 curr_sckt_co_eff = 1.1296; 1482 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 1483 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 1484 } 1485 1486 if (tech == 16) { 1487 //For 2019, MPU/ASIC stagger-contacted M1 half-pitch is 16 nm (so this is 16 nm 1488 //technology i.e. FEATURESIZE = 0.016). Using the DG process numbers for HP. 1489 //16 nm HP 1490 vdd[0] = 0.7; 1491 Lphy[0] = 0.006;//Lphy is the physical gate-length. 1492 Lelec[0] = 0.00315;//Lelec is the electrical gate-length. 1493 t_ox[0] = 0.5e-3;//micron 1494 v_th[0] = 0.1489;//V 1495 c_ox[0] = 3.83e-14;//F/micron2 Cox_elec in MASTAR 1496 mobility_eff[0] = 476.15 * (1e-2 * 1e6 * 1e-2 * 1e6); //micron2 / Vs 1497 Vdsat[0] = 1.42e-2; //V/micron calculated in spreadsheet 1498 c_g_ideal[0] = 2.30e-16;//F/micron 1499 c_fringe[0] = 0.06e-15;//F/micron MASTAR inputdynamic/3 1500 c_junc[0] = 0;//F/micron2 MASTAR result dynamic 1501 I_on_n[0] = 2768.4e-6;//A/micron 1502 I_on_p[0] = I_on_n[0] / 2;//A/micron //This value for I_on_p is not really used. 1503 nmos_effective_resistance_multiplier = 1.48;//nmos_effective_resistance_multiplier is the ratio of Ieff to Idsat where Ieff is the effective NMOS current and Idsat is the saturation current. 1504 n_to_p_eff_curr_drv_ratio[0] = 2; //Wpmos/Wnmos = 2 in 2007 MASTAR. Look in 1505 //"Dynamic" tab of Device workspace. 1506 gmp_to_gmn_multiplier[0] = 1.38; //Just using the 32nm SOI value. 1507 Rnchannelon[0] = nmos_effective_resistance_multiplier * vdd[0] / I_on_n[0];//ohm-micron 1508 Rpchannelon[0] = n_to_p_eff_curr_drv_ratio[0] * Rnchannelon[0];//ohm-micron 1509 long_channel_leakage_reduction[0] = 1 / 2.655; 1510 I_off_n[0][0] = 1.52e-7 / 1.5 * 1.2 * 1.07; 1511 I_off_n[0][10] = 1.55e-7 / 1.5 * 1.2 * 1.07; 1512 I_off_n[0][20] = 1.59e-7 / 1.5 * 1.2 * 1.07; 1513 I_off_n[0][30] = 1.68e-7 / 1.5 * 1.2 * 1.07; 1514 I_off_n[0][40] = 1.90e-7 / 1.5 * 1.2 * 1.07; 1515 I_off_n[0][50] = 2.69e-7 / 1.5 * 1.2 * 1.07; 1516 I_off_n[0][60] = 5.32e-7 / 1.5 * 1.2 * 1.07; 1517 I_off_n[0][70] = 1.02e-6 / 1.5 * 1.2 * 1.07; 1518 I_off_n[0][80] = 1.62e-6 / 1.5 * 1.2 * 1.07; 1519 I_off_n[0][90] = 2.73e-6 / 1.5 * 1.2 * 1.07; 1520 I_off_n[0][100] = 6.1e-6 / 1.5 * 1.2 * 1.07; 1521 //for 16nm DG HP 1522 I_g_on_n[0][0] = 1.07e-9;//A/micron 1523 I_g_on_n[0][10] = 1.07e-9; 1524 I_g_on_n[0][20] = 1.07e-9; 1525 I_g_on_n[0][30] = 1.07e-9; 1526 I_g_on_n[0][40] = 1.07e-9; 1527 I_g_on_n[0][50] = 1.07e-9; 1528 I_g_on_n[0][60] = 1.07e-9; 1529 I_g_on_n[0][70] = 1.07e-9; 1530 I_g_on_n[0][80] = 1.07e-9; 1531 I_g_on_n[0][90] = 1.07e-9; 1532 I_g_on_n[0][100] = 1.07e-9; 1533 1534 if (ram_cell_tech_type == 3) {} else if (ram_cell_tech_type == 4) { 1535 //22 nm commodity DRAM cell access transistor technology parameters. 1536 //parameters 1537 curr_vdd_dram_cell = 0.9;//0.45;//This value has reduced greatly in 2007 ITRS for all technology nodes. In 1538 //2005 ITRS, the value was about twice the value in 2007 ITRS 1539 Lphy[3] = 0.022;//micron 1540 Lelec[3] = 0.0181;//micron. 1541 curr_v_th_dram_access_transistor = 1;//V 1542 width_dram_access_transistor = 0.022;//micron 1543 curr_I_on_dram_cell = 20e-6; //This is a typical value that I have always 1544 //kept constant. In reality this could perhaps be lower 1545 curr_I_off_dram_cell_worst_case_length_temp = 1e-15;//A 1546 curr_Wmemcella_dram = width_dram_access_transistor; 1547 curr_Wmemcellpmos_dram = 0; 1548 curr_Wmemcellnmos_dram = 0; 1549 curr_area_cell_dram = 6 * 0.022 * 0.022;//micron2. 1550 curr_asp_ratio_cell_dram = 0.667; 1551 curr_c_dram_cell = 30e-15;//This is a typical value that I have alwaus 1552 //kept constant. 1553 1554 //22 nm commodity DRAM wordline transistor parameters obtained using MASTAR. 1555 curr_vpp = 2.3;//vpp. V 1556 t_ox[3] = 3.5e-3;//micron 1557 v_th[3] = 1.0;//V 1558 c_ox[3] = 9.06e-15;//F/micron2 1559 mobility_eff[3] = 367.29 * (1e-2 * 1e6 * 1e-2 * 1e6);//micron2 / Vs 1560 Vdsat[3] = 0.0972; //V/micron 1561 c_g_ideal[3] = 1.99e-16;//F/micron 1562 c_fringe[3] = 0.053e-15;//F/micron 1563 c_junc[3] = 1e-15;//F/micron2 1564 I_on_n[3] = 910.5e-6;//A/micron 1565 I_on_p[3] = I_on_n[3] / 2;//This value for I_on_p is not really used. 1566 nmos_effective_resistance_multiplier = 1.69;//Using the value from 32nm. 1567 // 1568 n_to_p_eff_curr_drv_ratio[3] = 1.95;//Using the value from 32nm 1569 gmp_to_gmn_multiplier[3] = 0.90; 1570 Rnchannelon[3] = nmos_effective_resistance_multiplier * curr_vpp / I_on_n[3];//ohm-micron 1571 Rpchannelon[3] = n_to_p_eff_curr_drv_ratio[3] * Rnchannelon[3];//ohm-micron 1572 long_channel_leakage_reduction[3] = 1; 1573 I_off_n[3][0] = 1.1e-13; //A/micron 1574 I_off_n[3][10] = 2.11e-13; 1575 I_off_n[3][20] = 3.88e-13; 1576 I_off_n[3][30] = 6.9e-13; 1577 I_off_n[3][40] = 1.19e-12; 1578 I_off_n[3][50] = 1.98e-12; 1579 I_off_n[3][60] = 3.22e-12; 1580 I_off_n[3][70] = 5.09e-12; 1581 I_off_n[3][80] = 7.85e-12; 1582 I_off_n[3][90] = 1.18e-11; 1583 I_off_n[3][100] = 1.72e-11; 1584 1585 } else { 1586 //some error handler 1587 } 1588 1589 //SRAM cell properties 1590 curr_Wmemcella_sram = 1.31 * g_ip->F_sz_um; 1591 curr_Wmemcellpmos_sram = 1.23 * g_ip->F_sz_um; 1592 curr_Wmemcellnmos_sram = 2.08 * g_ip->F_sz_um; 1593 curr_area_cell_sram = 146 * g_ip->F_sz_um * g_ip->F_sz_um; 1594 curr_asp_ratio_cell_sram = 1.46; 1595 //CAM cell properties //TODO: data need to be revisited 1596 curr_Wmemcella_cam = 1.31 * g_ip->F_sz_um; 1597 curr_Wmemcellpmos_cam = 1.23 * g_ip->F_sz_um; 1598 curr_Wmemcellnmos_cam = 2.08 * g_ip->F_sz_um; 1599 curr_area_cell_cam = 292 * g_ip->F_sz_um * g_ip->F_sz_um; 1600 curr_asp_ratio_cell_cam = 2.92; 1601 //Empirical undifferetiated core/FU coefficient 1602 curr_logic_scaling_co_eff = 0.7 * 0.7 * 0.7 * 0.7 * 0.7; 1603 curr_core_tx_density = 1.25 / 0.7 / 0.7 / 0.7; 1604 curr_sckt_co_eff = 1.1296; 1605 curr_chip_layout_overhead = 1.2;//die measurement results based on Niagara 1 and 2 1606 curr_macro_layout_overhead = 1.1;//EDA placement and routing tool rule of thumb 1607 } 1608 1609 1610 g_tp.peri_global.Vdd += curr_alpha * vdd[peri_global_tech_type]; 1611 g_tp.peri_global.t_ox += curr_alpha * t_ox[peri_global_tech_type]; 1612 g_tp.peri_global.Vth += curr_alpha * v_th[peri_global_tech_type]; 1613 g_tp.peri_global.C_ox += curr_alpha * c_ox[peri_global_tech_type]; 1614 g_tp.peri_global.C_g_ideal += curr_alpha * c_g_ideal[peri_global_tech_type]; 1615 g_tp.peri_global.C_fringe += curr_alpha * c_fringe[peri_global_tech_type]; 1616 g_tp.peri_global.C_junc += curr_alpha * c_junc[peri_global_tech_type]; 1617 g_tp.peri_global.C_junc_sidewall = 0.25e-15; // F/micron 1618 g_tp.peri_global.l_phy += curr_alpha * Lphy[peri_global_tech_type]; 1619 g_tp.peri_global.l_elec += curr_alpha * Lelec[peri_global_tech_type]; 1620 g_tp.peri_global.I_on_n += curr_alpha * I_on_n[peri_global_tech_type]; 1621 g_tp.peri_global.R_nch_on += curr_alpha * Rnchannelon[peri_global_tech_type]; 1622 g_tp.peri_global.R_pch_on += curr_alpha * Rpchannelon[peri_global_tech_type]; 1623 g_tp.peri_global.n_to_p_eff_curr_drv_ratio 1624 += curr_alpha * n_to_p_eff_curr_drv_ratio[peri_global_tech_type]; 1625 g_tp.peri_global.long_channel_leakage_reduction 1626 += curr_alpha * long_channel_leakage_reduction[peri_global_tech_type]; 1627 g_tp.peri_global.I_off_n += curr_alpha * I_off_n[peri_global_tech_type][g_ip->temp - 300]; 1628 g_tp.peri_global.I_off_p += curr_alpha * I_off_n[peri_global_tech_type][g_ip->temp - 300]; 1629 g_tp.peri_global.I_g_on_n += curr_alpha * I_g_on_n[peri_global_tech_type][g_ip->temp - 300]; 1630 g_tp.peri_global.I_g_on_p += curr_alpha * I_g_on_n[peri_global_tech_type][g_ip->temp - 300]; 1631 gmp_to_gmn_multiplier_periph_global += curr_alpha * gmp_to_gmn_multiplier[peri_global_tech_type]; 1632 1633 g_tp.sram_cell.Vdd += curr_alpha * vdd[ram_cell_tech_type]; 1634 g_tp.sram_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type]; 1635 g_tp.sram_cell.l_elec += curr_alpha * Lelec[ram_cell_tech_type]; 1636 g_tp.sram_cell.t_ox += curr_alpha * t_ox[ram_cell_tech_type]; 1637 g_tp.sram_cell.Vth += curr_alpha * v_th[ram_cell_tech_type]; 1638 g_tp.sram_cell.C_g_ideal += curr_alpha * c_g_ideal[ram_cell_tech_type]; 1639 g_tp.sram_cell.C_fringe += curr_alpha * c_fringe[ram_cell_tech_type]; 1640 g_tp.sram_cell.C_junc += curr_alpha * c_junc[ram_cell_tech_type]; 1641 g_tp.sram_cell.C_junc_sidewall = 0.25e-15; // F/micron 1642 g_tp.sram_cell.I_on_n += curr_alpha * I_on_n[ram_cell_tech_type]; 1643 g_tp.sram_cell.R_nch_on += curr_alpha * Rnchannelon[ram_cell_tech_type]; 1644 g_tp.sram_cell.R_pch_on += curr_alpha * Rpchannelon[ram_cell_tech_type]; 1645 g_tp.sram_cell.n_to_p_eff_curr_drv_ratio += curr_alpha * n_to_p_eff_curr_drv_ratio[ram_cell_tech_type]; 1646 g_tp.sram_cell.long_channel_leakage_reduction += curr_alpha * long_channel_leakage_reduction[ram_cell_tech_type]; 1647 g_tp.sram_cell.I_off_n += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300]; 1648 g_tp.sram_cell.I_off_p += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300]; 1649 g_tp.sram_cell.I_g_on_n += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; 1650 g_tp.sram_cell.I_g_on_p += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; 1651 1652 g_tp.dram_cell_Vdd += curr_alpha * curr_vdd_dram_cell; 1653 g_tp.dram_acc.Vth += curr_alpha * curr_v_th_dram_access_transistor; 1654 g_tp.dram_acc.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor]; 1655 g_tp.dram_acc.l_elec += curr_alpha * Lelec[dram_cell_tech_flavor]; 1656 g_tp.dram_acc.C_g_ideal += curr_alpha * c_g_ideal[dram_cell_tech_flavor]; 1657 g_tp.dram_acc.C_fringe += curr_alpha * c_fringe[dram_cell_tech_flavor]; 1658 g_tp.dram_acc.C_junc += curr_alpha * c_junc[dram_cell_tech_flavor]; 1659 g_tp.dram_acc.C_junc_sidewall = 0.25e-15; // F/micron 1660 g_tp.dram_cell_I_on += curr_alpha * curr_I_on_dram_cell; 1661 g_tp.dram_cell_I_off_worst_case_len_temp += curr_alpha * curr_I_off_dram_cell_worst_case_length_temp; 1662 g_tp.dram_acc.I_on_n += curr_alpha * I_on_n[dram_cell_tech_flavor]; 1663 g_tp.dram_cell_C += curr_alpha * curr_c_dram_cell; 1664 g_tp.vpp += curr_alpha * curr_vpp; 1665 g_tp.dram_wl.l_phy += curr_alpha * Lphy[dram_cell_tech_flavor]; 1666 g_tp.dram_wl.l_elec += curr_alpha * Lelec[dram_cell_tech_flavor]; 1667 g_tp.dram_wl.C_g_ideal += curr_alpha * c_g_ideal[dram_cell_tech_flavor]; 1668 g_tp.dram_wl.C_fringe += curr_alpha * c_fringe[dram_cell_tech_flavor]; 1669 g_tp.dram_wl.C_junc += curr_alpha * c_junc[dram_cell_tech_flavor]; 1670 g_tp.dram_wl.C_junc_sidewall = 0.25e-15; // F/micron 1671 g_tp.dram_wl.I_on_n += curr_alpha * I_on_n[dram_cell_tech_flavor]; 1672 g_tp.dram_wl.R_nch_on += curr_alpha * Rnchannelon[dram_cell_tech_flavor]; 1673 g_tp.dram_wl.R_pch_on += curr_alpha * Rpchannelon[dram_cell_tech_flavor]; 1674 g_tp.dram_wl.n_to_p_eff_curr_drv_ratio += curr_alpha * n_to_p_eff_curr_drv_ratio[dram_cell_tech_flavor]; 1675 g_tp.dram_wl.long_channel_leakage_reduction += curr_alpha * long_channel_leakage_reduction[dram_cell_tech_flavor]; 1676 g_tp.dram_wl.I_off_n += curr_alpha * I_off_n[dram_cell_tech_flavor][g_ip->temp - 300]; 1677 g_tp.dram_wl.I_off_p += curr_alpha * I_off_n[dram_cell_tech_flavor][g_ip->temp - 300]; 1678 1679 g_tp.cam_cell.Vdd += curr_alpha * vdd[ram_cell_tech_type]; 1680 g_tp.cam_cell.l_phy += curr_alpha * Lphy[ram_cell_tech_type]; 1681 g_tp.cam_cell.l_elec += curr_alpha * Lelec[ram_cell_tech_type]; 1682 g_tp.cam_cell.t_ox += curr_alpha * t_ox[ram_cell_tech_type]; 1683 g_tp.cam_cell.Vth += curr_alpha * v_th[ram_cell_tech_type]; 1684 g_tp.cam_cell.C_g_ideal += curr_alpha * c_g_ideal[ram_cell_tech_type]; 1685 g_tp.cam_cell.C_fringe += curr_alpha * c_fringe[ram_cell_tech_type]; 1686 g_tp.cam_cell.C_junc += curr_alpha * c_junc[ram_cell_tech_type]; 1687 g_tp.cam_cell.C_junc_sidewall = 0.25e-15; // F/micron 1688 g_tp.cam_cell.I_on_n += curr_alpha * I_on_n[ram_cell_tech_type]; 1689 g_tp.cam_cell.R_nch_on += curr_alpha * Rnchannelon[ram_cell_tech_type]; 1690 g_tp.cam_cell.R_pch_on += curr_alpha * Rpchannelon[ram_cell_tech_type]; 1691 g_tp.cam_cell.n_to_p_eff_curr_drv_ratio += curr_alpha * n_to_p_eff_curr_drv_ratio[ram_cell_tech_type]; 1692 g_tp.cam_cell.long_channel_leakage_reduction += curr_alpha * long_channel_leakage_reduction[ram_cell_tech_type]; 1693 g_tp.cam_cell.I_off_n += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300]; 1694 g_tp.cam_cell.I_off_p += curr_alpha * I_off_n[ram_cell_tech_type][g_ip->temp - 300]; 1695 g_tp.cam_cell.I_g_on_n += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; 1696 g_tp.cam_cell.I_g_on_p += curr_alpha * I_g_on_n[ram_cell_tech_type][g_ip->temp - 300]; 1697 1698 g_tp.dram.cell_a_w += curr_alpha * curr_Wmemcella_dram; 1699 g_tp.dram.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_dram; 1700 g_tp.dram.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_dram; 1701 area_cell_dram += curr_alpha * curr_area_cell_dram; 1702 asp_ratio_cell_dram += curr_alpha * curr_asp_ratio_cell_dram; 1703 1704 g_tp.sram.cell_a_w += curr_alpha * curr_Wmemcella_sram; 1705 g_tp.sram.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_sram; 1706 g_tp.sram.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_sram; 1707 area_cell_sram += curr_alpha * curr_area_cell_sram; 1708 asp_ratio_cell_sram += curr_alpha * curr_asp_ratio_cell_sram; 1709 1710 g_tp.cam.cell_a_w += curr_alpha * curr_Wmemcella_cam;//sheng 1711 g_tp.cam.cell_pmos_w += curr_alpha * curr_Wmemcellpmos_cam; 1712 g_tp.cam.cell_nmos_w += curr_alpha * curr_Wmemcellnmos_cam; 1713 area_cell_cam += curr_alpha * curr_area_cell_cam; 1714 asp_ratio_cell_cam += curr_alpha * curr_asp_ratio_cell_cam; 1715 1716 //Sense amplifier latch Gm calculation 1717 mobility_eff_periph_global += curr_alpha * mobility_eff[peri_global_tech_type]; 1718 Vdsat_periph_global += curr_alpha * Vdsat[peri_global_tech_type]; 1719 1720 //Empirical undifferetiated core/FU coefficient 1721 g_tp.scaling_factor.logic_scaling_co_eff += curr_alpha * curr_logic_scaling_co_eff; 1722 g_tp.scaling_factor.core_tx_density += curr_alpha * curr_core_tx_density; 1723 g_tp.chip_layout_overhead += curr_alpha * curr_chip_layout_overhead; 1724 g_tp.macro_layout_overhead += curr_alpha * curr_macro_layout_overhead; 1725 g_tp.sckt_co_eff += curr_alpha * curr_sckt_co_eff; 1726 } 1727 1728 1729 //Currently we are not modeling the resistance/capacitance of poly anywhere. 1730 //Continuous function (or date have been processed) does not need linear interpolation 1731 g_tp.w_comp_inv_p1 = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process 1732 g_tp.w_comp_inv_n1 = 7.5 * g_ip->F_sz_um;//this was 6 micron for the 0.8 micron process 1733 g_tp.w_comp_inv_p2 = 25 * g_ip->F_sz_um;//this was 20 micron for the 0.8 micron process 1734 g_tp.w_comp_inv_n2 = 15 * g_ip->F_sz_um;//this was 12 micron for the 0.8 micron process 1735 g_tp.w_comp_inv_p3 = 50 * g_ip->F_sz_um;//this was 40 micron for the 0.8 micron process 1736 g_tp.w_comp_inv_n3 = 30 * g_ip->F_sz_um;//this was 24 micron for the 0.8 micron process 1737 g_tp.w_eval_inv_p = 100 * g_ip->F_sz_um;//this was 80 micron for the 0.8 micron process 1738 g_tp.w_eval_inv_n = 50 * g_ip->F_sz_um;//this was 40 micron for the 0.8 micron process 1739 g_tp.w_comp_n = 12.5 * g_ip->F_sz_um;//this was 10 micron for the 0.8 micron process 1740 g_tp.w_comp_p = 37.5 * g_ip->F_sz_um;//this was 30 micron for the 0.8 micron process 1741 1742 g_tp.MIN_GAP_BET_P_AND_N_DIFFS = 5 * g_ip->F_sz_um; 1743 g_tp.MIN_GAP_BET_SAME_TYPE_DIFFS = 1.5 * g_ip->F_sz_um; 1744 g_tp.HPOWERRAIL = 2 * g_ip->F_sz_um; 1745 g_tp.cell_h_def = 50 * g_ip->F_sz_um; 1746 g_tp.w_poly_contact = g_ip->F_sz_um; 1747 g_tp.spacing_poly_to_contact = g_ip->F_sz_um; 1748 g_tp.spacing_poly_to_poly = 1.5 * g_ip->F_sz_um; 1749 g_tp.ram_wl_stitching_overhead_ = 7.5 * g_ip->F_sz_um; 1750 1751 g_tp.min_w_nmos_ = 3 * g_ip->F_sz_um / 2; 1752 g_tp.max_w_nmos_ = 100 * g_ip->F_sz_um; 1753 //was 10 micron for the 0.8 micron process 1754 g_tp.w_iso = 12.5 * g_ip->F_sz_um; 1755 // sense amplifier N-trans; was 3 micron for the 0.8 micron process 1756 g_tp.w_sense_n = 3.75 * g_ip->F_sz_um; 1757 // sense amplifier P-trans; was 6 micron for the 0.8 micron process 1758 g_tp.w_sense_p = 7.5 * g_ip->F_sz_um; 1759 // Sense enable transistor of the sense amplifier; was 4 micron for the 1760 //0.8 micron process 1761 g_tp.w_sense_en = 5 * g_ip->F_sz_um; 1762 g_tp.w_nmos_b_mux = 6 * g_tp.min_w_nmos_; 1763 g_tp.w_nmos_sa_mux= 6 * g_tp.min_w_nmos_; 1764 1765 if (ram_cell_tech_type == comm_dram) { 1766 g_tp.max_w_nmos_dec = 8 * g_ip->F_sz_um; 1767 g_tp.h_dec = 8; // in the unit of memory cell height 1768 } else { 1769 g_tp.max_w_nmos_dec = g_tp.max_w_nmos_; 1770 g_tp.h_dec = 4; // in the unit of memory cell height 1771 } 1772 1773 g_tp.peri_global.C_overlap = 0.2 * g_tp.peri_global.C_g_ideal; 1774 g_tp.sram_cell.C_overlap = 0.2 * g_tp.sram_cell.C_g_ideal; 1775 g_tp.cam_cell.C_overlap = 0.2 * g_tp.cam_cell.C_g_ideal; 1776 1777 g_tp.dram_acc.C_overlap = 0.2 * g_tp.dram_acc.C_g_ideal; 1778 g_tp.dram_acc.R_nch_on = g_tp.dram_cell_Vdd / g_tp.dram_acc.I_on_n; 1779 //g_tp.dram_acc.R_pch_on = g_tp.dram_cell_Vdd / g_tp.dram_acc.I_on_p; 1780 1781 g_tp.dram_wl.C_overlap = 0.2 * g_tp.dram_wl.C_g_ideal; 1782 1783 double gmn_sense_amp_latch = (mobility_eff_periph_global / 2) * g_tp.peri_global.C_ox * (g_tp.w_sense_n / g_tp.peri_global.l_elec) * Vdsat_periph_global; 1784 double gmp_sense_amp_latch = gmp_to_gmn_multiplier_periph_global * gmn_sense_amp_latch; 1785 g_tp.gm_sense_amp_latch = gmn_sense_amp_latch + gmp_sense_amp_latch; 1786 1787 g_tp.dram.b_w = sqrt(area_cell_dram / (asp_ratio_cell_dram)); 1788 g_tp.dram.b_h = asp_ratio_cell_dram * g_tp.dram.b_w; 1789 g_tp.sram.b_w = sqrt(area_cell_sram / (asp_ratio_cell_sram)); 1790 g_tp.sram.b_h = asp_ratio_cell_sram * g_tp.sram.b_w; 1791 g_tp.cam.b_w = sqrt(area_cell_cam / (asp_ratio_cell_cam));//Sheng 1792 g_tp.cam.b_h = asp_ratio_cell_cam * g_tp.cam.b_w; 1793 1794 g_tp.dram.Vbitpre = g_tp.dram_cell_Vdd; 1795 g_tp.sram.Vbitpre = vdd[ram_cell_tech_type]; 1796 g_tp.cam.Vbitpre = vdd[ram_cell_tech_type];//Sheng 1797 pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio(); 1798 g_tp.w_pmos_bl_precharge = 6 * pmos_to_nmos_sizing_r * g_tp.min_w_nmos_; 1799 g_tp.w_pmos_bl_eq = pmos_to_nmos_sizing_r * g_tp.min_w_nmos_; 1800 1801 1802 double wire_pitch [NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 1803 wire_r_per_micron[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 1804 wire_c_per_micron[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 1805 horiz_dielectric_constant[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 1806 vert_dielectric_constant[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 1807 aspect_ratio[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 1808 miller_value[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES], 1809 ild_thickness[NUMBER_INTERCONNECT_PROJECTION_TYPES][NUMBER_WIRE_TYPES]; 1810 1811 for (iter = 0; iter <= 1; ++iter) { 1812 // linear interpolation 1813 if (iter == 0) { 1814 tech = tech_lo; 1815 if (tech_lo == tech_hi) { 1816 curr_alpha = 1; 1817 } else { 1818 curr_alpha = (technology - tech_hi) / (tech_lo - tech_hi); 1819 } 1820 } else { 1821 tech = tech_hi; 1822 if (tech_lo == tech_hi) { 1823 break; 1824 } else { 1825 curr_alpha = (tech_lo - technology) / (tech_lo - tech_hi); 1826 } 1827 } 1828 1829 if (tech == 180) { 1830 //Aggressive projections 1831 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//micron 1832 aspect_ratio[0][0] = 2.0; 1833 wire_width = wire_pitch[0][0] / 2; //micron 1834 wire_thickness = aspect_ratio[0][0] * wire_width;//micron 1835 wire_spacing = wire_pitch[0][0] - wire_width;//micron 1836 barrier_thickness = 0.017;//micron 1837 dishing_thickness = 0;//micron 1838 alpha_scatter = 1; 1839 wire_r_per_micron[0][0] = wire_resistance(CU_RESISTIVITY, wire_width, 1840 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);//ohm/micron 1841 ild_thickness[0][0] = 0.75;//micron 1842 miller_value[0][0] = 1.5; 1843 horiz_dielectric_constant[0][0] = 2.709; 1844 vert_dielectric_constant[0][0] = 3.9; 1845 fringe_cap = 0.115e-15; //F/micron 1846 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 1847 ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], 1848 vert_dielectric_constant[0][0], 1849 fringe_cap);//F/micron. 1850 1851 wire_pitch[0][1] = 4 * g_ip->F_sz_um; 1852 wire_width = wire_pitch[0][1] / 2; 1853 aspect_ratio[0][1] = 2.4; 1854 wire_thickness = aspect_ratio[0][1] * wire_width; 1855 wire_spacing = wire_pitch[0][1] - wire_width; 1856 wire_r_per_micron[0][1] = wire_resistance(CU_RESISTIVITY, wire_width, 1857 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 1858 ild_thickness[0][1] = 0.75;//micron 1859 miller_value[0][1] = 1.5; 1860 horiz_dielectric_constant[0][1] = 2.709; 1861 vert_dielectric_constant[0][1] = 3.9; 1862 fringe_cap = 0.115e-15; //F/micron 1863 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 1864 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], 1865 vert_dielectric_constant[0][1], 1866 fringe_cap); 1867 1868 wire_pitch[0][2] = 8 * g_ip->F_sz_um; 1869 aspect_ratio[0][2] = 2.2; 1870 wire_width = wire_pitch[0][2] / 2; 1871 wire_thickness = aspect_ratio[0][2] * wire_width; 1872 wire_spacing = wire_pitch[0][2] - wire_width; 1873 wire_r_per_micron[0][2] = wire_resistance(CU_RESISTIVITY, wire_width, 1874 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 1875 ild_thickness[0][2] = 1.5; 1876 miller_value[0][2] = 1.5; 1877 horiz_dielectric_constant[0][2] = 2.709; 1878 vert_dielectric_constant[0][2] = 3.9; 1879 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 1880 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 1881 fringe_cap); 1882 1883 //Conservative projections 1884 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 1885 aspect_ratio[1][0] = 2.0; 1886 wire_width = wire_pitch[1][0] / 2; 1887 wire_thickness = aspect_ratio[1][0] * wire_width; 1888 wire_spacing = wire_pitch[1][0] - wire_width; 1889 barrier_thickness = 0.017; 1890 dishing_thickness = 0; 1891 alpha_scatter = 1; 1892 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 1893 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 1894 ild_thickness[1][0] = 0.75; 1895 miller_value[1][0] = 1.5; 1896 horiz_dielectric_constant[1][0] = 3.038; 1897 vert_dielectric_constant[1][0] = 3.9; 1898 fringe_cap = 0.115e-15; 1899 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 1900 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], 1901 vert_dielectric_constant[1][0], 1902 fringe_cap); 1903 1904 wire_pitch[1][1] = 4 * g_ip->F_sz_um; 1905 wire_width = wire_pitch[1][1] / 2; 1906 aspect_ratio[1][1] = 2.0; 1907 wire_thickness = aspect_ratio[1][1] * wire_width; 1908 wire_spacing = wire_pitch[1][1] - wire_width; 1909 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 1910 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 1911 ild_thickness[1][1] = 0.75; 1912 miller_value[1][1] = 1.5; 1913 horiz_dielectric_constant[1][1] = 3.038; 1914 vert_dielectric_constant[1][1] = 3.9; 1915 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 1916 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], 1917 vert_dielectric_constant[1][1], 1918 fringe_cap); 1919 1920 wire_pitch[1][2] = 8 * g_ip->F_sz_um; 1921 aspect_ratio[1][2] = 2.2; 1922 wire_width = wire_pitch[1][2] / 2; 1923 wire_thickness = aspect_ratio[1][2] * wire_width; 1924 wire_spacing = wire_pitch[1][2] - wire_width; 1925 dishing_thickness = 0.1 * wire_thickness; 1926 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 1927 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 1928 ild_thickness[1][2] = 1.98; 1929 miller_value[1][2] = 1.5; 1930 horiz_dielectric_constant[1][2] = 3.038; 1931 vert_dielectric_constant[1][2] = 3.9; 1932 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 1933 ild_thickness[1][2] , miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 1934 fringe_cap); 1935 //Nominal projections for commodity DRAM wordline/bitline 1936 wire_pitch[1][3] = 2 * 0.18; 1937 wire_c_per_micron[1][3] = 60e-15 / (256 * 2 * 0.18); 1938 wire_r_per_micron[1][3] = 12 / 0.18; 1939 } else if (tech == 90) { 1940 //Aggressive projections 1941 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//micron 1942 aspect_ratio[0][0] = 2.4; 1943 wire_width = wire_pitch[0][0] / 2; //micron 1944 wire_thickness = aspect_ratio[0][0] * wire_width;//micron 1945 wire_spacing = wire_pitch[0][0] - wire_width;//micron 1946 barrier_thickness = 0.01;//micron 1947 dishing_thickness = 0;//micron 1948 alpha_scatter = 1; 1949 wire_r_per_micron[0][0] = wire_resistance(CU_RESISTIVITY, wire_width, 1950 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter);//ohm/micron 1951 ild_thickness[0][0] = 0.48;//micron 1952 miller_value[0][0] = 1.5; 1953 horiz_dielectric_constant[0][0] = 2.709; 1954 vert_dielectric_constant[0][0] = 3.9; 1955 fringe_cap = 0.115e-15; //F/micron 1956 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 1957 ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], 1958 vert_dielectric_constant[0][0], 1959 fringe_cap);//F/micron. 1960 1961 wire_pitch[0][1] = 4 * g_ip->F_sz_um; 1962 wire_width = wire_pitch[0][1] / 2; 1963 aspect_ratio[0][1] = 2.4; 1964 wire_thickness = aspect_ratio[0][1] * wire_width; 1965 wire_spacing = wire_pitch[0][1] - wire_width; 1966 wire_r_per_micron[0][1] = wire_resistance(CU_RESISTIVITY, wire_width, 1967 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 1968 ild_thickness[0][1] = 0.48;//micron 1969 miller_value[0][1] = 1.5; 1970 horiz_dielectric_constant[0][1] = 2.709; 1971 vert_dielectric_constant[0][1] = 3.9; 1972 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 1973 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], 1974 vert_dielectric_constant[0][1], 1975 fringe_cap); 1976 1977 wire_pitch[0][2] = 8 * g_ip->F_sz_um; 1978 aspect_ratio[0][2] = 2.7; 1979 wire_width = wire_pitch[0][2] / 2; 1980 wire_thickness = aspect_ratio[0][2] * wire_width; 1981 wire_spacing = wire_pitch[0][2] - wire_width; 1982 wire_r_per_micron[0][2] = wire_resistance(CU_RESISTIVITY, wire_width, 1983 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 1984 ild_thickness[0][2] = 0.96; 1985 miller_value[0][2] = 1.5; 1986 horiz_dielectric_constant[0][2] = 2.709; 1987 vert_dielectric_constant[0][2] = 3.9; 1988 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 1989 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 1990 fringe_cap); 1991 1992 //Conservative projections 1993 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 1994 aspect_ratio[1][0] = 2.0; 1995 wire_width = wire_pitch[1][0] / 2; 1996 wire_thickness = aspect_ratio[1][0] * wire_width; 1997 wire_spacing = wire_pitch[1][0] - wire_width; 1998 barrier_thickness = 0.008; 1999 dishing_thickness = 0; 2000 alpha_scatter = 1; 2001 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 2002 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2003 ild_thickness[1][0] = 0.48; 2004 miller_value[1][0] = 1.5; 2005 horiz_dielectric_constant[1][0] = 3.038; 2006 vert_dielectric_constant[1][0] = 3.9; 2007 fringe_cap = 0.115e-15; 2008 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2009 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], 2010 vert_dielectric_constant[1][0], 2011 fringe_cap); 2012 2013 wire_pitch[1][1] = 4 * g_ip->F_sz_um; 2014 wire_width = wire_pitch[1][1] / 2; 2015 aspect_ratio[1][1] = 2.0; 2016 wire_thickness = aspect_ratio[1][1] * wire_width; 2017 wire_spacing = wire_pitch[1][1] - wire_width; 2018 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 2019 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2020 ild_thickness[1][1] = 0.48; 2021 miller_value[1][1] = 1.5; 2022 horiz_dielectric_constant[1][1] = 3.038; 2023 vert_dielectric_constant[1][1] = 3.9; 2024 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2025 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], 2026 vert_dielectric_constant[1][1], 2027 fringe_cap); 2028 2029 wire_pitch[1][2] = 8 * g_ip->F_sz_um; 2030 aspect_ratio[1][2] = 2.2; 2031 wire_width = wire_pitch[1][2] / 2; 2032 wire_thickness = aspect_ratio[1][2] * wire_width; 2033 wire_spacing = wire_pitch[1][2] - wire_width; 2034 dishing_thickness = 0.1 * wire_thickness; 2035 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 2036 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2037 ild_thickness[1][2] = 1.1; 2038 miller_value[1][2] = 1.5; 2039 horiz_dielectric_constant[1][2] = 3.038; 2040 vert_dielectric_constant[1][2] = 3.9; 2041 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2042 ild_thickness[1][2] , miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 2043 fringe_cap); 2044 //Nominal projections for commodity DRAM wordline/bitline 2045 wire_pitch[1][3] = 2 * 0.09; 2046 wire_c_per_micron[1][3] = 60e-15 / (256 * 2 * 0.09); 2047 wire_r_per_micron[1][3] = 12 / 0.09; 2048 } else if (tech == 65) { 2049 //Aggressive projections 2050 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; 2051 aspect_ratio[0][0] = 2.7; 2052 wire_width = wire_pitch[0][0] / 2; 2053 wire_thickness = aspect_ratio[0][0] * wire_width; 2054 wire_spacing = wire_pitch[0][0] - wire_width; 2055 barrier_thickness = 0; 2056 dishing_thickness = 0; 2057 alpha_scatter = 1; 2058 wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2059 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2060 ild_thickness[0][0] = 0.405; 2061 miller_value[0][0] = 1.5; 2062 horiz_dielectric_constant[0][0] = 2.303; 2063 vert_dielectric_constant[0][0] = 3.9; 2064 fringe_cap = 0.115e-15; 2065 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2066 ild_thickness[0][0] , miller_value[0][0] , horiz_dielectric_constant[0][0] , vert_dielectric_constant[0][0] , 2067 fringe_cap); 2068 2069 wire_pitch[0][1] = 4 * g_ip->F_sz_um; 2070 wire_width = wire_pitch[0][1] / 2; 2071 aspect_ratio[0][1] = 2.7; 2072 wire_thickness = aspect_ratio[0][1] * wire_width; 2073 wire_spacing = wire_pitch[0][1] - wire_width; 2074 wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2075 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2076 ild_thickness[0][1] = 0.405; 2077 miller_value[0][1] = 1.5; 2078 horiz_dielectric_constant[0][1] = 2.303; 2079 vert_dielectric_constant[0][1] = 3.9; 2080 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2081 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], 2082 vert_dielectric_constant[0][1], 2083 fringe_cap); 2084 2085 wire_pitch[0][2] = 8 * g_ip->F_sz_um; 2086 aspect_ratio[0][2] = 2.8; 2087 wire_width = wire_pitch[0][2] / 2; 2088 wire_thickness = aspect_ratio[0][2] * wire_width; 2089 wire_spacing = wire_pitch[0][2] - wire_width; 2090 wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2091 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2092 ild_thickness[0][2] = 0.81; 2093 miller_value[0][2] = 1.5; 2094 horiz_dielectric_constant[0][2] = 2.303; 2095 vert_dielectric_constant[0][2] = 3.9; 2096 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2097 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 2098 fringe_cap); 2099 2100 //Conservative projections 2101 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 2102 aspect_ratio[1][0] = 2.0; 2103 wire_width = wire_pitch[1][0] / 2; 2104 wire_thickness = aspect_ratio[1][0] * wire_width; 2105 wire_spacing = wire_pitch[1][0] - wire_width; 2106 barrier_thickness = 0.006; 2107 dishing_thickness = 0; 2108 alpha_scatter = 1; 2109 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 2110 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2111 ild_thickness[1][0] = 0.405; 2112 miller_value[1][0] = 1.5; 2113 horiz_dielectric_constant[1][0] = 2.734; 2114 vert_dielectric_constant[1][0] = 3.9; 2115 fringe_cap = 0.115e-15; 2116 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2117 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0], 2118 fringe_cap); 2119 2120 wire_pitch[1][1] = 4 * g_ip->F_sz_um; 2121 wire_width = wire_pitch[1][1] / 2; 2122 aspect_ratio[1][1] = 2.0; 2123 wire_thickness = aspect_ratio[1][1] * wire_width; 2124 wire_spacing = wire_pitch[1][1] - wire_width; 2125 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 2126 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2127 ild_thickness[1][1] = 0.405; 2128 miller_value[1][1] = 1.5; 2129 horiz_dielectric_constant[1][1] = 2.734; 2130 vert_dielectric_constant[1][1] = 3.9; 2131 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2132 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1], 2133 fringe_cap); 2134 2135 wire_pitch[1][2] = 8 * g_ip->F_sz_um; 2136 aspect_ratio[1][2] = 2.2; 2137 wire_width = wire_pitch[1][2] / 2; 2138 wire_thickness = aspect_ratio[1][2] * wire_width; 2139 wire_spacing = wire_pitch[1][2] - wire_width; 2140 dishing_thickness = 0.1 * wire_thickness; 2141 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 2142 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2143 ild_thickness[1][2] = 0.77; 2144 miller_value[1][2] = 1.5; 2145 horiz_dielectric_constant[1][2] = 2.734; 2146 vert_dielectric_constant[1][2] = 3.9; 2147 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2148 ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 2149 fringe_cap); 2150 //Nominal projections for commodity DRAM wordline/bitline 2151 wire_pitch[1][3] = 2 * 0.065; 2152 wire_c_per_micron[1][3] = 52.5e-15 / (256 * 2 * 0.065); 2153 wire_r_per_micron[1][3] = 12 / 0.065; 2154 } else if (tech == 45) { 2155 //Aggressive projections. 2156 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; 2157 aspect_ratio[0][0] = 3.0; 2158 wire_width = wire_pitch[0][0] / 2; 2159 wire_thickness = aspect_ratio[0][0] * wire_width; 2160 wire_spacing = wire_pitch[0][0] - wire_width; 2161 barrier_thickness = 0; 2162 dishing_thickness = 0; 2163 alpha_scatter = 1; 2164 wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2165 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2166 ild_thickness[0][0] = 0.315; 2167 miller_value[0][0] = 1.5; 2168 horiz_dielectric_constant[0][0] = 1.958; 2169 vert_dielectric_constant[0][0] = 3.9; 2170 fringe_cap = 0.115e-15; 2171 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2172 ild_thickness[0][0] , miller_value[0][0] , horiz_dielectric_constant[0][0] , vert_dielectric_constant[0][0] , 2173 fringe_cap); 2174 2175 wire_pitch[0][1] = 4 * g_ip->F_sz_um; 2176 wire_width = wire_pitch[0][1] / 2; 2177 aspect_ratio[0][1] = 3.0; 2178 wire_thickness = aspect_ratio[0][1] * wire_width; 2179 wire_spacing = wire_pitch[0][1] - wire_width; 2180 wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2181 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2182 ild_thickness[0][1] = 0.315; 2183 miller_value[0][1] = 1.5; 2184 horiz_dielectric_constant[0][1] = 1.958; 2185 vert_dielectric_constant[0][1] = 3.9; 2186 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2187 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1], 2188 fringe_cap); 2189 2190 wire_pitch[0][2] = 8 * g_ip->F_sz_um; 2191 aspect_ratio[0][2] = 3.0; 2192 wire_width = wire_pitch[0][2] / 2; 2193 wire_thickness = aspect_ratio[0][2] * wire_width; 2194 wire_spacing = wire_pitch[0][2] - wire_width; 2195 wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2196 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2197 ild_thickness[0][2] = 0.63; 2198 miller_value[0][2] = 1.5; 2199 horiz_dielectric_constant[0][2] = 1.958; 2200 vert_dielectric_constant[0][2] = 3.9; 2201 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2202 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 2203 fringe_cap); 2204 2205 //Conservative projections 2206 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 2207 aspect_ratio[1][0] = 2.0; 2208 wire_width = wire_pitch[1][0] / 2; 2209 wire_thickness = aspect_ratio[1][0] * wire_width; 2210 wire_spacing = wire_pitch[1][0] - wire_width; 2211 barrier_thickness = 0.004; 2212 dishing_thickness = 0; 2213 alpha_scatter = 1; 2214 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 2215 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2216 ild_thickness[1][0] = 0.315; 2217 miller_value[1][0] = 1.5; 2218 horiz_dielectric_constant[1][0] = 2.46; 2219 vert_dielectric_constant[1][0] = 3.9; 2220 fringe_cap = 0.115e-15; 2221 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2222 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0], 2223 fringe_cap); 2224 2225 wire_pitch[1][1] = 4 * g_ip->F_sz_um; 2226 wire_width = wire_pitch[1][1] / 2; 2227 aspect_ratio[1][1] = 2.0; 2228 wire_thickness = aspect_ratio[1][1] * wire_width; 2229 wire_spacing = wire_pitch[1][1] - wire_width; 2230 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 2231 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2232 ild_thickness[1][1] = 0.315; 2233 miller_value[1][1] = 1.5; 2234 horiz_dielectric_constant[1][1] = 2.46; 2235 vert_dielectric_constant[1][1] = 3.9; 2236 fringe_cap = 0.115e-15; 2237 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2238 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1], 2239 fringe_cap); 2240 2241 wire_pitch[1][2] = 8 * g_ip->F_sz_um; 2242 aspect_ratio[1][2] = 2.2; 2243 wire_width = wire_pitch[1][2] / 2; 2244 wire_thickness = aspect_ratio[1][2] * wire_width; 2245 wire_spacing = wire_pitch[1][2] - wire_width; 2246 dishing_thickness = 0.1 * wire_thickness; 2247 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 2248 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2249 ild_thickness[1][2] = 0.55; 2250 miller_value[1][2] = 1.5; 2251 horiz_dielectric_constant[1][2] = 2.46; 2252 vert_dielectric_constant[1][2] = 3.9; 2253 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2254 ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 2255 fringe_cap); 2256 //Nominal projections for commodity DRAM wordline/bitline 2257 wire_pitch[1][3] = 2 * 0.045; 2258 wire_c_per_micron[1][3] = 37.5e-15 / (256 * 2 * 0.045); 2259 wire_r_per_micron[1][3] = 12 / 0.045; 2260 } else if (tech == 32) { 2261 //Aggressive projections. 2262 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um; 2263 aspect_ratio[0][0] = 3.0; 2264 wire_width = wire_pitch[0][0] / 2; 2265 wire_thickness = aspect_ratio[0][0] * wire_width; 2266 wire_spacing = wire_pitch[0][0] - wire_width; 2267 barrier_thickness = 0; 2268 dishing_thickness = 0; 2269 alpha_scatter = 1; 2270 wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2271 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2272 ild_thickness[0][0] = 0.21; 2273 miller_value[0][0] = 1.5; 2274 horiz_dielectric_constant[0][0] = 1.664; 2275 vert_dielectric_constant[0][0] = 3.9; 2276 fringe_cap = 0.115e-15; 2277 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2278 ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], vert_dielectric_constant[0][0], 2279 fringe_cap); 2280 2281 wire_pitch[0][1] = 4 * g_ip->F_sz_um; 2282 wire_width = wire_pitch[0][1] / 2; 2283 aspect_ratio[0][1] = 3.0; 2284 wire_thickness = aspect_ratio[0][1] * wire_width; 2285 wire_spacing = wire_pitch[0][1] - wire_width; 2286 wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2287 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2288 ild_thickness[0][1] = 0.21; 2289 miller_value[0][1] = 1.5; 2290 horiz_dielectric_constant[0][1] = 1.664; 2291 vert_dielectric_constant[0][1] = 3.9; 2292 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2293 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1], 2294 fringe_cap); 2295 2296 wire_pitch[0][2] = 8 * g_ip->F_sz_um; 2297 aspect_ratio[0][2] = 3.0; 2298 wire_width = wire_pitch[0][2] / 2; 2299 wire_thickness = aspect_ratio[0][2] * wire_width; 2300 wire_spacing = wire_pitch[0][2] - wire_width; 2301 wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2302 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2303 ild_thickness[0][2] = 0.42; 2304 miller_value[0][2] = 1.5; 2305 horiz_dielectric_constant[0][2] = 1.664; 2306 vert_dielectric_constant[0][2] = 3.9; 2307 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2308 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 2309 fringe_cap); 2310 2311 //Conservative projections 2312 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 2313 aspect_ratio[1][0] = 2.0; 2314 wire_width = wire_pitch[1][0] / 2; 2315 wire_thickness = aspect_ratio[1][0] * wire_width; 2316 wire_spacing = wire_pitch[1][0] - wire_width; 2317 barrier_thickness = 0.003; 2318 dishing_thickness = 0; 2319 alpha_scatter = 1; 2320 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 2321 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2322 ild_thickness[1][0] = 0.21; 2323 miller_value[1][0] = 1.5; 2324 horiz_dielectric_constant[1][0] = 2.214; 2325 vert_dielectric_constant[1][0] = 3.9; 2326 fringe_cap = 0.115e-15; 2327 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2328 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0], 2329 fringe_cap); 2330 2331 wire_pitch[1][1] = 4 * g_ip->F_sz_um; 2332 aspect_ratio[1][1] = 2.0; 2333 wire_width = wire_pitch[1][1] / 2; 2334 wire_thickness = aspect_ratio[1][1] * wire_width; 2335 wire_spacing = wire_pitch[1][1] - wire_width; 2336 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 2337 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2338 ild_thickness[1][1] = 0.21; 2339 miller_value[1][1] = 1.5; 2340 horiz_dielectric_constant[1][1] = 2.214; 2341 vert_dielectric_constant[1][1] = 3.9; 2342 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2343 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1], 2344 fringe_cap); 2345 2346 wire_pitch[1][2] = 8 * g_ip->F_sz_um; 2347 aspect_ratio[1][2] = 2.2; 2348 wire_width = wire_pitch[1][2] / 2; 2349 wire_thickness = aspect_ratio[1][2] * wire_width; 2350 wire_spacing = wire_pitch[1][2] - wire_width; 2351 dishing_thickness = 0.1 * wire_thickness; 2352 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 2353 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2354 ild_thickness[1][2] = 0.385; 2355 miller_value[1][2] = 1.5; 2356 horiz_dielectric_constant[1][2] = 2.214; 2357 vert_dielectric_constant[1][2] = 3.9; 2358 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2359 ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 2360 fringe_cap); 2361 //Nominal projections for commodity DRAM wordline/bitline 2362 wire_pitch[1][3] = 2 * 0.032;//micron 2363 wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.032);//F/micron 2364 wire_r_per_micron[1][3] = 12 / 0.032;//ohm/micron 2365 } else if (tech == 22) { 2366 //Aggressive projections. 2367 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//local 2368 aspect_ratio[0][0] = 3.0; 2369 wire_width = wire_pitch[0][0] / 2; 2370 wire_thickness = aspect_ratio[0][0] * wire_width; 2371 wire_spacing = wire_pitch[0][0] - wire_width; 2372 barrier_thickness = 0; 2373 dishing_thickness = 0; 2374 alpha_scatter = 1; 2375 wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2376 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2377 ild_thickness[0][0] = 0.15; 2378 miller_value[0][0] = 1.5; 2379 horiz_dielectric_constant[0][0] = 1.414; 2380 vert_dielectric_constant[0][0] = 3.9; 2381 fringe_cap = 0.115e-15; 2382 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2383 ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], vert_dielectric_constant[0][0], 2384 fringe_cap); 2385 2386 wire_pitch[0][1] = 4 * g_ip->F_sz_um;//semi-global 2387 wire_width = wire_pitch[0][1] / 2; 2388 aspect_ratio[0][1] = 3.0; 2389 wire_thickness = aspect_ratio[0][1] * wire_width; 2390 wire_spacing = wire_pitch[0][1] - wire_width; 2391 wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2392 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2393 ild_thickness[0][1] = 0.15; 2394 miller_value[0][1] = 1.5; 2395 horiz_dielectric_constant[0][1] = 1.414; 2396 vert_dielectric_constant[0][1] = 3.9; 2397 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2398 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1], 2399 fringe_cap); 2400 2401 wire_pitch[0][2] = 8 * g_ip->F_sz_um;//global 2402 aspect_ratio[0][2] = 3.0; 2403 wire_width = wire_pitch[0][2] / 2; 2404 wire_thickness = aspect_ratio[0][2] * wire_width; 2405 wire_spacing = wire_pitch[0][2] - wire_width; 2406 wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2407 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2408 ild_thickness[0][2] = 0.3; 2409 miller_value[0][2] = 1.5; 2410 horiz_dielectric_constant[0][2] = 1.414; 2411 vert_dielectric_constant[0][2] = 3.9; 2412 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2413 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 2414 fringe_cap); 2415 2416 //Conservative projections 2417 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 2418 aspect_ratio[1][0] = 2.0; 2419 wire_width = wire_pitch[1][0] / 2; 2420 wire_thickness = aspect_ratio[1][0] * wire_width; 2421 wire_spacing = wire_pitch[1][0] - wire_width; 2422 barrier_thickness = 0.003; 2423 dishing_thickness = 0; 2424 alpha_scatter = 1.05; 2425 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 2426 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2427 ild_thickness[1][0] = 0.15; 2428 miller_value[1][0] = 1.5; 2429 horiz_dielectric_constant[1][0] = 2.104; 2430 vert_dielectric_constant[1][0] = 3.9; 2431 fringe_cap = 0.115e-15; 2432 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2433 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0], 2434 fringe_cap); 2435 2436 wire_pitch[1][1] = 4 * g_ip->F_sz_um; 2437 wire_width = wire_pitch[1][1] / 2; 2438 aspect_ratio[1][1] = 2.0; 2439 wire_thickness = aspect_ratio[1][1] * wire_width; 2440 wire_spacing = wire_pitch[1][1] - wire_width; 2441 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 2442 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2443 ild_thickness[1][1] = 0.15; 2444 miller_value[1][1] = 1.5; 2445 horiz_dielectric_constant[1][1] = 2.104; 2446 vert_dielectric_constant[1][1] = 3.9; 2447 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2448 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1], 2449 fringe_cap); 2450 2451 wire_pitch[1][2] = 8 * g_ip->F_sz_um; 2452 aspect_ratio[1][2] = 2.2; 2453 wire_width = wire_pitch[1][2] / 2; 2454 wire_thickness = aspect_ratio[1][2] * wire_width; 2455 wire_spacing = wire_pitch[1][2] - wire_width; 2456 dishing_thickness = 0.1 * wire_thickness; 2457 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 2458 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2459 ild_thickness[1][2] = 0.275; 2460 miller_value[1][2] = 1.5; 2461 horiz_dielectric_constant[1][2] = 2.104; 2462 vert_dielectric_constant[1][2] = 3.9; 2463 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2464 ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 2465 fringe_cap); 2466 //Nominal projections for commodity DRAM wordline/bitline 2467 wire_pitch[1][3] = 2 * 0.022;//micron 2468 wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.022);//F/micron 2469 wire_r_per_micron[1][3] = 12 / 0.022;//ohm/micron 2470 } 2471 2472 else if (tech == 16) { 2473 //Aggressive projections. 2474 wire_pitch[0][0] = 2.5 * g_ip->F_sz_um;//local 2475 aspect_ratio[0][0] = 3.0; 2476 wire_width = wire_pitch[0][0] / 2; 2477 wire_thickness = aspect_ratio[0][0] * wire_width; 2478 wire_spacing = wire_pitch[0][0] - wire_width; 2479 barrier_thickness = 0; 2480 dishing_thickness = 0; 2481 alpha_scatter = 1; 2482 wire_r_per_micron[0][0] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2483 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2484 ild_thickness[0][0] = 0.108; 2485 miller_value[0][0] = 1.5; 2486 horiz_dielectric_constant[0][0] = 1.202; 2487 vert_dielectric_constant[0][0] = 3.9; 2488 fringe_cap = 0.115e-15; 2489 wire_c_per_micron[0][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2490 ild_thickness[0][0], miller_value[0][0], horiz_dielectric_constant[0][0], vert_dielectric_constant[0][0], 2491 fringe_cap); 2492 2493 wire_pitch[0][1] = 4 * g_ip->F_sz_um;//semi-global 2494 aspect_ratio[0][1] = 3.0; 2495 wire_width = wire_pitch[0][1] / 2; 2496 wire_thickness = aspect_ratio[0][1] * wire_width; 2497 wire_spacing = wire_pitch[0][1] - wire_width; 2498 wire_r_per_micron[0][1] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2499 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2500 ild_thickness[0][1] = 0.108; 2501 miller_value[0][1] = 1.5; 2502 horiz_dielectric_constant[0][1] = 1.202; 2503 vert_dielectric_constant[0][1] = 3.9; 2504 wire_c_per_micron[0][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2505 ild_thickness[0][1], miller_value[0][1], horiz_dielectric_constant[0][1], vert_dielectric_constant[0][1], 2506 fringe_cap); 2507 2508 wire_pitch[0][2] = 8 * g_ip->F_sz_um;//global 2509 aspect_ratio[0][2] = 3.0; 2510 wire_width = wire_pitch[0][2] / 2; 2511 wire_thickness = aspect_ratio[0][2] * wire_width; 2512 wire_spacing = wire_pitch[0][2] - wire_width; 2513 wire_r_per_micron[0][2] = wire_resistance(BULK_CU_RESISTIVITY, wire_width, 2514 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2515 ild_thickness[0][2] = 0.216; 2516 miller_value[0][2] = 1.5; 2517 horiz_dielectric_constant[0][2] = 1.202; 2518 vert_dielectric_constant[0][2] = 3.9; 2519 wire_c_per_micron[0][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2520 ild_thickness[0][2], miller_value[0][2], horiz_dielectric_constant[0][2], vert_dielectric_constant[0][2], 2521 fringe_cap); 2522 2523 //Conservative projections 2524 wire_pitch[1][0] = 2.5 * g_ip->F_sz_um; 2525 aspect_ratio[1][0] = 2.0; 2526 wire_width = wire_pitch[1][0] / 2; 2527 wire_thickness = aspect_ratio[1][0] * wire_width; 2528 wire_spacing = wire_pitch[1][0] - wire_width; 2529 barrier_thickness = 0.002; 2530 dishing_thickness = 0; 2531 alpha_scatter = 1.05; 2532 wire_r_per_micron[1][0] = wire_resistance(CU_RESISTIVITY, wire_width, 2533 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2534 ild_thickness[1][0] = 0.108; 2535 miller_value[1][0] = 1.5; 2536 horiz_dielectric_constant[1][0] = 1.998; 2537 vert_dielectric_constant[1][0] = 3.9; 2538 fringe_cap = 0.115e-15; 2539 wire_c_per_micron[1][0] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2540 ild_thickness[1][0], miller_value[1][0], horiz_dielectric_constant[1][0], vert_dielectric_constant[1][0], 2541 fringe_cap); 2542 2543 wire_pitch[1][1] = 4 * g_ip->F_sz_um; 2544 wire_width = wire_pitch[1][1] / 2; 2545 aspect_ratio[1][1] = 2.0; 2546 wire_thickness = aspect_ratio[1][1] * wire_width; 2547 wire_spacing = wire_pitch[1][1] - wire_width; 2548 wire_r_per_micron[1][1] = wire_resistance(CU_RESISTIVITY, wire_width, 2549 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2550 ild_thickness[1][1] = 0.108; 2551 miller_value[1][1] = 1.5; 2552 horiz_dielectric_constant[1][1] = 1.998; 2553 vert_dielectric_constant[1][1] = 3.9; 2554 wire_c_per_micron[1][1] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2555 ild_thickness[1][1], miller_value[1][1], horiz_dielectric_constant[1][1], vert_dielectric_constant[1][1], 2556 fringe_cap); 2557 2558 wire_pitch[1][2] = 8 * g_ip->F_sz_um; 2559 aspect_ratio[1][2] = 2.2; 2560 wire_width = wire_pitch[1][2] / 2; 2561 wire_thickness = aspect_ratio[1][2] * wire_width; 2562 wire_spacing = wire_pitch[1][2] - wire_width; 2563 dishing_thickness = 0.1 * wire_thickness; 2564 wire_r_per_micron[1][2] = wire_resistance(CU_RESISTIVITY, wire_width, 2565 wire_thickness, barrier_thickness, dishing_thickness, alpha_scatter); 2566 ild_thickness[1][2] = 0.198; 2567 miller_value[1][2] = 1.5; 2568 horiz_dielectric_constant[1][2] = 1.998; 2569 vert_dielectric_constant[1][2] = 3.9; 2570 wire_c_per_micron[1][2] = wire_capacitance(wire_width, wire_thickness, wire_spacing, 2571 ild_thickness[1][2], miller_value[1][2], horiz_dielectric_constant[1][2], vert_dielectric_constant[1][2], 2572 fringe_cap); 2573 //Nominal projections for commodity DRAM wordline/bitline 2574 wire_pitch[1][3] = 2 * 0.016;//micron 2575 wire_c_per_micron[1][3] = 31e-15 / (256 * 2 * 0.016);//F/micron 2576 wire_r_per_micron[1][3] = 12 / 0.016;//ohm/micron 2577 } 2578 g_tp.wire_local.pitch += curr_alpha * 2579 wire_pitch[g_ip->ic_proj_type] 2580 [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 2581 g_tp.wire_local.R_per_um += curr_alpha * 2582 wire_r_per_micron[g_ip->ic_proj_type] 2583 [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 2584 g_tp.wire_local.C_per_um += curr_alpha * 2585 wire_c_per_micron[g_ip->ic_proj_type] 2586 [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 2587 g_tp.wire_local.aspect_ratio += curr_alpha * 2588 aspect_ratio[g_ip->ic_proj_type] 2589 [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 2590 g_tp.wire_local.ild_thickness += curr_alpha * 2591 ild_thickness[g_ip->ic_proj_type] 2592 [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 2593 g_tp.wire_local.miller_value += curr_alpha * 2594 miller_value[g_ip->ic_proj_type] 2595 [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 2596 g_tp.wire_local.horiz_dielectric_constant += curr_alpha * 2597 horiz_dielectric_constant[g_ip->ic_proj_type] 2598 [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 2599 g_tp.wire_local.vert_dielectric_constant += curr_alpha * 2600 vert_dielectric_constant[g_ip->ic_proj_type] 2601 [(ram_cell_tech_type == comm_dram) ? 3 : 0]; 2602 2603 g_tp.wire_inside_mat.pitch += curr_alpha * 2604 wire_pitch[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 2605 g_tp.wire_inside_mat.R_per_um += curr_alpha * 2606 wire_r_per_micron[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 2607 g_tp.wire_inside_mat.C_per_um += curr_alpha * 2608 wire_c_per_micron[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 2609 g_tp.wire_inside_mat.aspect_ratio += curr_alpha * 2610 aspect_ratio[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 2611 g_tp.wire_inside_mat.ild_thickness += curr_alpha * 2612 ild_thickness[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 2613 g_tp.wire_inside_mat.miller_value += curr_alpha * 2614 miller_value[g_ip->ic_proj_type][g_ip->wire_is_mat_type]; 2615 g_tp.wire_inside_mat.horiz_dielectric_constant += curr_alpha * 2616 horiz_dielectric_constant[g_ip->ic_proj_type] 2617 [g_ip->wire_is_mat_type]; 2618 g_tp.wire_inside_mat.vert_dielectric_constant += curr_alpha * 2619 vert_dielectric_constant [g_ip->ic_proj_type] 2620 [g_ip->wire_is_mat_type]; 2621 2622 g_tp.wire_outside_mat.pitch += curr_alpha * 2623 wire_pitch[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 2624 g_tp.wire_outside_mat.R_per_um += curr_alpha * 2625 wire_r_per_micron[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 2626 g_tp.wire_outside_mat.C_per_um += curr_alpha * 2627 wire_c_per_micron[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 2628 g_tp.wire_outside_mat.aspect_ratio += curr_alpha * 2629 aspect_ratio[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 2630 g_tp.wire_outside_mat.ild_thickness += curr_alpha * 2631 ild_thickness[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 2632 g_tp.wire_outside_mat.miller_value += curr_alpha * 2633 miller_value[g_ip->ic_proj_type][g_ip->wire_os_mat_type]; 2634 g_tp.wire_outside_mat.horiz_dielectric_constant += curr_alpha * 2635 horiz_dielectric_constant[g_ip->ic_proj_type] 2636 [g_ip->wire_os_mat_type]; 2637 g_tp.wire_outside_mat.vert_dielectric_constant += curr_alpha * 2638 vert_dielectric_constant [g_ip->ic_proj_type] 2639 [g_ip->wire_os_mat_type]; 2640 2641 g_tp.unit_len_wire_del = g_tp.wire_inside_mat.R_per_um * 2642 g_tp.wire_inside_mat.C_per_um / 2; 2643 2644 g_tp.sense_delay += curr_alpha * SENSE_AMP_D; 2645 g_tp.sense_dy_power += curr_alpha * SENSE_AMP_P; 2646 2647 } 2648 g_tp.fringe_cap = fringe_cap; 2649 2650 double rd = tr_R_on(g_tp.min_w_nmos_, NCH, 1); 2651 double p_to_n_sizing_r = pmos_to_nmos_sz_ratio(); 2652 double c_load = gate_C(g_tp.min_w_nmos_ * (1 + p_to_n_sizing_r), 0.0); 2653 double tf = rd * c_load; 2654 g_tp.kinv = horowitz(0, tf, 0.5, 0.5, RISE); 2655 double KLOAD = 1; 2656 c_load = KLOAD * (drain_C_(g_tp.min_w_nmos_, NCH, 1, 1, g_tp.cell_h_def) + 2657 drain_C_(g_tp.min_w_nmos_ * p_to_n_sizing_r, PCH, 1, 1, g_tp.cell_h_def) + 2658 gate_C(g_tp.min_w_nmos_ * 4 * (1 + p_to_n_sizing_r), 0.0)); 2659 tf = rd * c_load; 2660 g_tp.FO4 = horowitz(0, tf, 0.5, 0.5, RISE); 2661} 2662 2663