basic_components.h revision 10152:52c552138ba1 
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31
32#ifndef BASIC_COMPONENTS_H_
33#define BASIC_COMPONENTS_H_
34
35#include <vector>
36
37#include "XML_Parse.h"
38#include "parameter.h"
39
40const double cdb_overhead = 1.1;
41
42enum FU_type {
43    FPU,
44    ALU,
45    MUL
46};
47
48enum Core_type {
49        OOO,
50        Inorder
51};
52
53enum Renaming_type {
54    RAMbased,
55        CAMbased
56};
57
58enum Scheduler_type {
59    PhysicalRegFile,
60        ReservationStation
61};
62
63enum cache_level {
64    L2,
65    L3,
66    L1Directory,
67    L2Directory
68};
69
70enum MemoryCtrl_type {
71        MC,    //memory controller
72        FLASHC //flash controller
73};
74
75enum Dir_type {
76        ST,//shadowed tag
77        DC,//directory cache
78        SBT,//static bank tag
79        NonDir
80
81};
82
83enum Cache_policy {
84        Write_through,
85        Write_back
86};
87
88enum Device_ty {
89        Core_device,
90        Uncore_device,
91        LLC_device
92};
93
94class statsComponents
95{
96  public:
97    double access;
98    double hit;
99    double miss;
100
101    statsComponents() : access(0), hit(0), miss(0)  {}
102    statsComponents(const statsComponents & obj) { *this = obj; }
103    statsComponents & operator=(const statsComponents & rhs)
104    {
105      access = rhs.access;
106      hit = rhs.hit;
107      miss  = rhs.miss;
108      return *this;
109    }
110    void reset() { access = 0; hit = 0; miss = 0;}
111
112    friend statsComponents operator+(const statsComponents & x, const statsComponents & y);
113    friend statsComponents operator*(const statsComponents & x, double const * const y);
114};
115
116class statsDef
117{
118  public:
119    statsComponents readAc;
120    statsComponents writeAc;
121    statsComponents searchAc;
122
123    statsDef() : readAc(), writeAc(),searchAc() { }
124    void reset() { readAc.reset(); writeAc.reset();searchAc.reset();}
125
126    friend statsDef operator+(const statsDef & x, const statsDef & y);
127    friend statsDef operator*(const statsDef & x, double const * const y);
128};
129
130double longer_channel_device_reduction(
131                enum Device_ty device_ty=Core_device,
132                enum Core_type core_ty=Inorder);
133
134class CoreDynParam {
135public:
136        CoreDynParam(){};
137        CoreDynParam(ParseXML *XML_interface, int ithCore_);
138        //    :XML(XML_interface),
139        //     ithCore(ithCore_)
140        //     core_ty(inorder),
141        //     rm_ty(CAMbased),
142        //     scheu_ty(PhysicalRegFile),
143        //     clockRate(1e9),//1GHz
144        //     arch_ireg_width(32),
145        //     arch_freg_width(32),
146        //     phy_ireg_width(128),
147        //     phy_freg_width(128),
148        //     perThreadState(8),
149        //     globalCheckpoint(32),
150        //     instructionLength(32){};
151        //ParseXML * XML;
152        bool opt_local;
153        bool x86;
154        bool Embedded;
155    enum Core_type  core_ty;
156        enum Renaming_type rm_ty;
157    enum Scheduler_type scheu_ty;
158    double clockRate,executionTime;
159    int  arch_ireg_width, arch_freg_width, phy_ireg_width, phy_freg_width;
160    int  num_IRF_entry, num_FRF_entry, num_ifreelist_entries, num_ffreelist_entries;
161    int  fetchW, decodeW,issueW,peak_issueW, commitW,peak_commitW, predictionW, fp_issueW, fp_decodeW;
162    int  perThreadState, globalCheckpoint, instruction_length, pc_width, opcode_length, micro_opcode_length;
163    int  num_hthreads, pipeline_stages, fp_pipeline_stages, num_pipelines, num_fp_pipelines;
164    int  num_alus, num_muls;
165    double num_fpus;
166    int  int_data_width, fp_data_width,v_address_width, p_address_width;
167    double pipeline_duty_cycle, total_cycles, busy_cycles, idle_cycles;
168    bool regWindowing,multithreaded;
169    double pppm_lkg_multhread[4];
170        double IFU_duty_cycle,BR_duty_cycle,LSU_duty_cycle,MemManU_I_duty_cycle,
171               MemManU_D_duty_cycle, ALU_duty_cycle,MUL_duty_cycle,
172               FPU_duty_cycle, ALU_cdb_duty_cycle,MUL_cdb_duty_cycle,
173               FPU_cdb_duty_cycle;
174    ~CoreDynParam(){};
175};
176
177class CacheDynParam {
178public:
179        CacheDynParam(){};
180        CacheDynParam(ParseXML *XML_interface, int ithCache_);
181    string name;
182        enum Dir_type    dir_ty;
183        double clockRate,executionTime;
184    double    capacity, blockW, assoc, nbanks;
185    double throughput, latency;
186    double duty_cycle, dir_duty_cycle;
187    //double duty_cycle;
188    int missb_size, fu_size, prefetchb_size, wbb_size;
189    ~CacheDynParam(){};
190};
191
192class MCParam {
193public:
194        MCParam(){};
195        MCParam(ParseXML *XML_interface, int ithCache_);
196    string name;
197    double  clockRate,num_mcs, peakDataTransferRate, num_channels;
198    //  double mcTEPowerperGhz;
199    //	double mcPHYperGbit;
200    //	double area;
201    int	   llcBlockSize, dataBusWidth, addressBusWidth;
202    int    opcodeW;
203    int    memAccesses;
204    int    memRank;
205    int    type;
206    double frontend_duty_cycle, duty_cycle, perc_load;
207    double executionTime, reads, writes;
208    bool   LVDS, withPHY;
209
210    ~MCParam(){};
211};
212
213class NoCParam {
214public:
215        NoCParam(){};
216        NoCParam(ParseXML *XML_interface, int ithCache_);
217    string name;
218    double  clockRate;
219    int	   flit_size;
220    int    input_ports, output_ports, min_ports, global_linked_ports;
221    int    virtual_channel_per_port,input_buffer_entries_per_vc;
222    int    horizontal_nodes,vertical_nodes, total_nodes;
223    double executionTime, total_access, link_throughput,link_latency,
224                   duty_cycle, chip_coverage, route_over_perc;
225    bool   has_global_link, type;
226
227    ~NoCParam(){};
228};
229
230class ProcParam {
231public:
232        ProcParam(){};
233        ProcParam(ParseXML *XML_interface, int ithCache_);
234    string name;
235    int  numCore, numL2, numL3, numNOC, numL1Dir, numL2Dir,numMC, numMCChannel;
236    bool homoCore, homoL2, homoL3, homoNOC, homoL1Dir, homoL2Dir;
237
238    ~ProcParam(){};
239};
240
241class NIUParam {
242public:
243        NIUParam(){};
244        NIUParam(ParseXML *XML_interface, int ithCache_);
245    string name;
246    double  clockRate;
247    int    num_units;
248    int    type;
249    double duty_cycle, perc_load;
250    ~NIUParam(){};
251};
252
253class PCIeParam {
254public:
255        PCIeParam(){};
256        PCIeParam(ParseXML *XML_interface, int ithCache_);
257    string name;
258    double  clockRate;
259    int    num_channels, num_units;
260    bool   withPHY;
261    int    type;
262    double duty_cycle, perc_load;
263    ~PCIeParam(){};
264};
265#endif /* BASIC_COMPONENTS_H_ */
266