TG11LVT.model revision 10447
1# WARNING: Most commercial fabs will not be happy if you release their exact
2# process information! If you derive these numbers through SPICE models,
3# the process design kit, or any other confidential material, please round-off
4# the values and leave the process name unidentifiable by fab (i.e. call it
5# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
6# rule may not apply for open processes, but you may want to check.
7
8# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
9
10# This file contains the model for a Tri-Gate (Multi-Gate) 11nm LVT process
11Name = TG11LVT
12
13# Supply voltage used in the circuit and for characterizations (V)
14Vdd = 0.6
15# Temperature (K)
16Temperature = 340
17
18# =============================================================================
19# Parameters for transistors
20# =============================================================================
21
22# Contacted gate pitch (m)
23Gate->PitchContacted = 0.080e-6
24
25# Min gate width (m)
26Gate->MinWidth = 0.080e-6
27
28# Gate cap per unit width (F/m)
29Gate->CapPerWidth = 0.61e-9
30# Source/Drain cap per unit width (F/m)
31Drain->CapPerWidth = 0.56e-9
32
33# Parameters characterization temperature (K)
34Nmos->CharacterizedTemperature = 300.0
35Pmos->CharacterizedTemperature = 300.0
36
37#------------------------------------------------------------------------------
38# I_Eff definition in Na, IEDM 2002
39#       I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
40#       R_EFF = VDD / I_EFF * 1 / (2 ln(2))
41# This is generally more accurate for when the delay is input transition time
42# limited
43#------------------------------------------------------------------------------
44# Effective resistance (Ohm-m)
45Nmos->EffResWidth = 1.16e-3
46Pmos->EffResWidth = 1.28e-3
47
48#------------------------------------------------------------------------------
49# The ratio of extra effective resistance with each additional stacked
50# transistor
51#       EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
52# For example, inverter has an normalized effective drive resistance of 1.0.
53# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
54# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
55# works relatively well up to 4 stacks. This value will change depending on the
56# VDD used. 
57#------------------------------------------------------------------------------
58# Effective resistance stack ratio
59Nmos->EffResStackRatio = 0.89
60Pmos->EffResStackRatio = 0.86
61
62#------------------------------------------------------------------------------
63# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
64#       Minimum off current is used in technologies where I_OFF stops scaling
65#       with transistor width below some threshold
66#------------------------------------------------------------------------------
67# Off current per width (A/m)
68Nmos->OffCurrent = 100.0e-3
69Pmos->OffCurrent = 100.0e-3
70# Minimum off current (A)
71Nmos->MinOffCurrent = 40e-9
72Pmos->MinOffCurrent = 4e-9
73
74# Subthreshold swing (V/dec)        
75Nmos->SubthresholdSwing = 0.080
76Pmos->SubthresholdSwing = 0.080
77# DIBL factor (V/V)
78Nmos->DIBL = 0.125
79Pmos->DIBL = 0.125
80# Subthreshold temperature swing (K/dec)
81Nmos->SubthresholdTempSwing = 100.0
82Pmos->SubthresholdTempSwing = 100.0
83#------------------------------------------------------------------------------
84
85# =============================================================================
86# Parameters for interconnect
87# =============================================================================
88
89Wire->AvailableLayers = [Metal1,Local,Intermediate,Semiglobal,Global]
90
91# Metal 1 Wire (used for std cell routing only)
92# Min width (m)
93Wire->Metal1->MinWidth = 20e-9
94# Min spacing (m)
95Wire->Metal1->MinSpacing = 20e-9
96# Resistivity (Ohm-m)
97Wire->Metal1->Resistivity = 6.8e-8
98# Metal thickness (m)
99Wire->Metal1->MetalThickness = 35.0e-9
100# Dielectric thickness (m)
101Wire->Metal1->DielectricThickness = 35.0e-9
102# Dielectric constant
103Wire->Metal1->DielectricConstant = 3.00
104
105# Local wire, 1.0X of the M1 pitch
106# Min width (m)
107Wire->Local->MinWidth = 20e-9
108# Min spacing (m)
109Wire->Local->MinSpacing = 20e-9
110# Resistivity (Ohm-m)
111Wire->Local->Resistivity = 6.8e-8
112# Metal thickness (m)
113Wire->Local->MetalThickness = 35.0e-9
114# Dielectric thickness (m)
115Wire->Local->DielectricThickness = 35.0e-9
116# Dielectric constant
117Wire->Local->DielectricConstant = 3.00
118
119# Intermediate wire, 2.0X the M1 pitch
120# Min width (m)
121Wire->Intermediate->MinWidth = 40e-9
122# Min spacing (m)
123Wire->Intermediate->MinSpacing = 40e-9
124# Resistivity (Ohm-m)
125Wire->Intermediate->Resistivity = 4.50e-8
126# Metal thickness (m)
127Wire->Intermediate->MetalThickness = 70.0e-9
128# Dielectric thickness (m)
129Wire->Intermediate->DielectricThickness = 70.0e-9
130# Dielectric constant
131Wire->Intermediate->DielectricConstant = 2.80
132
133# Semiglobal wire, 4.0X the M1 pitch
134# Min width (m)
135Wire->Semiglobal->MinWidth = 80e-9
136# Min spacing (m)
137Wire->Semiglobal->MinSpacing = 80e-9
138# Resistivity (Ohm-m)
139Wire->Semiglobal->Resistivity = 2.80e-8
140# Metal thickness (m)
141Wire->Semiglobal->MetalThickness = 150.0e-9
142# Dielectric thickness (m)
143Wire->Semiglobal->DielectricThickness = 150.0e-9
144# Dielectric constant
145Wire->Semiglobal->DielectricConstant = 2.60      
146
147# Global wire, 8.0X the M1 pitch
148# Min width (m)
149Wire->Global->MinWidth = 160e-9
150# Min spacing (m)
151Wire->Global->MinSpacing = 160e-9
152# Resistivity (Ohm-m)
153Wire->Global->Resistivity = 2.30e-8
154# Metal thickness (m)
155Wire->Global->MetalThickness = 280e-9
156# Dielectric thickness (m)
157Wire->Global->DielectricThickness = 250e-9
158# Dielectric constant
159Wire->Global->DielectricConstant = 2.60
160
161# =============================================================================
162# Parameters for Standard Cells
163# =============================================================================
164
165# The height of the standard cell is usually a multiple of the vertical
166# M1 pitch (tracks). By definition, an X1 size cell has transistors
167# that fit exactly in the given cell height without folding, or leaving
168# any wasted vertical area
169
170# Reasonable values for the number of M1 tracks that we have seen are 8-14
171StdCell->Tracks = 11
172# Height overhead due to supply rails, well spacing, etc. Note that this will grow
173# if the height of the standard cell decreases!
174StdCell->HeightOverheadFactor = 1.400
175
176# Sets the available sizes of each standard cell. Keep in mind that
177# 1.0 is the biggest cell without any transistor folding
178StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
179
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