1# Copyright (c) 2012 Massachusetts Institute of Technology
2#
3# Permission is hereby granted, free of charge, to any person obtaining a copy
4# of this software and associated documentation files (the "Software"), to deal
5# in the Software without restriction, including without limitation the rights
6# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
7# copies of the Software, and to permit persons to whom the Software is
8# furnished to do so, subject to the following conditions:
9# 
10# The above copyright notice and this permission notice shall be included in
11# all copies or substantial portions of the Software.
12# 
13# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
16# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
18# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
19# THE SOFTWARE.
20
21# WARNING: Most commercial fabs will not be happy if you release their exact
22# process information! If you derive these numbers through SPICE models,
23# the process design kit, or any other confidential material, please round-off
24# the values and leave the process name unidentifiable by fab (i.e. call it
25# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
26# rule may not apply for open processes, but you may want to check.
27
28# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
29
30# This file contains the model for a bulk 32nm LVT process
31Name = Bulk32LVT
32
33# Supply voltage used in the circuit and for characterizations (V)
34Vdd = 0.9
35# Temperature (K)
36Temperature = 340
37
38# =============================================================================
39# Parameters for transistors
40# =============================================================================
41
42# Contacted gate pitch (m)
43Gate->PitchContacted = 0.160e-6
44
45# Min gate width (m)
46Gate->MinWidth = 0.120e-6
47
48# Gate cap per unit width (F/m)
49Gate->CapPerWidth = 0.950e-9
50# Source/Drain cap per unit width (F/m)
51Drain->CapPerWidth = 0.640e-9
52
53# Parameters characterization temperature (K)
54Nmos->CharacterizedTemperature = 300.0
55Pmos->CharacterizedTemperature = 300.0
56
57#------------------------------------------------------------------------------
58# I_Eff definition in Na, IEDM 2002
59#       I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
60#       R_EFF = VDD / I_EFF * 1 / (2 ln(2))
61# This is generally accurate for when input and output transition times
62# are similar, which is a reasonable case after timing optimization
63#------------------------------------------------------------------------------
64# Effective resistance (Ohm-m)
65Nmos->EffResWidth = 0.890e-3               
66Pmos->EffResWidth = 1.270e-3
67
68#------------------------------------------------------------------------------
69# The ratio of extra effective resistance with each additional stacked
70# transistor
71#       EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
72# For example, inverter has an normalized effective drive resistance of 1.0.
73# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
74# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
75# works relatively well up to 4 stacks. This value will change depending on the
76# VDD used. 
77#------------------------------------------------------------------------------
78# Effective resistance stack ratio
79Nmos->EffResStackRatio = 0.78
80Pmos->EffResStackRatio = 0.66
81
82#------------------------------------------------------------------------------
83# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
84#       Minimum off current is used as a second fit point, since I_OFF often
85#       stops scaling with transistor width below some threshold
86#------------------------------------------------------------------------------
87# Off current per width (A/m)
88Nmos->OffCurrent = 100e-3
89Pmos->OffCurrent = 100e-3
90
91# Minimum off current (A)
92Nmos->MinOffCurrent = 100e-9
93Pmos->MinOffCurrent = 20e-9
94
95# Subthreshold swing (V/dec)        
96Nmos->SubthresholdSwing = 0.100
97Pmos->SubthresholdSwing = 0.100
98
99# DIBL factor (V/V)
100Nmos->DIBL = 0.150
101Pmos->DIBL = 0.150
102
103# Subthreshold leakage temperature swing (K/dec)
104Nmos->SubthresholdTempSwing = 100
105Pmos->SubthresholdTempSwing = 100
106#------------------------------------------------------------------------------
107
108# =============================================================================
109# Parameters for interconnect
110# =============================================================================
111
112Wire->AvailableLayers = [Metal1,Local,Intermediate,Global]
113
114# Metal 1 Wire (used for std cell routing only)
115# Min width (m)
116Wire->Metal1->MinWidth = 55e-9
117# Min spacing (m)
118Wire->Metal1->MinSpacing = 55e-9
119# Resistivity (Ohm-m)
120Wire->Metal1->Resistivity = 4.00e-8
121# Metal thickness (m)
122Wire->Metal1->MetalThickness = 100.0e-9
123# Dielectric thickness (m)
124Wire->Metal1->DielectricThickness = 100.0e-9
125# Dielectric constant
126Wire->Metal1->DielectricConstant = 3.2
127
128# Local wire, 1.0X of the M1 pitch
129# Min width (m)
130Wire->Local->MinWidth = 55e-9
131# Min spacing (m)
132Wire->Local->MinSpacing = 55e-9
133# Resistivity (Ohm-m)
134Wire->Local->Resistivity = 4.00e-8
135# Metal thickness (m)
136Wire->Local->MetalThickness = 100.0e-9
137# Dielectric thickness (m)
138Wire->Local->DielectricThickness = 100.0e-9
139# Dielectric constant
140Wire->Local->DielectricConstant = 3.2
141
142# Intermediate wire, 2.0X the M1 pitch
143# Min width (m)
144Wire->Intermediate->MinWidth = 110e-9
145# Min spacing (m)
146Wire->Intermediate->MinSpacing = 110e-9
147# Resistivity (Ohm-m)
148Wire->Intermediate->Resistivity = 2.60e-8
149# Metal thickness (m)
150Wire->Intermediate->MetalThickness = 200e-9
151# Dielectric thickness (m)
152Wire->Intermediate->DielectricThickness = 170e-9
153# Dielectric constant
154Wire->Intermediate->DielectricConstant = 3.00
155
156# Global wire, 3.0X the M1 pitch
157# Min width (m)
158Wire->Global->MinWidth = 160e-9
159# Min spacing (m)
160Wire->Global->MinSpacing = 160e-9
161# Resistivity (Ohm-m)
162Wire->Global->Resistivity = 2.30e-8
163# Metal thickness (m)
164Wire->Global->MetalThickness = 280e-9
165# Dielectric thickness (m)
166Wire->Global->DielectricThickness = 250e-9
167# Dielectric constant
168Wire->Global->DielectricConstant = 2.80
169
170# =============================================================================
171# Parameters for Standard Cells
172# =============================================================================
173
174# The height of the standard cell is usually a multiple of the vertical
175# M1 pitch (tracks). By definition, an X1 size cell has transistors
176# that fit exactly in the given cell height without folding, or leaving
177# any wasted vertical area
178
179# Reasonable values for the number of M1 tracks that we have seen are 8-14
180StdCell->Tracks = 11
181# Height overhead due to supply rails, well spacing, etc. Note that this will grow
182# if the height of the standard cell decreases!
183StdCell->HeightOverheadFactor = 1.400
184
185# Sets the available sizes of each standard cell. Keep in mind that
186# 1.0 is the biggest cell without any transistor folding
187StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
188
189