MOESI_hammer.py revision 7561:02a9a597fce4
16145SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 26386SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 36386SN/A# All rights reserved. 46386SN/A# 56386SN/A# Redistribution and use in source and binary forms, with or without 66386SN/A# modification, are permitted provided that the following conditions are 76386SN/A# met: redistributions of source code must retain the above copyright 86386SN/A# notice, this list of conditions and the following disclaimer; 96386SN/A# redistributions in binary form must reproduce the above copyright 106386SN/A# notice, this list of conditions and the following disclaimer in the 116386SN/A# documentation and/or other materials provided with the distribution; 126386SN/A# neither the name of the copyright holders nor the names of its 136386SN/A# contributors may be used to endorse or promote products derived from 146386SN/A# this software without specific prior written permission. 156386SN/A# 166386SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176386SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186386SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196386SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206386SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216386SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226386SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236386SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246386SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256386SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266386SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276386SN/A# 286145SN/A# Authors: Brad Beckmann 297553SN/A 307553SN/Aimport m5 317553SN/Afrom m5.objects import * 327553SN/Afrom m5.defines import buildEnv 337553SN/A 346145SN/A# 357553SN/A# Note: the L1 Cache latency is only used by the sequencer on fast path hits 367553SN/A# 376145SN/Aclass L1Cache(RubyCache): 387632SBrad.Beckmann@amd.com latency = 2 397632SBrad.Beckmann@amd.com 407553SN/A# 417553SN/A# Note: the L2 Cache latency is not currently used 426145SN/A# 437553SN/Aclass L2Cache(RubyCache): 447553SN/A latency = 10 457553SN/A 467553SN/Adef define_options(parser): 477553SN/A parser.add_option("--allow-atomic-migration", action="store_true", 487553SN/A help="allow migratory sharing for atomic only accessed blocks") 497553SN/A 507553SN/Adef create_system(options, system, piobus, dma_devices): 517553SN/A 527553SN/A if buildEnv['PROTOCOL'] != 'MOESI_hammer': 537553SN/A panic("This script requires the MOESI_hammer protocol to be built.") 547553SN/A 557553SN/A cpu_sequencers = [] 567553SN/A 577553SN/A # 587553SN/A # The ruby network creation expects the list of nodes in the system to be 597553SN/A # consistent with the NetDest list. Therefore the l1 controller nodes must be 606145SN/A # listed before the directory nodes and directory nodes before dma nodes, etc. 616145SN/A # 627553SN/A l1_cntrl_nodes = [] 636145SN/A dir_cntrl_nodes = [] 64 dma_cntrl_nodes = [] 65 66 # 67 # Must create the individual controllers before the network to ensure the 68 # controller constructors are called before the network constructor 69 # 70 71 for i in xrange(options.num_cpus): 72 # 73 # First create the Ruby objects associated with this cpu 74 # 75 l1i_cache = L1Cache(size = options.l1i_size, 76 assoc = options.l1i_assoc) 77 l1d_cache = L1Cache(size = options.l1d_size, 78 assoc = options.l1d_assoc) 79 l2_cache = L2Cache(size = options.l2_size, 80 assoc = options.l2_assoc) 81 82 cpu_seq = RubySequencer(version = i, 83 icache = l1i_cache, 84 dcache = l1d_cache, 85 physMemPort = system.physmem.port, 86 physmem = system.physmem) 87 88 if piobus != None: 89 cpu_seq.pio_port = piobus.port 90 91 l1_cntrl = L1Cache_Controller(version = i, 92 sequencer = cpu_seq, 93 L1IcacheMemory = l1i_cache, 94 L1DcacheMemory = l1d_cache, 95 L2cacheMemory = l2_cache, 96 no_mig_atomic = not \ 97 options.allow_atomic_migration) 98 99 exec("system.l1_cntrl%d = l1_cntrl" % i) 100 # 101 # Add controllers and sequencers to the appropriate lists 102 # 103 cpu_sequencers.append(cpu_seq) 104 l1_cntrl_nodes.append(l1_cntrl) 105 106 phys_mem_size = long(system.physmem.range.second) - \ 107 long(system.physmem.range.first) + 1 108 mem_module_size = phys_mem_size / options.num_dirs 109 110 for i in xrange(options.num_dirs): 111 # 112 # Create the Ruby objects associated with the directory controller 113 # 114 115 mem_cntrl = RubyMemoryControl(version = i) 116 117 dir_size = MemorySize('0B') 118 dir_size.value = mem_module_size 119 120 dir_cntrl = Directory_Controller(version = i, 121 directory = \ 122 RubyDirectoryMemory( \ 123 version = i, 124 size = dir_size, 125 use_map = options.use_map, 126 map_levels = \ 127 options.map_levels), 128 memBuffer = mem_cntrl) 129 130 exec("system.dir_cntrl%d = dir_cntrl" % i) 131 dir_cntrl_nodes.append(dir_cntrl) 132 133 for i, dma_device in enumerate(dma_devices): 134 # 135 # Create the Ruby objects associated with the dma controller 136 # 137 dma_seq = DMASequencer(version = i, 138 physMemPort = system.physmem.port, 139 physmem = system.physmem) 140 141 dma_cntrl = DMA_Controller(version = i, 142 dma_sequencer = dma_seq) 143 144 exec("system.dma_cntrl%d = dma_cntrl" % i) 145 if dma_device.type == 'MemTest': 146 system.dma_cntrl.dma_sequencer.port = dma_device.test 147 else: 148 system.dma_cntrl.dma_sequencer.port = dma_device.dma 149 dma_cntrl.dma_sequencer.port = dma_device.dma 150 dma_cntrl_nodes.append(dma_cntrl) 151 152 all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 153 154 return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 155