MOESI_hammer.py revision 7544:90c5eb6a5e66 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import m5
31from m5.objects import *
32from m5.defines import buildEnv
33
34#
35# Note: the L1 Cache latency is only used by the sequencer on fast path hits
36#
37class L1Cache(RubyCache):
38    latency = 3
39
40#
41# Note: the L2 Cache latency is not currently used
42#
43class L2Cache(RubyCache):
44    latency = 15
45
46def define_options(parser):
47    return
48
49def create_system(options, system, piobus, dma_devices):
50
51    if buildEnv['PROTOCOL'] != 'MOESI_hammer':
52        panic("This script requires the MOESI_hammer protocol to be built.")
53
54    cpu_sequencers = []
55
56    #
57    # The ruby network creation expects the list of nodes in the system to be
58    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
59    # listed before the directory nodes and directory nodes before dma nodes, etc.
60    #
61    l1_cntrl_nodes = []
62    dir_cntrl_nodes = []
63    dma_cntrl_nodes = []
64
65    #
66    # Must create the individual controllers before the network to ensure the
67    # controller constructors are called before the network constructor
68    #
69
70    for i in xrange(options.num_cpus):
71        #
72        # First create the Ruby objects associated with this cpu
73        #
74        l1i_cache = L1Cache(size = options.l1i_size,
75                            assoc = options.l1i_assoc)
76        l1d_cache = L1Cache(size = options.l1d_size,
77                            assoc = options.l1d_assoc)
78        l2_cache = L2Cache(size = options.l2_size,
79                           assoc = options.l2_assoc)
80
81        cpu_seq = RubySequencer(version = i,
82                                icache = l1i_cache,
83                                dcache = l1d_cache,
84                                physMemPort = system.physmem.port,
85                                physmem = system.physmem)
86
87        if piobus != None:
88            cpu_seq.pio_port = piobus.port
89
90        l1_cntrl = L1Cache_Controller(version = i,
91                                      sequencer = cpu_seq,
92                                      L1IcacheMemory = l1i_cache,
93                                      L1DcacheMemory = l1d_cache,
94                                      L2cacheMemory = l2_cache)
95
96        exec("system.l1_cntrl%d = l1_cntrl" % i)
97        #
98        # Add controllers and sequencers to the appropriate lists
99        #
100        cpu_sequencers.append(cpu_seq)
101        l1_cntrl_nodes.append(l1_cntrl)
102
103    phys_mem_size = long(system.physmem.range.second) - \
104                      long(system.physmem.range.first) + 1
105    mem_module_size = phys_mem_size / options.num_dirs
106
107    for i in xrange(options.num_dirs):
108        #
109        # Create the Ruby objects associated with the directory controller
110        #
111
112        mem_cntrl = RubyMemoryControl(version = i)
113
114        dir_size = MemorySize('0B')
115        dir_size.value = mem_module_size
116
117        dir_cntrl = Directory_Controller(version = i,
118                                         directory = \
119                                         RubyDirectoryMemory( \
120                                                    version = i,
121                                                    size = dir_size,
122                                                    use_map = options.use_map,
123                                                    map_levels = \
124                                                    options.map_levels),
125                                         memBuffer = mem_cntrl)
126
127        exec("system.dir_cntrl%d = dir_cntrl" % i)
128        dir_cntrl_nodes.append(dir_cntrl)
129
130    for i, dma_device in enumerate(dma_devices):
131        #
132        # Create the Ruby objects associated with the dma controller
133        #
134        dma_seq = DMASequencer(version = i,
135                               physMemPort = system.physmem.port,
136                               physmem = system.physmem)
137
138        dma_cntrl = DMA_Controller(version = i,
139                                   dma_sequencer = dma_seq)
140
141        exec("system.dma_cntrl%d = dma_cntrl" % i)
142        if dma_device.type == 'MemTest':
143            system.dma_cntrl.dma_sequencer.port = dma_device.test
144        else:
145            system.dma_cntrl.dma_sequencer.port = dma_device.dma
146        dma_cntrl.dma_sequencer.port = dma_device.dma
147        dma_cntrl_nodes.append(dma_cntrl)
148
149    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
150
151    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
152