MOESI_hammer.py revision 7032:9f938aea1942
1298SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 22188SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 3298SN/A# All rights reserved. 4298SN/A# 5298SN/A# Redistribution and use in source and binary forms, with or without 6298SN/A# modification, are permitted provided that the following conditions are 7298SN/A# met: redistributions of source code must retain the above copyright 8298SN/A# notice, this list of conditions and the following disclaimer; 9298SN/A# redistributions in binary form must reproduce the above copyright 10298SN/A# notice, this list of conditions and the following disclaimer in the 11298SN/A# documentation and/or other materials provided with the distribution; 12298SN/A# neither the name of the copyright holders nor the names of its 13298SN/A# contributors may be used to endorse or promote products derived from 14298SN/A# this software without specific prior written permission. 15298SN/A# 16298SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17298SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18298SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19298SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20298SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21298SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22298SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23298SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24298SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25298SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26298SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu# 282665Ssaidi@eecs.umich.edu# Authors: Brad Beckmann 29298SN/A 30298SN/Aimport m5 311642SN/Afrom m5.objects import * 32954SN/Afrom m5.defines import buildEnv 33956SN/Afrom m5.util import addToPath 34956SN/A 354078Sbinkertn@umich.edu 36299SN/A# 37299SN/A# Note: the L1 Cache latency is only used by the sequencer on fast path hits 382170SN/A# 395882Snate@binkert.orgclass L1Cache(RubyCache): 406658Snate@binkert.org latency = 3 416658Snate@binkert.org 421717SN/A# 432680Sktlim@umich.edu# Note: the L2 Cache latency is not currently used 442313SN/A# 455529Snate@binkert.orgclass L2Cache(RubyCache): 463565Sgblack@eecs.umich.edu latency = 15 47298SN/A 485606Snate@binkert.orgdef create_system(options, phys_mem, piobus, dma_devices): 49298SN/A 50695SN/A if buildEnv['PROTOCOL'] != 'MOESI_hammer': 51695SN/A panic("This script requires the MOESI_hammer protocol to be built.") 52954SN/A 536118Snate@binkert.org cpu_sequencers = [] 545780Ssteve.reinhardt@amd.com 556118Snate@binkert.org # 562080SN/A # The ruby network creation expects the list of nodes in the system to be 575780Ssteve.reinhardt@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 58298SN/A # listed before the directory nodes and directory nodes before dma nodes, etc. 59299SN/A # 601052SN/A l1_cntrl_nodes = [] 61729SN/A dir_cntrl_nodes = [] 622107SN/A dma_cntrl_nodes = [] 63298SN/A 645504Snate@binkert.org # 655504Snate@binkert.org # Must create the individual controllers before the network to ensure the 665780Ssteve.reinhardt@amd.com # controller constructors are called before the network constructor 675780Ssteve.reinhardt@amd.com # 685504Snate@binkert.org 695504Snate@binkert.org for i in xrange(options.num_cpus): 70298SN/A # 715504Snate@binkert.org # First create the Ruby objects associated with this cpu 725504Snate@binkert.org # 735504Snate@binkert.org l1i_cache = L1Cache(size = options.l1i_size, 745504Snate@binkert.org assoc = options.l1i_assoc) 755504Snate@binkert.org l1d_cache = L1Cache(size = options.l1d_size, 765504Snate@binkert.org assoc = options.l1d_assoc) 775504Snate@binkert.org l2_cache = L2Cache(size = options.l2_size, 785529Snate@binkert.org assoc = options.l2_assoc) 795504Snate@binkert.org 805504Snate@binkert.org cpu_seq = RubySequencer(version = i, 815504Snate@binkert.org icache = l1i_cache, 825504Snate@binkert.org dcache = l1d_cache, 835504Snate@binkert.org physMemPort = phys_mem.port, 845504Snate@binkert.org physmem = phys_mem) 855504Snate@binkert.org 865504Snate@binkert.org if piobus != None: 875504Snate@binkert.org cpu_seq.pio_port = piobus.port 885504Snate@binkert.org 895504Snate@binkert.org l1_cntrl = L1Cache_Controller(version = i, 905504Snate@binkert.org sequencer = cpu_seq, 917819Ssteve.reinhardt@amd.com L1IcacheMemory = l1i_cache, 927819Ssteve.reinhardt@amd.com L1DcacheMemory = l1d_cache, 937819Ssteve.reinhardt@amd.com L2cacheMemory = l2_cache) 945504Snate@binkert.org # 955504Snate@binkert.org # Add controllers and sequencers to the appropriate lists 965504Snate@binkert.org # 975504Snate@binkert.org cpu_sequencers.append(cpu_seq) 987064Snate@binkert.org l1_cntrl_nodes.append(l1_cntrl) 995504Snate@binkert.org 1007819Ssteve.reinhardt@amd.com phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1 1015504Snate@binkert.org mem_module_size = phys_mem_size / options.num_dirs 1025504Snate@binkert.org 1037819Ssteve.reinhardt@amd.com for i in xrange(options.num_dirs): 1045504Snate@binkert.org # 1055504Snate@binkert.org # Create the Ruby objects associated with the directory controller 1065504Snate@binkert.org # 1075504Snate@binkert.org 1085504Snate@binkert.org mem_cntrl = RubyMemoryControl(version = i) 1095504Snate@binkert.org 1105504Snate@binkert.org dir_size = MemorySize('0B') 1115504Snate@binkert.org dir_size.value = mem_module_size 1125504Snate@binkert.org 1137819Ssteve.reinhardt@amd.com dir_cntrl = Directory_Controller(version = i, 1147819Ssteve.reinhardt@amd.com directory = \ 1157819Ssteve.reinhardt@amd.com RubyDirectoryMemory(version = i, 1165504Snate@binkert.org size = dir_size, 1175504Snate@binkert.org use_map = options.use_map, 1185504Snate@binkert.org map_levels = options.map_levels), 1195504Snate@binkert.org memBuffer = mem_cntrl) 1207819Ssteve.reinhardt@amd.com 1215504Snate@binkert.org dir_cntrl_nodes.append(dir_cntrl) 1227819Ssteve.reinhardt@amd.com 1235504Snate@binkert.org for i, dma_device in enumerate(dma_devices): 1245504Snate@binkert.org # 1257819Ssteve.reinhardt@amd.com # Create the Ruby objects associated with the dma controller 1265504Snate@binkert.org # 1275504Snate@binkert.org dma_seq = DMASequencer(version = i, 1285504Snate@binkert.org physMemPort = phys_mem.port, 1295504Snate@binkert.org physmem = phys_mem) 1305504Snate@binkert.org 1315504Snate@binkert.org dma_cntrl = DMA_Controller(version = i, 1325504Snate@binkert.org dma_sequencer = dma_seq) 1335504Snate@binkert.org 1345504Snate@binkert.org dma_cntrl.dma_sequencer.port = dma_device.dma 1357064Snate@binkert.org dma_cntrl_nodes.append(dma_cntrl) 1367064Snate@binkert.org 1375504Snate@binkert.org all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes 1385504Snate@binkert.org 1395780Ssteve.reinhardt@amd.com return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 1405780Ssteve.reinhardt@amd.com