MOESI_hammer.py revision 13731:67cd980cb20f 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology, create_directories
35from Ruby import send_evicts
36
37#
38# Declare caches used by the protocol
39#
40class L1Cache(RubyCache): pass
41class L2Cache(RubyCache): pass
42#
43# Probe filter is a cache
44#
45class ProbeFilter(RubyCache): pass
46
47def define_options(parser):
48    parser.add_option("--allow-atomic-migration", action="store_true",
49          help="allow migratory sharing for atomic only accessed blocks")
50    parser.add_option("--pf-on", action="store_true",
51          help="Hammer: enable Probe Filter")
52    parser.add_option("--dir-on", action="store_true",
53          help="Hammer: enable Full-bit Directory")
54
55def create_system(options, full_system, system, dma_ports, bootmem,
56                  ruby_system):
57
58    if buildEnv['PROTOCOL'] != 'MOESI_hammer':
59        panic("This script requires the MOESI_hammer protocol to be built.")
60
61    cpu_sequencers = []
62
63    #
64    # The ruby network creation expects the list of nodes in the system to be
65    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
66    # listed before the directory nodes and directory nodes before dma nodes, etc.
67    #
68    l1_cntrl_nodes = []
69    dma_cntrl_nodes = []
70
71    #
72    # Must create the individual controllers before the network to ensure the
73    # controller constructors are called before the network constructor
74    #
75    block_size_bits = int(math.log(options.cacheline_size, 2))
76
77    for i in range(options.num_cpus):
78        #
79        # First create the Ruby objects associated with this cpu
80        #
81        l1i_cache = L1Cache(size = options.l1i_size,
82                            assoc = options.l1i_assoc,
83                            start_index_bit = block_size_bits,
84                            is_icache = True)
85        l1d_cache = L1Cache(size = options.l1d_size,
86                            assoc = options.l1d_assoc,
87                            start_index_bit = block_size_bits)
88        l2_cache = L2Cache(size = options.l2_size,
89                           assoc = options.l2_assoc,
90                           start_index_bit = block_size_bits)
91
92        # the ruby random tester reuses num_cpus to specify the
93        # number of cpu ports connected to the tester object, which
94        # is stored in system.cpu. because there is only ever one
95        # tester object, num_cpus is not necessarily equal to the
96        # size of system.cpu; therefore if len(system.cpu) == 1
97        # we use system.cpu[0] to set the clk_domain, thereby ensuring
98        # we don't index off the end of the cpu list.
99        if len(system.cpu) == 1:
100            clk_domain = system.cpu[0].clk_domain
101        else:
102            clk_domain = system.cpu[i].clk_domain
103
104        l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache,
105                                      L1Dcache=l1d_cache, L2cache=l2_cache,
106                                      no_mig_atomic=not \
107                                      options.allow_atomic_migration,
108                                      send_evictions=send_evicts(options),
109                                      transitions_per_cycle=options.ports,
110                                      clk_domain=clk_domain,
111                                      ruby_system=ruby_system)
112
113        cpu_seq = RubySequencer(version=i, icache=l1i_cache,
114                                dcache=l1d_cache,clk_domain=clk_domain,
115                                ruby_system=ruby_system)
116
117        l1_cntrl.sequencer = cpu_seq
118        if options.recycle_latency:
119            l1_cntrl.recycle_latency = options.recycle_latency
120
121        exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
122
123        # Add controllers and sequencers to the appropriate lists
124        cpu_sequencers.append(cpu_seq)
125        l1_cntrl_nodes.append(l1_cntrl)
126
127        # Connect the L1 controller and the network
128        # Connect the buffers from the controller to network
129        l1_cntrl.requestFromCache = MessageBuffer()
130        l1_cntrl.requestFromCache.master = ruby_system.network.slave
131        l1_cntrl.responseFromCache = MessageBuffer()
132        l1_cntrl.responseFromCache.master = ruby_system.network.slave
133        l1_cntrl.unblockFromCache = MessageBuffer()
134        l1_cntrl.unblockFromCache.master = ruby_system.network.slave
135
136        l1_cntrl.triggerQueue = MessageBuffer()
137
138        # Connect the buffers from the network to the controller
139        l1_cntrl.mandatoryQueue = MessageBuffer()
140        l1_cntrl.forwardToCache = MessageBuffer()
141        l1_cntrl.forwardToCache.slave = ruby_system.network.master
142        l1_cntrl.responseToCache = MessageBuffer()
143        l1_cntrl.responseToCache.slave = ruby_system.network.master
144
145
146    #
147    # determine size and index bits for probe filter
148    # By default, the probe filter size is configured to be twice the
149    # size of the L2 cache.
150    #
151    pf_size = MemorySize(options.l2_size)
152    pf_size.value = pf_size.value * 2
153    dir_bits = int(math.log(options.num_dirs, 2))
154    pf_bits = int(math.log(pf_size.value, 2))
155    if options.numa_high_bit:
156        if options.pf_on or options.dir_on:
157            # if numa high bit explicitly set, make sure it does not overlap
158            # with the probe filter index
159            assert(options.numa_high_bit - dir_bits > pf_bits)
160
161        # set the probe filter start bit to just above the block offset
162        pf_start_bit = block_size_bits
163    else:
164        if dir_bits > 0:
165            pf_start_bit = dir_bits + block_size_bits - 1
166        else:
167            pf_start_bit = block_size_bits
168
169    # Run each of the ruby memory controllers at a ratio of the frequency of
170    # the ruby system
171    # clk_divider value is a fix to pass regression.
172    ruby_system.memctrl_clk_domain = DerivedClockDomain(
173                                          clk_domain=ruby_system.clk_domain,
174                                          clk_divider=3)
175
176    mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
177        options, bootmem, ruby_system, system)
178    dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
179    if rom_dir_cntrl_node is not None:
180        dir_cntrl_nodes.append(rom_dir_cntrl_node)
181    for dir_cntrl in dir_cntrl_nodes:
182        pf = ProbeFilter(size = pf_size, assoc = 4,
183                         start_index_bit = pf_start_bit)
184
185        dir_cntrl.probeFilter = pf
186        dir_cntrl.probe_filter_enabled = options.pf_on
187        dir_cntrl.full_bit_dir_enabled = options.dir_on
188
189        if options.recycle_latency:
190            dir_cntrl.recycle_latency = options.recycle_latency
191
192        # Connect the directory controller to the network
193        dir_cntrl.forwardFromDir = MessageBuffer()
194        dir_cntrl.forwardFromDir.master = ruby_system.network.slave
195        dir_cntrl.responseFromDir = MessageBuffer()
196        dir_cntrl.responseFromDir.master = ruby_system.network.slave
197        dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
198        dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
199
200        dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
201
202        dir_cntrl.unblockToDir = MessageBuffer()
203        dir_cntrl.unblockToDir.slave = ruby_system.network.master
204        dir_cntrl.responseToDir = MessageBuffer()
205        dir_cntrl.responseToDir.slave = ruby_system.network.master
206        dir_cntrl.requestToDir = MessageBuffer()
207        dir_cntrl.requestToDir.slave = ruby_system.network.master
208        dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
209        dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
210        dir_cntrl.responseFromMemory = MessageBuffer()
211
212
213    for i, dma_port in enumerate(dma_ports):
214        #
215        # Create the Ruby objects associated with the dma controller
216        #
217        dma_seq = DMASequencer(version = i,
218                               ruby_system = ruby_system,
219                               slave = dma_port)
220
221        dma_cntrl = DMA_Controller(version = i,
222                                   dma_sequencer = dma_seq,
223                                   transitions_per_cycle = options.ports,
224                                   ruby_system = ruby_system)
225
226        exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
227        dma_cntrl_nodes.append(dma_cntrl)
228
229        if options.recycle_latency:
230            dma_cntrl.recycle_latency = options.recycle_latency
231
232        # Connect the dma controller to the network
233        dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
234        dma_cntrl.responseFromDir.slave = ruby_system.network.master
235        dma_cntrl.requestToDir = MessageBuffer()
236        dma_cntrl.requestToDir.master = ruby_system.network.slave
237        dma_cntrl.mandatoryQueue = MessageBuffer()
238
239    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
240
241    # Create the io controller and the sequencer
242    if full_system:
243        io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
244        ruby_system._io_port = io_seq
245        io_controller = DMA_Controller(version = len(dma_ports),
246                                       dma_sequencer = io_seq,
247                                       ruby_system = ruby_system)
248        ruby_system.io_controller = io_controller
249
250        # Connect the dma controller to the network
251        io_controller.responseFromDir = MessageBuffer(ordered = True)
252        io_controller.responseFromDir.slave = ruby_system.network.master
253        io_controller.requestToDir = MessageBuffer()
254        io_controller.requestToDir.master = ruby_system.network.slave
255        io_controller.mandatoryQueue = MessageBuffer()
256
257        all_cntrls = all_cntrls + [io_controller]
258
259    ruby_system.network.number_of_virtual_networks = 6
260    topology = create_topology(all_cntrls, options)
261    return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
262