MOESI_CMP_token.py revision 9841:69c158420c51 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology
35
36#
37# Note: the L1 Cache latency is only used by the sequencer on fast path hits
38#
39class L1Cache(RubyCache):
40    latency = 2
41
42#
43# Note: the L2 Cache latency is not currently used
44#
45class L2Cache(RubyCache):
46    latency = 10
47
48def define_options(parser):
49    parser.add_option("--l1-retries", type="int", default=1,
50                      help="Token_CMP: # of l1 retries before going persistent")
51    parser.add_option("--timeout-latency", type="int", default=300,
52                      help="Token_CMP: cycles until issuing again");
53    parser.add_option("--disable-dyn-timeouts", action="store_true",
54          help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
55    parser.add_option("--allow-atomic-migration", action="store_true",
56          help="allow migratory sharing for atomic only accessed blocks")
57
58def create_system(options, system, piobus, dma_ports, ruby_system):
59
60    if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
61        panic("This script requires the MOESI_CMP_token protocol to be built.")
62
63    #
64    # number of tokens that the owner passes to requests so that shared blocks can
65    # respond to read requests
66    #
67    n_tokens = options.num_cpus + 1
68
69    cpu_sequencers = []
70
71    #
72    # The ruby network creation expects the list of nodes in the system to be
73    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
74    # listed before the directory nodes and directory nodes before dma nodes, etc.
75    #
76    l1_cntrl_nodes = []
77    l2_cntrl_nodes = []
78    dir_cntrl_nodes = []
79    dma_cntrl_nodes = []
80
81    #
82    # Must create the individual controllers before the network to ensure the
83    # controller constructors are called before the network constructor
84    #
85    l2_bits = int(math.log(options.num_l2caches, 2))
86    block_size_bits = int(math.log(options.cacheline_size, 2))
87
88    cntrl_count = 0
89
90    for i in xrange(options.num_cpus):
91        #
92        # First create the Ruby objects associated with this cpu
93        #
94        l1i_cache = L1Cache(size = options.l1i_size,
95                            assoc = options.l1i_assoc,
96                            start_index_bit = block_size_bits)
97        l1d_cache = L1Cache(size = options.l1d_size,
98                            assoc = options.l1d_assoc,
99                            start_index_bit = block_size_bits)
100
101        l1_cntrl = L1Cache_Controller(version = i,
102                                      cntrl_id = cntrl_count,
103                                      L1Icache = l1i_cache,
104                                      L1Dcache = l1d_cache,
105                                      l2_select_num_bits = l2_bits,
106                                      N_tokens = n_tokens,
107                                      retry_threshold = \
108                                        options.l1_retries,
109                                      fixed_timeout_latency = \
110                                        options.timeout_latency,
111                                      dynamic_timeout_enabled = \
112                                        not options.disable_dyn_timeouts,
113                                      no_mig_atomic = not \
114                                        options.allow_atomic_migration,
115                                      send_evictions = (
116                                          options.cpu_type == "detailed"),
117                                      transitions_per_cycle = options.ports,
118                                      ruby_system = ruby_system)
119
120        cpu_seq = RubySequencer(version = i,
121                                icache = l1i_cache,
122                                dcache = l1d_cache,
123                                ruby_system = ruby_system)
124
125        l1_cntrl.sequencer = cpu_seq
126
127        if piobus != None:
128            cpu_seq.pio_port = piobus.slave
129
130        exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
131        #
132        # Add controllers and sequencers to the appropriate lists
133        #
134        cpu_sequencers.append(cpu_seq)
135        l1_cntrl_nodes.append(l1_cntrl)
136
137        cntrl_count += 1
138
139    l2_index_start = block_size_bits + l2_bits
140
141    for i in xrange(options.num_l2caches):
142        #
143        # First create the Ruby objects associated with this cpu
144        #
145        l2_cache = L2Cache(size = options.l2_size,
146                           assoc = options.l2_assoc,
147                           start_index_bit = l2_index_start)
148
149        l2_cntrl = L2Cache_Controller(version = i,
150                                      cntrl_id = cntrl_count,
151                                      L2cache = l2_cache,
152                                      N_tokens = n_tokens,
153                                      transitions_per_cycle = options.ports,
154                                      ruby_system = ruby_system)
155
156        exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
157        l2_cntrl_nodes.append(l2_cntrl)
158
159        cntrl_count += 1
160
161    phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
162    assert(phys_mem_size % options.num_dirs == 0)
163    mem_module_size = phys_mem_size / options.num_dirs
164
165    # Run each of the ruby memory controllers at a ratio of the frequency of
166    # the ruby system
167    # clk_divider value is a fix to pass regression.
168    ruby_system.memctrl_clk_domain = DerivedClockDomain(
169                                          clk_domain=ruby_system.clk_domain,
170                                          clk_divider=3)
171
172    for i in xrange(options.num_dirs):
173        #
174        # Create the Ruby objects associated with the directory controller
175        #
176
177        mem_cntrl = RubyMemoryControl(
178                              clk_domain = ruby_system.memctrl_clk_domain,
179                              version = i,
180                              ruby_system = ruby_system)
181
182        dir_size = MemorySize('0B')
183        dir_size.value = mem_module_size
184
185        dir_cntrl = Directory_Controller(version = i,
186                                         cntrl_id = cntrl_count,
187                                         directory = \
188                                         RubyDirectoryMemory(version = i,
189                                             use_map = options.use_map,
190                                             size = dir_size),
191                                         memBuffer = mem_cntrl,
192                                         l2_select_num_bits = l2_bits,
193                                         transitions_per_cycle = options.ports,
194                                         ruby_system = ruby_system)
195
196        exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
197        dir_cntrl_nodes.append(dir_cntrl)
198
199        cntrl_count += 1
200
201    for i, dma_port in enumerate(dma_ports):
202        #
203        # Create the Ruby objects associated with the dma controller
204        #
205        dma_seq = DMASequencer(version = i,
206                               ruby_system = ruby_system)
207
208        dma_cntrl = DMA_Controller(version = i,
209                                   cntrl_id = cntrl_count,
210                                   dma_sequencer = dma_seq,
211                                   transitions_per_cycle = options.ports,
212                                   ruby_system = ruby_system)
213
214        exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
215        exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
216        dma_cntrl_nodes.append(dma_cntrl)
217        cntrl_count += 1
218
219    all_cntrls = l1_cntrl_nodes + \
220                 l2_cntrl_nodes + \
221                 dir_cntrl_nodes + \
222                 dma_cntrl_nodes
223
224    topology = create_topology(all_cntrls, options)
225
226    return (cpu_sequencers, dir_cntrl_nodes, topology)
227