MOESI_CMP_token.py revision 7564:3559d47839a1
12131SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 25268Sksewell@umich.edu# Copyright (c) 2009 Advanced Micro Devices, Inc. 35224Sksewell@umich.edu# All rights reserved. 45224Sksewell@umich.edu# 52131SN/A# Redistribution and use in source and binary forms, with or without 65224Sksewell@umich.edu# modification, are permitted provided that the following conditions are 75224Sksewell@umich.edu# met: redistributions of source code must retain the above copyright 85224Sksewell@umich.edu# notice, this list of conditions and the following disclaimer; 95224Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright 105224Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the 115224Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 125224Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 135224Sksewell@umich.edu# contributors may be used to endorse or promote products derived from 145224Sksewell@umich.edu# this software without specific prior written permission. 155224Sksewell@umich.edu# 162131SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175224Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185224Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195224Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205224Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215224Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225224Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235224Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245224Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255224Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265224Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275224Sksewell@umich.edu# 282665Ssaidi@eecs.umich.edu# Authors: Brad Beckmann 295224Sksewell@umich.edu 305224Sksewell@umich.eduimport math 315222Sksewell@umich.eduimport m5 322131SN/Afrom m5.objects import * 332131SN/Afrom m5.defines import buildEnv 342239SN/A 352239SN/A# 362131SN/A# Note: the L1 Cache latency is only used by the sequencer on fast path hits 372131SN/A# 382447SN/Aclass L1Cache(RubyCache): 392447SN/A latency = 2 402447SN/A 416378Sgblack@eecs.umich.edu# 422447SN/A# Note: the L2 Cache latency is not currently used 432131SN/A# 442239SN/Aclass L2Cache(RubyCache): 452131SN/A latency = 10 462447SN/A 472447SN/Adef define_options(parser): 482447SN/A parser.add_option("--l1-retries", type="int", default=1, 492131SN/A help="Token_CMP: # of l1 retries before going persistent") 506379Sgblack@eecs.umich.edu parser.add_option("--timeout-latency", type="int", default=300, 516379Sgblack@eecs.umich.edu help="Token_CMP: cycles until issuing again"); 526379Sgblack@eecs.umich.edu parser.add_option("--disable-dyn-timeouts", action="store_true", 536379Sgblack@eecs.umich.edu help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 546379Sgblack@eecs.umich.edu parser.add_option("--allow-atomic-migration", action="store_true", 552447SN/A help="allow migratory sharing for atomic only accessed blocks") 567678Sgblack@eecs.umich.edu 577678Sgblack@eecs.umich.edudef create_system(options, system, piobus, dma_devices): 587678Sgblack@eecs.umich.edu 596378Sgblack@eecs.umich.edu if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 606378Sgblack@eecs.umich.edu panic("This script requires the MOESI_CMP_token protocol to be built.") 612447SN/A 622447SN/A # 632447SN/A # number of tokens that the owner passes to requests so that shared blocks can 642131SN/A # respond to read requests 652131SN/A # 662447SN/A n_tokens = options.num_cpus + 1 672131SN/A 682447SN/A cpu_sequencers = [] 692447SN/A 702447SN/A # 712447SN/A # The ruby network creation expects the list of nodes in the system to be 722131SN/A # consistent with the NetDest list. Therefore the l1 controller nodes must be 734695Sgblack@eecs.umich.edu # listed before the directory nodes and directory nodes before dma nodes, etc. 742447SN/A # 752447SN/A l1_cntrl_nodes = [] 765222Sksewell@umich.edu l2_cntrl_nodes = [] 775222Sksewell@umich.edu dir_cntrl_nodes = [] 785222Sksewell@umich.edu dma_cntrl_nodes = [] 795222Sksewell@umich.edu 805222Sksewell@umich.edu # 815222Sksewell@umich.edu # Must create the individual controllers before the network to ensure the 825222Sksewell@umich.edu # controller constructors are called before the network constructor 835222Sksewell@umich.edu # 845222Sksewell@umich.edu l2_bits = int(math.log(options.num_l2caches, 2)) 855222Sksewell@umich.edu 865222Sksewell@umich.edu for i in xrange(options.num_cpus): 875222Sksewell@umich.edu # 885222Sksewell@umich.edu # First create the Ruby objects associated with this cpu 895222Sksewell@umich.edu # 902447SN/A l1i_cache = L1Cache(size = options.l1i_size, 912131SN/A assoc = options.l1i_assoc) 922447SN/A l1d_cache = L1Cache(size = options.l1d_size, 932131SN/A assoc = options.l1d_assoc) 942447SN/A 952447SN/A cpu_seq = RubySequencer(version = i, 962447SN/A icache = l1i_cache, 972447SN/A dcache = l1d_cache, 982131SN/A physMemPort = system.physmem.port, 994695Sgblack@eecs.umich.edu physmem = system.physmem) 1002447SN/A 1012447SN/A if piobus != None: 1025222Sksewell@umich.edu cpu_seq.pio_port = piobus.port 1032447SN/A 1042131SN/A l1_cntrl = L1Cache_Controller(version = i, 1055222Sksewell@umich.edu sequencer = cpu_seq, 1065222Sksewell@umich.edu L1IcacheMemory = l1i_cache, 1075222Sksewell@umich.edu L1DcacheMemory = l1d_cache, 1085222Sksewell@umich.edu l2_select_num_bits = l2_bits, 1095222Sksewell@umich.edu N_tokens = n_tokens, 1105222Sksewell@umich.edu retry_threshold = \ 1115222Sksewell@umich.edu options.l1_retries, 1125222Sksewell@umich.edu fixed_timeout_latency = \ 1135222Sksewell@umich.edu options.timeout_latency, 1145222Sksewell@umich.edu dynamic_timeout_enabled = \ 1155222Sksewell@umich.edu not options.disable_dyn_timeouts, 1167678Sgblack@eecs.umich.edu no_mig_atomic = not \ 1177678Sgblack@eecs.umich.edu options.allow_atomic_migration) 1185222Sksewell@umich.edu 1195222Sksewell@umich.edu exec("system.l1_cntrl%d = l1_cntrl" % i) 1205222Sksewell@umich.edu # 1216378Sgblack@eecs.umich.edu # Add controllers and sequencers to the appropriate lists 1225222Sksewell@umich.edu # 1235222Sksewell@umich.edu cpu_sequencers.append(cpu_seq) 1245222Sksewell@umich.edu l1_cntrl_nodes.append(l1_cntrl) 1255222Sksewell@umich.edu 1265222Sksewell@umich.edu for i in xrange(options.num_l2caches): 1275222Sksewell@umich.edu # 1285222Sksewell@umich.edu # First create the Ruby objects associated with this cpu 1295222Sksewell@umich.edu # 1305222Sksewell@umich.edu l2_cache = L2Cache(size = options.l2_size, 1315222Sksewell@umich.edu assoc = options.l2_assoc, 1325222Sksewell@umich.edu start_index_bit = l2_bits) 1337678Sgblack@eecs.umich.edu 1347678Sgblack@eecs.umich.edu l2_cntrl = L2Cache_Controller(version = i, 1355222Sksewell@umich.edu L2cacheMemory = l2_cache, 1366378Sgblack@eecs.umich.edu N_tokens = n_tokens) 1375222Sksewell@umich.edu 1384661Sksewell@umich.edu exec("system.l2_cntrl%d = l2_cntrl" % i) 1394661Sksewell@umich.edu l2_cntrl_nodes.append(l2_cntrl) 1404661Sksewell@umich.edu 1414661Sksewell@umich.edu phys_mem_size = long(system.physmem.range.second) - \ 1424661Sksewell@umich.edu long(system.physmem.range.first) + 1 1434661Sksewell@umich.edu mem_module_size = phys_mem_size / options.num_dirs 1444661Sksewell@umich.edu 1454695Sgblack@eecs.umich.edu for i in xrange(options.num_dirs): 1464661Sksewell@umich.edu # 1474661Sksewell@umich.edu # Create the Ruby objects associated with the directory controller 1484661Sksewell@umich.edu # 1494661Sksewell@umich.edu 1502447SN/A mem_cntrl = RubyMemoryControl(version = i) 1515222Sksewell@umich.edu 1522447SN/A dir_size = MemorySize('0B') 1532447SN/A dir_size.value = mem_module_size 1545222Sksewell@umich.edu 1552447SN/A dir_cntrl = Directory_Controller(version = i, 1562447SN/A directory = \ 1572447SN/A RubyDirectoryMemory(version = i, 1582131SN/A size = \ 1594695Sgblack@eecs.umich.edu dir_size), 1602447SN/A memBuffer = mem_cntrl, 1612447SN/A l2_select_num_bits = \ 1627678Sgblack@eecs.umich.edu math.log(options.num_l2caches, 1637678Sgblack@eecs.umich.edu 2)) 1642447SN/A 1656378Sgblack@eecs.umich.edu exec("system.dir_cntrl%d = dir_cntrl" % i) 1665222Sksewell@umich.edu dir_cntrl_nodes.append(dir_cntrl) 1674661Sksewell@umich.edu 1684661Sksewell@umich.edu for i, dma_device in enumerate(dma_devices): 1695222Sksewell@umich.edu # 1704661Sksewell@umich.edu # Create the Ruby objects associated with the dma controller 1714661Sksewell@umich.edu # 1724661Sksewell@umich.edu dma_seq = DMASequencer(version = i, 1734661Sksewell@umich.edu physMemPort = system.physmem.port, 1744695Sgblack@eecs.umich.edu physmem = system.physmem) 1754661Sksewell@umich.edu 1764661Sksewell@umich.edu dma_cntrl = DMA_Controller(version = i, 1777678Sgblack@eecs.umich.edu dma_sequencer = dma_seq) 1787678Sgblack@eecs.umich.edu 1794661Sksewell@umich.edu exec("system.dma_cntrl%d = dma_cntrl" % i) 1804661Sksewell@umich.edu if dma_device.type == 'MemTest': 1812447SN/A system.dma_cntrl.dma_sequencer.port = dma_device.test 1822131SN/A else: 1832447SN/A system.dma_cntrl.dma_sequencer.port = dma_device.dma 1842447SN/A dma_cntrl.dma_sequencer.port = dma_device.dma 1852447SN/A dma_cntrl_nodes.append(dma_cntrl) 1862447SN/A 1872131SN/A all_cntrls = l1_cntrl_nodes + \ 1884695Sgblack@eecs.umich.edu l2_cntrl_nodes + \ 1892447SN/A dir_cntrl_nodes + \ 1902447SN/A dma_cntrl_nodes 1912447SN/A 1922131SN/A return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 1932447SN/A