MOESI_CMP_token.py revision 13731:67cd980cb20f
110780SCurtis.Dunham@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 210780SCurtis.Dunham@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 310780SCurtis.Dunham@arm.com# All rights reserved. 410780SCurtis.Dunham@arm.com# 510780SCurtis.Dunham@arm.com# Redistribution and use in source and binary forms, with or without 610780SCurtis.Dunham@arm.com# modification, are permitted provided that the following conditions are 710780SCurtis.Dunham@arm.com# met: redistributions of source code must retain the above copyright 810780SCurtis.Dunham@arm.com# notice, this list of conditions and the following disclaimer; 910780SCurtis.Dunham@arm.com# redistributions in binary form must reproduce the above copyright 1010780SCurtis.Dunham@arm.com# notice, this list of conditions and the following disclaimer in the 1110780SCurtis.Dunham@arm.com# documentation and/or other materials provided with the distribution; 1210780SCurtis.Dunham@arm.com# neither the name of the copyright holders nor the names of its 1310780SCurtis.Dunham@arm.com# contributors may be used to endorse or promote products derived from 1410780SCurtis.Dunham@arm.com# this software without specific prior written permission. 1510780SCurtis.Dunham@arm.com# 1610780SCurtis.Dunham@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710780SCurtis.Dunham@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810780SCurtis.Dunham@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910780SCurtis.Dunham@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010780SCurtis.Dunham@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110780SCurtis.Dunham@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210780SCurtis.Dunham@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310780SCurtis.Dunham@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410780SCurtis.Dunham@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510780SCurtis.Dunham@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610780SCurtis.Dunham@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710780SCurtis.Dunham@arm.com# 2810780SCurtis.Dunham@arm.com# Authors: Brad Beckmann 2910780SCurtis.Dunham@arm.com 3010780SCurtis.Dunham@arm.comimport math 3110780SCurtis.Dunham@arm.comimport m5 3210780SCurtis.Dunham@arm.comfrom m5.objects import * 3310780SCurtis.Dunham@arm.comfrom m5.defines import buildEnv 3410780SCurtis.Dunham@arm.comfrom Ruby import create_topology, create_directories 3510780SCurtis.Dunham@arm.comfrom Ruby import send_evicts 3610780SCurtis.Dunham@arm.com 3710780SCurtis.Dunham@arm.com# 3810780SCurtis.Dunham@arm.com# Declare caches used by the protocol 3910780SCurtis.Dunham@arm.com# 4010780SCurtis.Dunham@arm.comclass L1Cache(RubyCache): pass 4110780SCurtis.Dunham@arm.comclass L2Cache(RubyCache): pass 4210780SCurtis.Dunham@arm.com 4310780SCurtis.Dunham@arm.comdef define_options(parser): 4410780SCurtis.Dunham@arm.com parser.add_option("--l1-retries", type="int", default=1, 4510780SCurtis.Dunham@arm.com help="Token_CMP: # of l1 retries before going persistent") 4610780SCurtis.Dunham@arm.com parser.add_option("--timeout-latency", type="int", default=300, 4710780SCurtis.Dunham@arm.com help="Token_CMP: cycles until issuing again"); 4810780SCurtis.Dunham@arm.com parser.add_option("--disable-dyn-timeouts", action="store_true", 4910780SCurtis.Dunham@arm.com help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 5010780SCurtis.Dunham@arm.com parser.add_option("--allow-atomic-migration", action="store_true", 5110780SCurtis.Dunham@arm.com help="allow migratory sharing for atomic only accessed blocks") 5210780SCurtis.Dunham@arm.com 5310780SCurtis.Dunham@arm.comdef create_system(options, full_system, system, dma_ports, bootmem, 5410780SCurtis.Dunham@arm.com ruby_system): 5511617SCurtis.Dunham@arm.com 5611617SCurtis.Dunham@arm.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 5711617SCurtis.Dunham@arm.com panic("This script requires the MOESI_CMP_token protocol to be built.") 5811617SCurtis.Dunham@arm.com 5911617SCurtis.Dunham@arm.com # 6011617SCurtis.Dunham@arm.com # number of tokens that the owner passes to requests so that shared blocks can 6111617SCurtis.Dunham@arm.com # respond to read requests 6210780SCurtis.Dunham@arm.com # 6311617SCurtis.Dunham@arm.com n_tokens = options.num_cpus + 1 6410780SCurtis.Dunham@arm.com 6510780SCurtis.Dunham@arm.com cpu_sequencers = [] 6610780SCurtis.Dunham@arm.com 6710780SCurtis.Dunham@arm.com # 6811617SCurtis.Dunham@arm.com # The ruby network creation expects the list of nodes in the system to be 6910780SCurtis.Dunham@arm.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 7010780SCurtis.Dunham@arm.com # listed before the directory nodes and directory nodes before dma nodes, etc. 7110780SCurtis.Dunham@arm.com # 7211617SCurtis.Dunham@arm.com l1_cntrl_nodes = [] 7310780SCurtis.Dunham@arm.com l2_cntrl_nodes = [] 7410780SCurtis.Dunham@arm.com dma_cntrl_nodes = [] 7510780SCurtis.Dunham@arm.com 7610780SCurtis.Dunham@arm.com # 7710780SCurtis.Dunham@arm.com # Must create the individual controllers before the network to ensure the 7810780SCurtis.Dunham@arm.com # controller constructors are called before the network constructor 7910780SCurtis.Dunham@arm.com # 8010780SCurtis.Dunham@arm.com l2_bits = int(math.log(options.num_l2caches, 2)) 8110780SCurtis.Dunham@arm.com block_size_bits = int(math.log(options.cacheline_size, 2)) 8211617SCurtis.Dunham@arm.com 8310780SCurtis.Dunham@arm.com for i in range(options.num_cpus): 8410780SCurtis.Dunham@arm.com # 8510780SCurtis.Dunham@arm.com # First create the Ruby objects associated with this cpu 8610780SCurtis.Dunham@arm.com # 8710780SCurtis.Dunham@arm.com l1i_cache = L1Cache(size = options.l1i_size, 8810780SCurtis.Dunham@arm.com assoc = options.l1i_assoc, 8910780SCurtis.Dunham@arm.com start_index_bit = block_size_bits) 9010780SCurtis.Dunham@arm.com l1d_cache = L1Cache(size = options.l1d_size, 9110780SCurtis.Dunham@arm.com assoc = options.l1d_assoc, 9210780SCurtis.Dunham@arm.com start_index_bit = block_size_bits) 9310780SCurtis.Dunham@arm.com 9410780SCurtis.Dunham@arm.com # the ruby random tester reuses num_cpus to specify the 9510780SCurtis.Dunham@arm.com # number of cpu ports connected to the tester object, which 9611617SCurtis.Dunham@arm.com # is stored in system.cpu. because there is only ever one 9711617SCurtis.Dunham@arm.com # tester object, num_cpus is not necessarily equal to the 9810780SCurtis.Dunham@arm.com # size of system.cpu; therefore if len(system.cpu) == 1 9911314SCurtis.Dunham@arm.com # we use system.cpu[0] to set the clk_domain, thereby ensuring 10010780SCurtis.Dunham@arm.com # we don't index off the end of the cpu list. 10110780SCurtis.Dunham@arm.com if len(system.cpu) == 1: 10210780SCurtis.Dunham@arm.com clk_domain = system.cpu[0].clk_domain 10310780SCurtis.Dunham@arm.com else: 10410780SCurtis.Dunham@arm.com clk_domain = system.cpu[i].clk_domain 10511617SCurtis.Dunham@arm.com 10610780SCurtis.Dunham@arm.com l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache, 10710780SCurtis.Dunham@arm.com L1Dcache=l1d_cache, 10810780SCurtis.Dunham@arm.com l2_select_num_bits=l2_bits, 10910780SCurtis.Dunham@arm.com N_tokens=n_tokens, 11010780SCurtis.Dunham@arm.com retry_threshold=options.l1_retries, 11110780SCurtis.Dunham@arm.com fixed_timeout_latency=\ 11210780SCurtis.Dunham@arm.com options.timeout_latency, 11310780SCurtis.Dunham@arm.com dynamic_timeout_enabled=\ 11410780SCurtis.Dunham@arm.com not options.disable_dyn_timeouts, 11510780SCurtis.Dunham@arm.com no_mig_atomic=not \ 11610780SCurtis.Dunham@arm.com options.allow_atomic_migration, 11710780SCurtis.Dunham@arm.com send_evictions=send_evicts(options), 11810780SCurtis.Dunham@arm.com transitions_per_cycle=options.ports, 11910780SCurtis.Dunham@arm.com clk_domain=clk_domain, 12010780SCurtis.Dunham@arm.com ruby_system=ruby_system) 12110780SCurtis.Dunham@arm.com 12210780SCurtis.Dunham@arm.com cpu_seq = RubySequencer(version=i, icache=l1i_cache, 12310780SCurtis.Dunham@arm.com dcache=l1d_cache, clk_domain=clk_domain, 12410780SCurtis.Dunham@arm.com ruby_system=ruby_system) 12510780SCurtis.Dunham@arm.com 12610780SCurtis.Dunham@arm.com l1_cntrl.sequencer = cpu_seq 12710780SCurtis.Dunham@arm.com exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 12810780SCurtis.Dunham@arm.com 12910780SCurtis.Dunham@arm.com # Add controllers and sequencers to the appropriate lists 13010780SCurtis.Dunham@arm.com cpu_sequencers.append(cpu_seq) 13110780SCurtis.Dunham@arm.com l1_cntrl_nodes.append(l1_cntrl) 13210780SCurtis.Dunham@arm.com 13310780SCurtis.Dunham@arm.com # Connect the L1 controllers and the network 13410780SCurtis.Dunham@arm.com l1_cntrl.requestFromL1Cache = MessageBuffer() 13510780SCurtis.Dunham@arm.com l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave 13610780SCurtis.Dunham@arm.com l1_cntrl.responseFromL1Cache = MessageBuffer() 13710780SCurtis.Dunham@arm.com l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave 13810780SCurtis.Dunham@arm.com l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered = True) 13910780SCurtis.Dunham@arm.com l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave 14010780SCurtis.Dunham@arm.com 14110780SCurtis.Dunham@arm.com l1_cntrl.mandatoryQueue = MessageBuffer() 14210780SCurtis.Dunham@arm.com l1_cntrl.requestToL1Cache = MessageBuffer() 14310780SCurtis.Dunham@arm.com l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 14410780SCurtis.Dunham@arm.com l1_cntrl.responseToL1Cache = MessageBuffer() 14510780SCurtis.Dunham@arm.com l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 14610780SCurtis.Dunham@arm.com l1_cntrl.persistentToL1Cache = MessageBuffer(ordered = True) 14710780SCurtis.Dunham@arm.com l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master 14810780SCurtis.Dunham@arm.com 14910780SCurtis.Dunham@arm.com 15010780SCurtis.Dunham@arm.com l2_index_start = block_size_bits + l2_bits 15110780SCurtis.Dunham@arm.com 15210780SCurtis.Dunham@arm.com for i in range(options.num_l2caches): 15310780SCurtis.Dunham@arm.com # 15410780SCurtis.Dunham@arm.com # First create the Ruby objects associated with this cpu 15510780SCurtis.Dunham@arm.com # 15610780SCurtis.Dunham@arm.com l2_cache = L2Cache(size = options.l2_size, 15710780SCurtis.Dunham@arm.com assoc = options.l2_assoc, 15810780SCurtis.Dunham@arm.com start_index_bit = l2_index_start) 15910780SCurtis.Dunham@arm.com 16010780SCurtis.Dunham@arm.com l2_cntrl = L2Cache_Controller(version = i, 16110780SCurtis.Dunham@arm.com L2cache = l2_cache, 16210780SCurtis.Dunham@arm.com N_tokens = n_tokens, 16311617SCurtis.Dunham@arm.com transitions_per_cycle = options.ports, 16410780SCurtis.Dunham@arm.com ruby_system = ruby_system) 16510780SCurtis.Dunham@arm.com 16610780SCurtis.Dunham@arm.com exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 16710780SCurtis.Dunham@arm.com l2_cntrl_nodes.append(l2_cntrl) 16810780SCurtis.Dunham@arm.com 16910780SCurtis.Dunham@arm.com # Connect the L2 controllers and the network 17010780SCurtis.Dunham@arm.com l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() 17110780SCurtis.Dunham@arm.com l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave 17210780SCurtis.Dunham@arm.com l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 17310780SCurtis.Dunham@arm.com l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 17410780SCurtis.Dunham@arm.com l2_cntrl.responseFromL2Cache = MessageBuffer() 17510780SCurtis.Dunham@arm.com l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 17611617SCurtis.Dunham@arm.com 17710780SCurtis.Dunham@arm.com l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() 17810780SCurtis.Dunham@arm.com l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master 17910780SCurtis.Dunham@arm.com l2_cntrl.L1RequestToL2Cache = MessageBuffer() 18010780SCurtis.Dunham@arm.com l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 18110780SCurtis.Dunham@arm.com l2_cntrl.responseToL2Cache = MessageBuffer() 18210780SCurtis.Dunham@arm.com l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 18310780SCurtis.Dunham@arm.com l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True) 18410780SCurtis.Dunham@arm.com l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master 18510780SCurtis.Dunham@arm.com 18610780SCurtis.Dunham@arm.com 18710780SCurtis.Dunham@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 18810780SCurtis.Dunham@arm.com # the ruby system 18910780SCurtis.Dunham@arm.com # clk_divider value is a fix to pass regression. 19010780SCurtis.Dunham@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 19110780SCurtis.Dunham@arm.com clk_domain=ruby_system.clk_domain, 19210780SCurtis.Dunham@arm.com clk_divider=3) 19310780SCurtis.Dunham@arm.com 19410780SCurtis.Dunham@arm.com mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories( 19510780SCurtis.Dunham@arm.com options, bootmem, ruby_system, system) 19610780SCurtis.Dunham@arm.com dir_cntrl_nodes = mem_dir_cntrl_nodes[:] 19710780SCurtis.Dunham@arm.com if rom_dir_cntrl_node is not None: 19810780SCurtis.Dunham@arm.com dir_cntrl_nodes.append(rom_dir_cntrl_node) 19910780SCurtis.Dunham@arm.com for dir_cntrl in dir_cntrl_nodes: 20010780SCurtis.Dunham@arm.com dir_cntrl.l2_select_num_bits = l2_bits 20110780SCurtis.Dunham@arm.com # Connect the directory controllers and the network 20210780SCurtis.Dunham@arm.com dir_cntrl.requestToDir = MessageBuffer() 20310780SCurtis.Dunham@arm.com dir_cntrl.requestToDir.slave = ruby_system.network.master 20410780SCurtis.Dunham@arm.com dir_cntrl.responseToDir = MessageBuffer() 205 dir_cntrl.responseToDir.slave = ruby_system.network.master 206 dir_cntrl.persistentToDir = MessageBuffer(ordered = True) 207 dir_cntrl.persistentToDir.slave = ruby_system.network.master 208 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True) 209 dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master 210 211 dir_cntrl.requestFromDir = MessageBuffer() 212 dir_cntrl.requestFromDir.master = ruby_system.network.slave 213 dir_cntrl.responseFromDir = MessageBuffer() 214 dir_cntrl.responseFromDir.master = ruby_system.network.slave 215 dir_cntrl.persistentFromDir = MessageBuffer(ordered = True) 216 dir_cntrl.persistentFromDir.master = ruby_system.network.slave 217 dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True) 218 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave 219 dir_cntrl.responseFromMemory = MessageBuffer() 220 221 222 for i, dma_port in enumerate(dma_ports): 223 # 224 # Create the Ruby objects associated with the dma controller 225 # 226 dma_seq = DMASequencer(version = i, 227 ruby_system = ruby_system, 228 slave = dma_port) 229 230 dma_cntrl = DMA_Controller(version = i, 231 dma_sequencer = dma_seq, 232 transitions_per_cycle = options.ports, 233 ruby_system = ruby_system) 234 235 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 236 dma_cntrl_nodes.append(dma_cntrl) 237 238 # Connect the dma controller to the network 239 dma_cntrl.mandatoryQueue = MessageBuffer() 240 dma_cntrl.responseFromDir = MessageBuffer(ordered = True) 241 dma_cntrl.responseFromDir.slave = ruby_system.network.master 242 dma_cntrl.reqToDirectory = MessageBuffer() 243 dma_cntrl.reqToDirectory.master = ruby_system.network.slave 244 245 all_cntrls = l1_cntrl_nodes + \ 246 l2_cntrl_nodes + \ 247 dir_cntrl_nodes + \ 248 dma_cntrl_nodes 249 250 # Create the io controller and the sequencer 251 if full_system: 252 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 253 ruby_system._io_port = io_seq 254 io_controller = DMA_Controller(version = len(dma_ports), 255 dma_sequencer = io_seq, 256 ruby_system = ruby_system) 257 ruby_system.io_controller = io_controller 258 259 # Connect the dma controller to the network 260 io_controller.mandatoryQueue = MessageBuffer() 261 io_controller.responseFromDir = MessageBuffer(ordered = True) 262 io_controller.responseFromDir.slave = ruby_system.network.master 263 io_controller.reqToDirectory = MessageBuffer() 264 io_controller.reqToDirectory.master = ruby_system.network.slave 265 266 all_cntrls = all_cntrls + [io_controller] 267 268 269 ruby_system.network.number_of_virtual_networks = 6 270 topology = create_topology(all_cntrls, options) 271 return (cpu_sequencers, mem_dir_cntrl_nodes, topology) 272