MOESI_CMP_token.py revision 10116:d61a59beb670
12379SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 210298Salexandru.dutu@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 32379SN/A# All rights reserved. 42379SN/A# 52379SN/A# Redistribution and use in source and binary forms, with or without 62379SN/A# modification, are permitted provided that the following conditions are 72379SN/A# met: redistributions of source code must retain the above copyright 82379SN/A# notice, this list of conditions and the following disclaimer; 92379SN/A# redistributions in binary form must reproduce the above copyright 102379SN/A# notice, this list of conditions and the following disclaimer in the 112379SN/A# documentation and/or other materials provided with the distribution; 122379SN/A# neither the name of the copyright holders nor the names of its 132379SN/A# contributors may be used to endorse or promote products derived from 142379SN/A# this software without specific prior written permission. 152379SN/A# 162379SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172379SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182379SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192379SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202379SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212379SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222379SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232379SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242379SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252379SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262379SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272379SN/A# 282665Ssaidi@eecs.umich.edu# Authors: Brad Beckmann 292665Ssaidi@eecs.umich.edu 302665Ssaidi@eecs.umich.eduimport math 313311Ssaidi@eecs.umich.eduimport m5 322379SN/Afrom m5.objects import * 332379SN/Afrom m5.defines import buildEnv 342379SN/Afrom Ruby import create_topology 352379SN/A 3610298Salexandru.dutu@amd.com# 372379SN/A# Note: the L1 Cache latency is only used by the sequencer on fast path hits 3811793Sbrandon.potter@amd.com# 3911793Sbrandon.potter@amd.comclass L1Cache(RubyCache): 402379SN/A latency = 2 412379SN/A 4212536Sbrandon.potter@amd.com# 432379SN/A# Note: the L2 Cache latency is not currently used 448232Snate@binkert.org# 457678Sgblack@eecs.umich.educlass L2Cache(RubyCache): 4611800Sbrandon.potter@amd.com latency = 10 472379SN/A 482399SN/Adef define_options(parser): 4912448Sgabeblack@google.com parser.add_option("--l1-retries", type="int", default=1, 502399SN/A help="Token_CMP: # of l1 retries before going persistent") 5110558Salexandru.dutu@amd.com parser.add_option("--timeout-latency", type="int", default=300, 522399SN/A help="Token_CMP: cycles until issuing again"); 532399SN/A parser.add_option("--disable-dyn-timeouts", action="store_true", 542399SN/A help="Token_CMP: disable dyanimc timeouts, use fixed latency instead") 5512448Sgabeblack@google.com parser.add_option("--allow-atomic-migration", action="store_true", 563311Ssaidi@eecs.umich.edu help="allow migratory sharing for atomic only accessed blocks") 5712448Sgabeblack@google.com 5812442Sgabeblack@google.comdef create_system(options, system, dma_ports, ruby_system): 5912442Sgabeblack@google.com 6012461Sgabeblack@google.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 6112461Sgabeblack@google.com panic("This script requires the MOESI_CMP_token protocol to be built.") 6212461Sgabeblack@google.com 6312461Sgabeblack@google.com # 6412461Sgabeblack@google.com # number of tokens that the owner passes to requests so that shared blocks can 6512442Sgabeblack@google.com # respond to read requests 6612461Sgabeblack@google.com # 672399SN/A n_tokens = options.num_cpus + 1 682399SN/A 6912448Sgabeblack@google.com cpu_sequencers = [] 7012448Sgabeblack@google.com 7112448Sgabeblack@google.com # 722399SN/A # The ruby network creation expects the list of nodes in the system to be 732399SN/A # consistent with the NetDest list. Therefore the l1 controller nodes must be 742399SN/A # listed before the directory nodes and directory nodes before dma nodes, etc. 755877Shsul@eecs.umich.edu # 7612448Sgabeblack@google.com l1_cntrl_nodes = [] 775877Shsul@eecs.umich.edu l2_cntrl_nodes = [] 785877Shsul@eecs.umich.edu dir_cntrl_nodes = [] 795877Shsul@eecs.umich.edu dma_cntrl_nodes = [] 805877Shsul@eecs.umich.edu 815877Shsul@eecs.umich.edu # 825877Shsul@eecs.umich.edu # Must create the individual controllers before the network to ensure the 835877Shsul@eecs.umich.edu # controller constructors are called before the network constructor 8412448Sgabeblack@google.com # 8512536Sbrandon.potter@amd.com l2_bits = int(math.log(options.num_l2caches, 2)) 8612442Sgabeblack@google.com block_size_bits = int(math.log(options.cacheline_size, 2)) 8712442Sgabeblack@google.com 885877Shsul@eecs.umich.edu for i in xrange(options.num_cpus): 8912519Srico.amslinger@informatik.uni-augsburg.de # 9012442Sgabeblack@google.com # First create the Ruby objects associated with this cpu 9112448Sgabeblack@google.com # 9212448Sgabeblack@google.com l1i_cache = L1Cache(size = options.l1i_size, 9312448Sgabeblack@google.com assoc = options.l1i_assoc, 945877Shsul@eecs.umich.edu start_index_bit = block_size_bits) 955877Shsul@eecs.umich.edu l1d_cache = L1Cache(size = options.l1d_size, 965877Shsul@eecs.umich.edu assoc = options.l1d_assoc, 975877Shsul@eecs.umich.edu start_index_bit = block_size_bits) 9812448Sgabeblack@google.com 9911886Sbrandon.potter@amd.com l1_cntrl = L1Cache_Controller(version = i, 10011886Sbrandon.potter@amd.com L1Icache = l1i_cache, 10112637Sodanrc@yahoo.com.br L1Dcache = l1d_cache, 10211886Sbrandon.potter@amd.com l2_select_num_bits = l2_bits, 10311886Sbrandon.potter@amd.com N_tokens = n_tokens, 10411886Sbrandon.potter@amd.com retry_threshold = \ 10512448Sgabeblack@google.com options.l1_retries, 1065877Shsul@eecs.umich.edu fixed_timeout_latency = \ 1075877Shsul@eecs.umich.edu options.timeout_latency, 1085877Shsul@eecs.umich.edu dynamic_timeout_enabled = \ 10912461Sgabeblack@google.com not options.disable_dyn_timeouts, 1105877Shsul@eecs.umich.edu no_mig_atomic = not \ 11112448Sgabeblack@google.com options.allow_atomic_migration, 11212442Sgabeblack@google.com send_evictions = ( 11312442Sgabeblack@google.com options.cpu_type == "detailed"), 11412442Sgabeblack@google.com transitions_per_cycle = options.ports, 11512448Sgabeblack@google.com ruby_system = ruby_system) 11612448Sgabeblack@google.com 1175877Shsul@eecs.umich.edu cpu_seq = RubySequencer(version = i, 1185877Shsul@eecs.umich.edu icache = l1i_cache, 1195877Shsul@eecs.umich.edu dcache = l1d_cache, 1202399SN/A ruby_system = ruby_system) 12112448Sgabeblack@google.com 1228600Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 1238600Ssteve.reinhardt@amd.com exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 1248600Ssteve.reinhardt@amd.com 1258600Ssteve.reinhardt@amd.com # 12612448Sgabeblack@google.com # Add controllers and sequencers to the appropriate lists 12712448Sgabeblack@google.com # 1288600Ssteve.reinhardt@amd.com cpu_sequencers.append(cpu_seq) 1298600Ssteve.reinhardt@amd.com l1_cntrl_nodes.append(l1_cntrl) 1308600Ssteve.reinhardt@amd.com 1318600Ssteve.reinhardt@amd.com l2_index_start = block_size_bits + l2_bits 1328600Ssteve.reinhardt@amd.com 13312461Sgabeblack@google.com for i in xrange(options.num_l2caches): 13412455Sgabeblack@google.com # 1352399SN/A # First create the Ruby objects associated with this cpu 1362399SN/A # 1375004Sgblack@eecs.umich.edu l2_cache = L2Cache(size = options.l2_size, 13812448Sgabeblack@google.com assoc = options.l2_assoc, 13912455Sgabeblack@google.com start_index_bit = l2_index_start) 14012461Sgabeblack@google.com 1412399SN/A l2_cntrl = L2Cache_Controller(version = i, 1422399SN/A L2cache = l2_cache, 1435004Sgblack@eecs.umich.edu N_tokens = n_tokens, 14412448Sgabeblack@google.com transitions_per_cycle = options.ports, 1455004Sgblack@eecs.umich.edu ruby_system = ruby_system) 14612461Sgabeblack@google.com 14712455Sgabeblack@google.com exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1485183Ssaidi@eecs.umich.edu l2_cntrl_nodes.append(l2_cntrl) 1495004Sgblack@eecs.umich.edu 1505183Ssaidi@eecs.umich.edu phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 15112461Sgabeblack@google.com assert(phys_mem_size % options.num_dirs == 0) 1525183Ssaidi@eecs.umich.edu mem_module_size = phys_mem_size / options.num_dirs 1535004Sgblack@eecs.umich.edu 1545004Sgblack@eecs.umich.edu # Run each of the ruby memory controllers at a ratio of the frequency of 1552399SN/A # the ruby system 1562394SN/A # clk_divider value is a fix to pass regression. 15712448Sgabeblack@google.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 1582394SN/A clk_domain=ruby_system.clk_domain, 1592532SN/A clk_divider=3) 16012448Sgabeblack@google.com 16112448Sgabeblack@google.com for i in xrange(options.num_dirs): 16212448Sgabeblack@google.com # 1635004Sgblack@eecs.umich.edu # Create the Ruby objects associated with the directory controller 1642532SN/A # 1655004Sgblack@eecs.umich.edu 1665004Sgblack@eecs.umich.edu mem_cntrl = RubyMemoryControl( 1675004Sgblack@eecs.umich.edu clk_domain = ruby_system.memctrl_clk_domain, 1685004Sgblack@eecs.umich.edu version = i, 1695004Sgblack@eecs.umich.edu ruby_system = ruby_system) 1702394SN/A 1713311Ssaidi@eecs.umich.edu dir_size = MemorySize('0B') 1723311Ssaidi@eecs.umich.edu dir_size.value = mem_module_size 17312448Sgabeblack@google.com 1743311Ssaidi@eecs.umich.edu dir_cntrl = Directory_Controller(version = i, 17510905Sandreas.sandberg@arm.com directory = \ 1763320Shsul@eecs.umich.edu RubyDirectoryMemory(version = i, 1776227Snate@binkert.org use_map = options.use_map, 17810905Sandreas.sandberg@arm.com size = dir_size), 17910905Sandreas.sandberg@arm.com memBuffer = mem_cntrl, 1803311Ssaidi@eecs.umich.edu l2_select_num_bits = l2_bits, 18110905Sandreas.sandberg@arm.com transitions_per_cycle = options.ports, 18212461Sgabeblack@google.com ruby_system = ruby_system) 18312461Sgabeblack@google.com 1843311Ssaidi@eecs.umich.edu exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1853311Ssaidi@eecs.umich.edu dir_cntrl_nodes.append(dir_cntrl) 1863311Ssaidi@eecs.umich.edu 1873311Ssaidi@eecs.umich.edu for i, dma_port in enumerate(dma_ports): 1883311Ssaidi@eecs.umich.edu # 18912448Sgabeblack@google.com # Create the Ruby objects associated with the dma controller 1903311Ssaidi@eecs.umich.edu # 19110905Sandreas.sandberg@arm.com dma_seq = DMASequencer(version = i, 19210905Sandreas.sandberg@arm.com ruby_system = ruby_system) 1933311Ssaidi@eecs.umich.edu 19410905Sandreas.sandberg@arm.com dma_cntrl = DMA_Controller(version = i, 19510905Sandreas.sandberg@arm.com dma_sequencer = dma_seq, 1963311Ssaidi@eecs.umich.edu transitions_per_cycle = options.ports, 19712461Sgabeblack@google.com ruby_system = ruby_system) 19812461Sgabeblack@google.com 19912461Sgabeblack@google.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 20012461Sgabeblack@google.com exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) 20112461Sgabeblack@google.com dma_cntrl_nodes.append(dma_cntrl) 20212461Sgabeblack@google.com 20310905Sandreas.sandberg@arm.com all_cntrls = l1_cntrl_nodes + \ 20412461Sgabeblack@google.com l2_cntrl_nodes + \ 2056818SLisa.Hsu@amd.com dir_cntrl_nodes + \ 2063311Ssaidi@eecs.umich.edu dma_cntrl_nodes 2073311Ssaidi@eecs.umich.edu 208 topology = create_topology(all_cntrls, options) 209 210 return (cpu_sequencers, dir_cntrl_nodes, topology) 211