MOESI_CMP_token.py revision 7015
16908SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26908SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36908SBrad.Beckmann@amd.com# All rights reserved. 46908SBrad.Beckmann@amd.com# 56908SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66908SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76908SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86908SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96908SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106908SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116908SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126908SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136908SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146908SBrad.Beckmann@amd.com# this software without specific prior written permission. 156908SBrad.Beckmann@amd.com# 166908SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176908SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186908SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196908SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206908SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216908SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226908SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236908SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246908SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256908SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266908SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276908SBrad.Beckmann@amd.com# 286908SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296908SBrad.Beckmann@amd.com 306908SBrad.Beckmann@amd.comimport math 316908SBrad.Beckmann@amd.comimport m5 326908SBrad.Beckmann@amd.comfrom m5.objects import * 336908SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 346908SBrad.Beckmann@amd.comfrom m5.util import addToPath 356908SBrad.Beckmann@amd.com 366908SBrad.Beckmann@amd.com# 376908SBrad.Beckmann@amd.com# Note: the L1 Cache latency is only used by the sequencer on fast path hits 386908SBrad.Beckmann@amd.com# 396908SBrad.Beckmann@amd.comclass L1Cache(RubyCache): 406908SBrad.Beckmann@amd.com latency = 3 416908SBrad.Beckmann@amd.com 426908SBrad.Beckmann@amd.com# 436908SBrad.Beckmann@amd.com# Note: the L2 Cache latency is not currently used 446908SBrad.Beckmann@amd.com# 456908SBrad.Beckmann@amd.comclass L2Cache(RubyCache): 466908SBrad.Beckmann@amd.com latency = 15 476908SBrad.Beckmann@amd.com 486908SBrad.Beckmann@amd.comdef create_system(options, phys_mem, piobus, dma_devices): 496908SBrad.Beckmann@amd.com 506908SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_token': 516908SBrad.Beckmann@amd.com panic("This script requires the MOESI_CMP_token protocol to be built.") 526908SBrad.Beckmann@amd.com 536908SBrad.Beckmann@amd.com # 546908SBrad.Beckmann@amd.com # number of tokens that the owner passes to requests so that shared blocks can 556908SBrad.Beckmann@amd.com # respond to read requests 566908SBrad.Beckmann@amd.com # 576908SBrad.Beckmann@amd.com n_tokens = options.num_cpus + 1 586908SBrad.Beckmann@amd.com 596908SBrad.Beckmann@amd.com cpu_sequencers = [] 606908SBrad.Beckmann@amd.com 616908SBrad.Beckmann@amd.com # 626908SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 636908SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 646908SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 656908SBrad.Beckmann@amd.com # 666908SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 676908SBrad.Beckmann@amd.com l2_cntrl_nodes = [] 686908SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 696908SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 706908SBrad.Beckmann@amd.com 716908SBrad.Beckmann@amd.com # 726908SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 736908SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 746908SBrad.Beckmann@amd.com # 756908SBrad.Beckmann@amd.com 766908SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 776908SBrad.Beckmann@amd.com # 786908SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 796908SBrad.Beckmann@amd.com # 806908SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 816908SBrad.Beckmann@amd.com assoc = options.l1i_assoc) 826908SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 836908SBrad.Beckmann@amd.com assoc = options.l1d_assoc) 846908SBrad.Beckmann@amd.com 857015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 867015SBrad.Beckmann@amd.com icache = l1i_cache, 876908SBrad.Beckmann@amd.com dcache = l1d_cache, 886908SBrad.Beckmann@amd.com physMemPort = phys_mem.port, 896908SBrad.Beckmann@amd.com physmem = phys_mem) 906908SBrad.Beckmann@amd.com 916908SBrad.Beckmann@amd.com if piobus != None: 926908SBrad.Beckmann@amd.com cpu_seq.pio_port = piobus.port 936908SBrad.Beckmann@amd.com 946908SBrad.Beckmann@amd.com l1_cntrl = L1Cache_Controller(version = i, 956908SBrad.Beckmann@amd.com sequencer = cpu_seq, 966908SBrad.Beckmann@amd.com L1IcacheMemory = l1i_cache, 976908SBrad.Beckmann@amd.com L1DcacheMemory = l1d_cache, 986908SBrad.Beckmann@amd.com l2_select_num_bits = \ 996908SBrad.Beckmann@amd.com math.log(options.num_l2caches, 2), 1006908SBrad.Beckmann@amd.com N_tokens = n_tokens) 1016908SBrad.Beckmann@amd.com # 1026908SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1036908SBrad.Beckmann@amd.com # 1046908SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1056908SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1066908SBrad.Beckmann@amd.com 1076908SBrad.Beckmann@amd.com for i in xrange(options.num_l2caches): 1086908SBrad.Beckmann@amd.com # 1096908SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 1106908SBrad.Beckmann@amd.com # 1116908SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 1126908SBrad.Beckmann@amd.com assoc = options.l2_assoc) 1136908SBrad.Beckmann@amd.com 1146908SBrad.Beckmann@amd.com l2_cntrl = L2Cache_Controller(version = i, 1156908SBrad.Beckmann@amd.com L2cacheMemory = l2_cache, 1166908SBrad.Beckmann@amd.com N_tokens = n_tokens) 1176908SBrad.Beckmann@amd.com 1186908SBrad.Beckmann@amd.com l2_cntrl_nodes.append(l2_cntrl) 1196908SBrad.Beckmann@amd.com 1206908SBrad.Beckmann@amd.com phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1 1216908SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1226908SBrad.Beckmann@amd.com 1236908SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1246908SBrad.Beckmann@amd.com # 1256908SBrad.Beckmann@amd.com # Create the Ruby objects associated with the directory controller 1266908SBrad.Beckmann@amd.com # 1276908SBrad.Beckmann@amd.com 1286908SBrad.Beckmann@amd.com mem_cntrl = RubyMemoryControl(version = i) 1296908SBrad.Beckmann@amd.com 1306908SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1316908SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1326908SBrad.Beckmann@amd.com 1336908SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 1346908SBrad.Beckmann@amd.com directory = \ 1356908SBrad.Beckmann@amd.com RubyDirectoryMemory(version = i, 1366908SBrad.Beckmann@amd.com size = dir_size), 1376908SBrad.Beckmann@amd.com memBuffer = mem_cntrl, 1386908SBrad.Beckmann@amd.com l2_select_num_bits = \ 1396908SBrad.Beckmann@amd.com math.log(options.num_l2caches, 2)) 1406908SBrad.Beckmann@amd.com 1416908SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1426908SBrad.Beckmann@amd.com 1436908SBrad.Beckmann@amd.com for i, dma_device in enumerate(dma_devices): 1446908SBrad.Beckmann@amd.com # 1456908SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1466908SBrad.Beckmann@amd.com # 1476908SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 1486908SBrad.Beckmann@amd.com physMemPort = phys_mem.port, 1496908SBrad.Beckmann@amd.com physmem = phys_mem) 1506908SBrad.Beckmann@amd.com 1516908SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1526908SBrad.Beckmann@amd.com dma_sequencer = dma_seq) 1536908SBrad.Beckmann@amd.com 1546908SBrad.Beckmann@amd.com dma_cntrl.dma_sequencer.port = dma_device.dma 1556908SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 1566908SBrad.Beckmann@amd.com 1576908SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + \ 1586908SBrad.Beckmann@amd.com l2_cntrl_nodes + \ 1596908SBrad.Beckmann@amd.com dir_cntrl_nodes + \ 1606908SBrad.Beckmann@amd.com dma_cntrl_nodes 1616908SBrad.Beckmann@amd.com 1626908SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, all_cntrls) 163