MOESI_CMP_directory.py revision 11065
16911SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26911SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 36911SBrad.Beckmann@amd.com# All rights reserved. 46911SBrad.Beckmann@amd.com# 56911SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 66911SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 76911SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 86911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 96911SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 106911SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 116911SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 126911SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 136911SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 146911SBrad.Beckmann@amd.com# this software without specific prior written permission. 156911SBrad.Beckmann@amd.com# 166911SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176911SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186911SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196911SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206911SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216911SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226911SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236911SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246911SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256911SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266911SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276911SBrad.Beckmann@amd.com# 286911SBrad.Beckmann@amd.com# Authors: Brad Beckmann 296911SBrad.Beckmann@amd.com 306911SBrad.Beckmann@amd.comimport math 316911SBrad.Beckmann@amd.comimport m5 326911SBrad.Beckmann@amd.comfrom m5.objects import * 336911SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 349100SBrad.Beckmann@amd.comfrom Ruby import create_topology 3510529Smorr@cs.wisc.edufrom Ruby import send_evicts 366911SBrad.Beckmann@amd.com 376911SBrad.Beckmann@amd.com# 3811019Sjthestness@gmail.com# Declare caches used by the protocol 396911SBrad.Beckmann@amd.com# 4011019Sjthestness@gmail.comclass L1Cache(RubyCache): pass 4111019Sjthestness@gmail.comclass L2Cache(RubyCache): pass 426911SBrad.Beckmann@amd.com 437538SBrad.Beckmann@amd.comdef define_options(parser): 447538SBrad.Beckmann@amd.com return 457538SBrad.Beckmann@amd.com 4610519Snilay@cs.wisc.edudef create_system(options, full_system, system, dma_ports, ruby_system): 478436SBrad.Beckmann@amd.com 486911SBrad.Beckmann@amd.com if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': 496911SBrad.Beckmann@amd.com panic("This script requires the MOESI_CMP_directory protocol to be built.") 506911SBrad.Beckmann@amd.com 516911SBrad.Beckmann@amd.com cpu_sequencers = [] 5210917Sbrandon.potter@amd.com 536911SBrad.Beckmann@amd.com # 546911SBrad.Beckmann@amd.com # The ruby network creation expects the list of nodes in the system to be 556911SBrad.Beckmann@amd.com # consistent with the NetDest list. Therefore the l1 controller nodes must be 566911SBrad.Beckmann@amd.com # listed before the directory nodes and directory nodes before dma nodes, etc. 576911SBrad.Beckmann@amd.com # 586911SBrad.Beckmann@amd.com l1_cntrl_nodes = [] 596911SBrad.Beckmann@amd.com l2_cntrl_nodes = [] 606911SBrad.Beckmann@amd.com dir_cntrl_nodes = [] 616911SBrad.Beckmann@amd.com dma_cntrl_nodes = [] 626911SBrad.Beckmann@amd.com 636911SBrad.Beckmann@amd.com # 646911SBrad.Beckmann@amd.com # Must create the individual controllers before the network to ensure the 656911SBrad.Beckmann@amd.com # controller constructors are called before the network constructor 666911SBrad.Beckmann@amd.com # 678180SBrad.Beckmann@amd.com l2_bits = int(math.log(options.num_l2caches, 2)) 688180SBrad.Beckmann@amd.com block_size_bits = int(math.log(options.cacheline_size, 2)) 698257SBrad.Beckmann@amd.com 706911SBrad.Beckmann@amd.com for i in xrange(options.num_cpus): 716911SBrad.Beckmann@amd.com # 726911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 736911SBrad.Beckmann@amd.com # 746911SBrad.Beckmann@amd.com l1i_cache = L1Cache(size = options.l1i_size, 758180SBrad.Beckmann@amd.com assoc = options.l1i_assoc, 769319Smalek.musleh@gmail.com start_index_bit = block_size_bits, 779319Smalek.musleh@gmail.com is_icache = True) 786911SBrad.Beckmann@amd.com l1d_cache = L1Cache(size = options.l1d_size, 798180SBrad.Beckmann@amd.com assoc = options.l1d_assoc, 809319Smalek.musleh@gmail.com start_index_bit = block_size_bits, 819319Smalek.musleh@gmail.com is_icache = False) 826911SBrad.Beckmann@amd.com 838322Ssteve.reinhardt@amd.com l1_cntrl = L1Cache_Controller(version = i, 849694Snilay@cs.wisc.edu L1Icache = l1i_cache, 859694Snilay@cs.wisc.edu L1Dcache = l1d_cache, 868436SBrad.Beckmann@amd.com l2_select_num_bits = l2_bits, 8710529Smorr@cs.wisc.edu send_evictions = send_evicts(options), 889841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 8910300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 908436SBrad.Beckmann@amd.com ruby_system = ruby_system) 918322Ssteve.reinhardt@amd.com 927015SBrad.Beckmann@amd.com cpu_seq = RubySequencer(version = i, 937015SBrad.Beckmann@amd.com icache = l1i_cache, 946911SBrad.Beckmann@amd.com dcache = l1d_cache, 9510300Scastilloe@unican.es clk_domain=system.cpu[i].clk_domain, 968436SBrad.Beckmann@amd.com ruby_system = ruby_system) 976911SBrad.Beckmann@amd.com 988322Ssteve.reinhardt@amd.com l1_cntrl.sequencer = cpu_seq 9910116Snilay@cs.wisc.edu exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 1008322Ssteve.reinhardt@amd.com 1016911SBrad.Beckmann@amd.com # Add controllers and sequencers to the appropriate lists 1026911SBrad.Beckmann@amd.com cpu_sequencers.append(cpu_seq) 1036911SBrad.Beckmann@amd.com l1_cntrl_nodes.append(l1_cntrl) 1046911SBrad.Beckmann@amd.com 10510311Snilay@cs.wisc.edu # Connect the L1 controllers and the network 10611022Sjthestness@gmail.com l1_cntrl.mandatoryQueue = MessageBuffer() 10711022Sjthestness@gmail.com l1_cntrl.requestFromL1Cache = MessageBuffer() 10811022Sjthestness@gmail.com l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave 10911022Sjthestness@gmail.com l1_cntrl.responseFromL1Cache = MessageBuffer() 11011022Sjthestness@gmail.com l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave 11111022Sjthestness@gmail.com l1_cntrl.requestToL1Cache = MessageBuffer() 11211022Sjthestness@gmail.com l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 11311022Sjthestness@gmail.com l1_cntrl.responseToL1Cache = MessageBuffer() 11411022Sjthestness@gmail.com l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 11511022Sjthestness@gmail.com l1_cntrl.triggerQueue = MessageBuffer(ordered = True) 11610311Snilay@cs.wisc.edu 11710311Snilay@cs.wisc.edu 1188180SBrad.Beckmann@amd.com l2_index_start = block_size_bits + l2_bits 1198180SBrad.Beckmann@amd.com 1206911SBrad.Beckmann@amd.com for i in xrange(options.num_l2caches): 1216911SBrad.Beckmann@amd.com # 1226911SBrad.Beckmann@amd.com # First create the Ruby objects associated with this cpu 1236911SBrad.Beckmann@amd.com # 1246911SBrad.Beckmann@amd.com l2_cache = L2Cache(size = options.l2_size, 1258180SBrad.Beckmann@amd.com assoc = options.l2_assoc, 1268180SBrad.Beckmann@amd.com start_index_bit = l2_index_start) 1276911SBrad.Beckmann@amd.com 1286911SBrad.Beckmann@amd.com l2_cntrl = L2Cache_Controller(version = i, 1299694Snilay@cs.wisc.edu L2cache = l2_cache, 1309841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1318436SBrad.Beckmann@amd.com ruby_system = ruby_system) 13210917Sbrandon.potter@amd.com 1339468Smalek.musleh@gmail.com exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 1346911SBrad.Beckmann@amd.com l2_cntrl_nodes.append(l2_cntrl) 1358257SBrad.Beckmann@amd.com 13610311Snilay@cs.wisc.edu # Connect the L2 controllers and the network 13711022Sjthestness@gmail.com l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() 13811022Sjthestness@gmail.com l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave 13911022Sjthestness@gmail.com l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 14011022Sjthestness@gmail.com l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 14111022Sjthestness@gmail.com l2_cntrl.responseFromL2Cache = MessageBuffer() 14211022Sjthestness@gmail.com l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 14310311Snilay@cs.wisc.edu 14411022Sjthestness@gmail.com l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() 14511022Sjthestness@gmail.com l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master 14611022Sjthestness@gmail.com l2_cntrl.L1RequestToL2Cache = MessageBuffer() 14711022Sjthestness@gmail.com l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 14811022Sjthestness@gmail.com l2_cntrl.responseToL2Cache = MessageBuffer() 14911022Sjthestness@gmail.com l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 15011022Sjthestness@gmail.com l2_cntrl.triggerQueue = MessageBuffer(ordered = True) 15110311Snilay@cs.wisc.edu 15210311Snilay@cs.wisc.edu 1539826Sandreas.hansson@arm.com phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 1549798Snilay@cs.wisc.edu assert(phys_mem_size % options.num_dirs == 0) 1556911SBrad.Beckmann@amd.com mem_module_size = phys_mem_size / options.num_dirs 1566911SBrad.Beckmann@amd.com 15710311Snilay@cs.wisc.edu 1589793Sakash.bagdia@arm.com # Run each of the ruby memory controllers at a ratio of the frequency of 1599793Sakash.bagdia@arm.com # the ruby system. 1609793Sakash.bagdia@arm.com # clk_divider value is a fix to pass regression. 1619793Sakash.bagdia@arm.com ruby_system.memctrl_clk_domain = DerivedClockDomain( 1629793Sakash.bagdia@arm.com clk_domain=ruby_system.clk_domain, 1639793Sakash.bagdia@arm.com clk_divider=3) 1649793Sakash.bagdia@arm.com 1656911SBrad.Beckmann@amd.com for i in xrange(options.num_dirs): 1666911SBrad.Beckmann@amd.com dir_size = MemorySize('0B') 1676911SBrad.Beckmann@amd.com dir_size.value = mem_module_size 1686911SBrad.Beckmann@amd.com 1696911SBrad.Beckmann@amd.com dir_cntrl = Directory_Controller(version = i, 17010524Snilay@cs.wisc.edu directory = RubyDirectoryMemory( 17110524Snilay@cs.wisc.edu version = i, size = dir_size), 1729841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 1738436SBrad.Beckmann@amd.com ruby_system = ruby_system) 1746911SBrad.Beckmann@amd.com 1759468Smalek.musleh@gmail.com exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 1766911SBrad.Beckmann@amd.com dir_cntrl_nodes.append(dir_cntrl) 1776911SBrad.Beckmann@amd.com 17810311Snilay@cs.wisc.edu # Connect the directory controllers and the network 17911022Sjthestness@gmail.com dir_cntrl.requestToDir = MessageBuffer() 18011022Sjthestness@gmail.com dir_cntrl.requestToDir.slave = ruby_system.network.master 18111022Sjthestness@gmail.com dir_cntrl.responseToDir = MessageBuffer() 18211022Sjthestness@gmail.com dir_cntrl.responseToDir.slave = ruby_system.network.master 18311022Sjthestness@gmail.com dir_cntrl.responseFromDir = MessageBuffer() 18411022Sjthestness@gmail.com dir_cntrl.responseFromDir.master = ruby_system.network.slave 18511022Sjthestness@gmail.com dir_cntrl.forwardFromDir = MessageBuffer() 18611022Sjthestness@gmail.com dir_cntrl.forwardFromDir.master = ruby_system.network.slave 18711022Sjthestness@gmail.com dir_cntrl.responseFromMemory = MessageBuffer() 18810311Snilay@cs.wisc.edu 18910311Snilay@cs.wisc.edu 1908929Snilay@cs.wisc.edu for i, dma_port in enumerate(dma_ports): 1916911SBrad.Beckmann@amd.com # 1926911SBrad.Beckmann@amd.com # Create the Ruby objects associated with the dma controller 1936911SBrad.Beckmann@amd.com # 1946911SBrad.Beckmann@amd.com dma_seq = DMASequencer(version = i, 19510519Snilay@cs.wisc.edu ruby_system = ruby_system, 19610519Snilay@cs.wisc.edu slave = dma_port) 19710917Sbrandon.potter@amd.com 1986911SBrad.Beckmann@amd.com dma_cntrl = DMA_Controller(version = i, 1998477Snilay@cs.wisc.edu dma_sequencer = dma_seq, 2009841Snilay@cs.wisc.edu transitions_per_cycle = options.ports, 2018477Snilay@cs.wisc.edu ruby_system = ruby_system) 2026911SBrad.Beckmann@amd.com 2039468Smalek.musleh@gmail.com exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 2046911SBrad.Beckmann@amd.com dma_cntrl_nodes.append(dma_cntrl) 2058257SBrad.Beckmann@amd.com 20610519Snilay@cs.wisc.edu # Connect the dma controller to the network 20711022Sjthestness@gmail.com dma_cntrl.mandatoryQueue = MessageBuffer() 20811022Sjthestness@gmail.com dma_cntrl.responseFromDir = MessageBuffer() 20911022Sjthestness@gmail.com dma_cntrl.responseFromDir.slave = ruby_system.network.master 21011022Sjthestness@gmail.com dma_cntrl.reqToDir = MessageBuffer() 21111022Sjthestness@gmail.com dma_cntrl.reqToDir.master = ruby_system.network.slave 21211022Sjthestness@gmail.com dma_cntrl.respToDir = MessageBuffer() 21311022Sjthestness@gmail.com dma_cntrl.respToDir.master = ruby_system.network.slave 21411022Sjthestness@gmail.com dma_cntrl.triggerQueue = MessageBuffer(ordered = True) 21510519Snilay@cs.wisc.edu 21610311Snilay@cs.wisc.edu 2176911SBrad.Beckmann@amd.com all_cntrls = l1_cntrl_nodes + \ 2186911SBrad.Beckmann@amd.com l2_cntrl_nodes + \ 2196911SBrad.Beckmann@amd.com dir_cntrl_nodes + \ 2206911SBrad.Beckmann@amd.com dma_cntrl_nodes 2216911SBrad.Beckmann@amd.com 22210519Snilay@cs.wisc.edu # Create the io controller and the sequencer 22310519Snilay@cs.wisc.edu if full_system: 22410519Snilay@cs.wisc.edu io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 22510519Snilay@cs.wisc.edu ruby_system._io_port = io_seq 22610519Snilay@cs.wisc.edu io_controller = DMA_Controller(version = len(dma_ports), 22710519Snilay@cs.wisc.edu dma_sequencer = io_seq, 22810519Snilay@cs.wisc.edu ruby_system = ruby_system) 22910519Snilay@cs.wisc.edu ruby_system.io_controller = io_controller 23010519Snilay@cs.wisc.edu 23110519Snilay@cs.wisc.edu # Connect the dma controller to the network 23211022Sjthestness@gmail.com io_controller.mandatoryQueue = MessageBuffer() 23311022Sjthestness@gmail.com io_controller.responseFromDir = MessageBuffer() 23411022Sjthestness@gmail.com io_controller.responseFromDir.slave = ruby_system.network.master 23511022Sjthestness@gmail.com io_controller.reqToDir = MessageBuffer() 23611022Sjthestness@gmail.com io_controller.reqToDir.master = ruby_system.network.slave 23711022Sjthestness@gmail.com io_controller.respToDir = MessageBuffer() 23811022Sjthestness@gmail.com io_controller.respToDir.master = ruby_system.network.slave 23911022Sjthestness@gmail.com io_controller.triggerQueue = MessageBuffer(ordered = True) 24010519Snilay@cs.wisc.edu 24110519Snilay@cs.wisc.edu all_cntrls = all_cntrls + [io_controller] 24210519Snilay@cs.wisc.edu 24310519Snilay@cs.wisc.edu 24411065Snilay@cs.wisc.edu ruby_system.network.number_of_virtual_networks = 3 2459100SBrad.Beckmann@amd.com topology = create_topology(all_cntrls, options) 2469100SBrad.Beckmann@amd.com return (cpu_sequencers, dir_cntrl_nodes, topology) 247